KR100276079B1 - A cell spacer using bucket calendar and its cotrol method - Google Patents

Abstract

A cell spacer of an ATM matching device, which measures a CDV generated in a system, removes the CDV, and transmits the cell to the other party, thereby removing the CDV so that the cell can be delivered to the end user without cell loss. To provide a control method. The present invention constitutes a cell spacer including a bucket calendar having a bucket acting like an FIFO for storing a buffer address of an output cell for each cell slot and an emitting FIFO, wherein the bucket is registered in the cell slot. It consists of one cell counter indicating the number of cells and seven cell pointers for registering the cell buffer address where the cells are stored. The cell spacer receives an ATM cell, a CDV, and a cell arrival time t. When a cell is input to the cell buffer, it is stored in the cell buffer, and the stored cell buffer address is registered in the bucket of the slot that is CDV later than the current time, and when the output time is reached, the cell buffer address registered in the corresponding slot is stored. Cell spacer of ATM matching device to perform spacing by delaying input cell by CDV in such a way as to read cell and outputting cell Provide control method. Therefore, the cell spacer proposed in the present invention has a simple control structure, and since the bucket can be configured using a simple RAM, the cell spacer can be simply and efficiently configured.

Description

Cell spacer and its control method using bucket calendar

According to an aspect of the present invention, there is provided a cell spacer device for removing a cell delay variation (CDV) generated in a multiplexing process so that a cell can be delivered to an end user without cell loss. It is for.

In general, the ATM matching apparatus monitors the speed of a cell input from all users so that a good subscriber does not suffer from network congestion caused by transmitting a cell having a higher band than a negotiated band. It detects cells that enter the band higher than the negotiated band and discards them, and has a cell speed monitoring function to prevent network congestion by malicious subscribers.

However, in the speed monitoring function of the matching device, it is determined that the negotiated band is observed and when a cell delivered to the network passes through a multiplexing device such as a switch, a new cell delay variation (CDV) is generated during the multiplexing process and outputted to the matching device. A violation of the negotiated band may occur instantaneously. In this case, although the user correctly transmits the cell in compliance with the negotiation bandwidth, due to the CDV generated by the network, the cell is discarded because the next node is considered to be in violation of the negotiated band and the cell is lost when the end user receives the cell. Will occur.

To prevent this, ATM matching device removes CDV by measuring CDV generated in the system when cell is output and removes CDV and transmits cell to the other party so that cell can be delivered to end user without cell loss. Cell spacers should be constructed.

Conventional cell spacers record the position of the cell in memory behind the current output calendar by CDV when recording the location where the cell is stored in a memory called calendar memory to delay the cell by CDV. The device configures the cell spacers in order to read and output the cells registered in the calendar.

However, when you register a cell in calendar memory that adds the CDV to the current time to delay the CDV, if the location is already occupied by another cell, it is stored in the next memory. In this way, the output time of the cell was registered. In order to do this, a time is needed to find unoccupied memory in the calendar memory after the output time, so a queue for registering with the calendar is needed. The problem of cell transfer order may be reversed due to the inconsistency of the cell timer. Can be.

In the present invention, in order to solve the problem described above, a queue is used to guarantee the cell transmission order and to wait for an unoccupied cell slot by using a bucket calendar having a separate queue for each cell time instead of a calendar using a simple memory. It is an object to provide a cell spacer using a bucket calendar to eliminate.

In order to achieve the above object, the present invention provides a cell spacer including a bucket calendar having a bucket acting like an FIFO for storing a buffer address of an output cell for each cell slot, and a discharge FIFO, wherein the bucket includes: It consists of one cell counter indicating the number of cells registered in the corresponding cell slot and seven cell pointers for registering the cell buffer address in which the cell is stored. The cell spacer is composed of ATM cell, CDV, and cell arrival time t. When the cell is input at any time, the cell buffer address is stored in the cell buffer, and the stored cell buffer address is registered in the bucket of the slot that is CDV later than the current time. ATM is configured to delay the input cell by CDV by reading the registered cell buffer address and outputting the cell. By providing a cell spacer of the matching device and a control method thereof.

1 is a block diagram of an ATM matching device for applying the present invention.

2 is a block diagram of a transmission cell processing unit of an ATM matching device for applying the present invention.

Figure 3 is a cell spacer configuration using a VSA for applying the present invention.

4 is a flow chart of the VSA algorithm of the present invention.

Figure 5 is a cell spacer configuration using a conventional simple calendar.

Figure 6 is a cell spacer configuration using a bucket calendar of the present invention.

7 is a configuration of a bucket calendar of the present invention.

<Description of the code | symbol about the principal part of drawing>

1: subscriber line 2: physical layer processing unit

3: receiving cell processing section 4: transmitting cell processing section

5 switch link matching unit 6 switch link

7: control unit 9: connection identifier management unit

10 cell spacer 11 output cell processor

12: VSA engine 13: spacer

23: write control unit 24: cell buffer

25 read control 26 idle FIFO

30: calendar control unit 31: bucket calendar

32: emission FIFO 33: spacer control unit

Hereinafter, the configuration and operation of the present invention through the accompanying drawings will be described in detail.

1 shows a configuration of a matching device of an ATM switch for applying the present invention. The ATM matching device includes a physical layer processing section 2, a receiving cell processing section 3, a transmitting cell processing section 4, a switch link matching section 5, a control section 7 and the like.

The physical layer processor 2 restores data and clocks from the signal received from the subscriber line 1, extracts a frame according to the type of the subscriber line 1, processes the frame, and extracts an ATM cell, thereby extracting the received cell processor ( 3) or the ATM cell received by the transmitting cell processor 4 generates a frame according to the type of subscriber, and loads the ATM cell in the frame to the subscriber through the subscriber line (1).

When the receiving cell processing unit 3 is informed that the cell has been received from the physical layer processing unit 2, the corresponding physical layer processing unit 2 reads and multiplexes the cell, converts the header of the receiving cell using the receiving connection information, and switches Transfer to link matching section 5.

The switch link matching unit 5 receives the cell from the reception cell processing unit 3, converts the cell into a form used by the switch link 6, and transmits the cell to the switch link 6. In addition, when the cell is received from the switch link 6, the cell transmits the cell to the transmitting cell processing section 4.

The transmission cell processing section 4 multiplexes the user cell received from the switch link matching section 5 and the management cell received from the control section 7, selects an output line according to the transmission connection information, and selects the corresponding physical layer processing section 2. Pass the cell to

The control unit 7 manages the state of the physical layer processing unit 2, manages the reception connection information in the reception cell processing unit 3, and manages the transmission connection information of the transmission cell processing unit 4.

2 shows a detailed configuration of the transmission cell processing section 4 to which the present invention is applied.

The transmission cell processing unit 4 is composed of a connection identifier management unit 9, a cell spacer unit 10, and an output cell processing unit 11.

When receiving the cell from the switch link matching unit, the connection identifier managing unit 9 extracts the connection identifier by referring to the VPI and VCI of the cell and transfers the connection identifier and the cell data to the cell spacer unit 10. The cell spacer 10 calculates the CDV of the input cell, adjusts the output speed of the cell by the calculated CDV, and transmits the output speed to the output cell processor 11. The output cell processor 11 performs an OAM function such as monitoring the performance of the cell received by the cell spacer 10, finds an output line, and outputs the cell to the physical layer processor.

3 shows a detailed configuration of the cell spacer 10 to which the present invention is applied.

The cell spacer 10 includes a VSA (Virtual Scheduling Algorithm) engine 12 that performs speed monitoring of an input cell and calculates a CDV, and a spacer 13 that performs spacing by delaying the input cell by CDV. do.

When the VSA engine 12 receives the connection identifier and the ATM cell from the connection identifier manager 9, the VSA engine 12 reads the parameters stored as a result of the speed monitoring for the connection from the parameter table for the connection using the connection identifier. According to the flowchart shown in FIG. 4, cell rate monitoring is performed and CDV is calculated.

As shown in Figure 4, the procedure for calculating the CDV is as follows.

When a cell for any connection arrives at time t (S41), it is checked whether the previous cell arrival time (hereinafter referred to as TAT) has expired (S42). A previous cell arrival time has expired, meaning that the cell has not been entered for a time significantly greater than the negotiated minimum cell interval T. Therefore, the connection expired means that the input cell did not violate the negotiated band, in which case the CDV is zero.

If it has not expired, the TAT, the theoretical time the previous cell of the connection arrived, is added to the minimum cell interval T (X = TAT + T) (S43), to check if the sum is less than the current time t (X <t? (S44). A smaller value than t means that the cell has been input larger than the minimum cell spacing, and this time indicates that the cell has been entered without violating the negotiated bandwidth. The CDV at this time is also zero (S49).

However, if it is larger than t, it means that the cell has been entered with a cell interval smaller than the negotiated minimum cell interval, thus violating the negotiated cell rate.

However, when negotiating cell rate, the cell negotiates Cell Delay Variance Tolerance of PCR (τV) considering CDV generated through various multiplexing devices. Therefore, it checks again whether the input cell violates the CDVT. In order to check the CDVT, it is checked whether the current time t plus the CDVT (= τ) is greater than TAT + T (S45). If t + τ is smaller than TAT + T (= X), the cell is discarded because the cell is input beyond the negotiated bandwidth and the allowed CDV (S48).

Otherwise, the cell rate is violated, but the CDV is calculated because the cell is input without violating the allowed CDV (S46). CDV is the theoretical arrival time TAT + T minus the current time t (CDV = X-t). If the cell rate and the CDV are not violated, the TAT is stored as a TAT + T value or the current time t, and the cell and the CDV are output (S47).

The VSA engine 12 delivers the CDV, the current time t, and the cell calculated in the above manner to the spacer 13.

FIG. 5 shows a detailed configuration diagram of a spacer using a calendar composed of a DPRAM that has been used in the past, and FIG. 6 shows a configuration of a spacer using a bucket calendar to which the present invention is applied.

The spacer 13 is composed of a spacer controller 33 for controlling the spacing of the cell and a cell buffer 24 for storing the cell. The spacer controller 33 is composed of a field programmable gate array (FPGA). 24 is composed of dual port RAM (DPRAM).

First, the operation of the spacer controller 33 shown in FIG. 5 will be described.

The write control unit 23 of the spacer controller 33 receives the cell data, the calculated CDV, and the current time t from the VSA engine as an input from an idle FIFO 26 storing an unoccupied idle address of the cell buffer. The idle address is read, the cell is written to the cell buffer 24 of the corresponding write address waddr, and the CDV and the write address waddr are stored in the CDV FIFO 27.

If there is data stored in the CDV FIFO 27, the calendar control unit 28 reads the CDV and the cell buffer address in which the cells are stored in the CDV FIFO 27, and the calendar 29 after the current time t by CDV. The memory is read to see if there is a cell already registered in the slot. If not, the cell buffer address is recorded and the slot is occupied. If the slot is already occupied by another cell, the next address is read sequentially to find an empty slot and register the cell.

The read control unit 25 reads the calendar memory of the current time and, if the cell is registered, reads the cell from the cell buffer using the registered cell buffer address and outputs the cell buffer address to the idle FIFO. If no cell is registered, output an idle cell. Here, the current time t increases by 1 every cell time.

The cell spacer of this method can be implemented using a relatively small memory because the controller is relatively simple and the calendar memory needs to be as large as the CDV allowed by the system.

However, if a collision occurs in calendar memory, the next memory must be searched until an empty slot is found, and thus, the CDV FIFO 27 may be required. The order may be reversed.

The operation of the cell spacer controller 33 to which the present invention shown in FIG. 6 is applied to solve such a problem is as follows. Here, instead of the CDV FIFO 27 and the calendar memory 29, each of the cell slots stores a bucket calendar 31 having a bucket acting as an FIFO which stores the buffer address of the output cell, and the buffer address of the output cell. It has an emitting FIFO 32.

As described in FIG. 5, the write control unit 23 reads the idle address from the idle address FIFO 26, stores the cell in the cell buffer 24, and transfers the CDV and the buffer address to the calendar control unit 30.

The calendar control unit 30 stores the buffer address in the bucket at the current time t plus the CDV. In addition, all buffer addresses registered in the bucket of the current time are read and stored in the discharge FIFO 32.

On the other hand, the read control unit 25 takes the address of the cell buffer to be output from the emission FIFO 32, reads out the cell in the cell buffer 24 and outputs it, and stores the buffer address in the idle FIFO 26.

The structure and operation of the bucket calendar 31 used herein will be described in more detail. The structure of the bucket calendar 31 is configured using a general RAM as shown in FIG. 7 and is registered for each cell slot. It consists of a cell counter indicating the number of cells present and a bucket 34 for registering the cell buffer address in which the cell is stored.

If a cell is input at any time t, and CDV is Δ, then the memory at (t + Δ) * 8 is read to know the number of cells registered in the corresponding cell slot. Here, if the number of cells read is n, n + 1 is rewritten in (t + Δ) * 8, and the cell buffer address is written in (t + Δ) * 8 + n + 1. Ends.

The procedure for reading the cell pointer in the bucket calendar reads the cell counter registered at t * 8 at any time t, stores the counter, and reads the cell pointer from t * 8 + 1 until the counter becomes 0. 32). When the counter is read, if the counter is 0, it indicates that there is no cell to output in the corresponding slot, so no action is taken.

The present invention does not violate the transmission band negotiated between the user and the network in a virtual connection in the ATM network, the cell is transmitted in violation of the bandwidth due to the CDV generated while passing through the transmission device of the network, such as switches, multiplexers, etc. In configuring the cell spacer for preventing the cell spacer, the cell spacer is configured using the bucket calendar, thereby eliminating the cell output time registration delay and the change of the cell transmission order.

In particular, the bucket calendar configured in the present invention provides a structure for configuring a FIFO for each transmission slot using a general RAM structure, thereby simplifying the control structure.

Therefore, according to the present invention, it is possible to efficiently construct a cell calendar of a bucket calendar structure using a general FPGA which is commonly used.

Claims (6)

A cell spacer which calculates a CDV of a cell input in a matching device of an ATM exchanger, adjusts an output speed of a cell by a calculated CDV, and delivers the result to a physical layer processor through an output cell processor. The cell spacer is When receiving the connection identifier and the ATM cell from the connection identifier management unit 9 which receives the ATM cell from the switch link matching unit and manages the connection identifier, the speed monitoring for the connection is performed from the parameter table for the connection using the connection identifier. A VSA engine 12 which performs cell rate monitoring by reading the result stored parameters and calculates a CDV; It receives ATM cell, CDV, and cell arrival time t from the VSA engine 12, and if a cell is input at any time, it is stored in the cell buffer, and the stored cell buffer address of the slot that is CDV behind the current time. The spacer 13 registers the cell buffer address in the bucket and outputs the cell by reading the cell buffer address registered in the corresponding slot, and delays the input cell by CDV to perform spacing. Cell spacer using a bucket calendar. The method of claim 1, wherein the spacer 13, A spacer controller 33 for controlling the spacing of the cells, A cell buffer 24 for storing cells, The spacer controller 33, A cell is written from the VSA engine, the CDV and the current time t are input, and a cell is written to the cell buffer 24 using the unoccupied idle address of the cell buffer 24 as a write address, and the CDV and the write are written. A write control unit 23 for transmitting the address waddr to the bucket calendar 30, A bucket calendar 31 including a bucket that acts like a FIFO for storing buffer addresses of output cells in each cell slot; An emission FIFO 32 storing a buffer address of an output cell, The CDV and the address are received from the write control unit, the buffer address is stored in the bucket calendar 31 at the time of adding the CDV to the current time t, and all the buffer addresses registered in the bucket at the current time are read. A calendar control unit 30 to store in 32; A read control unit 25 which obtains an address of a cell buffer to be output from the emission FIFO 32 and reads and outputs a cell in the cell buffer 24; And an idle FIFO (26) for receiving the output buffer address from the read control unit (25) and storing it as an idle address for the write control unit (23) to read. The structure of claim 2, wherein the bucket calendar 31 is It consists of multiple cell slots using normal RAM One cell slot, A cell using a bucket calendar, characterized in that it comprises one cell counter indicating the number of cells registered in the corresponding cell slot and a bucket 34 comprising a plurality of cell pointers for registering a cell buffer address where the cell is stored. Spacer. A method of controlling a cell spacer for removing a CDV generated in a system in a cell in an ATM matching device, Using the connection identifier, read the parameter stored as the result of the speed monitoring for the connection from the parameter table for the connection, monitor the cell speed, calculate the CDV, Each cell slot constitutes a cell calendar including a bucket calendar having a bucket acting like a FIFO storing a buffer address of an output cell and an emitting FIFO, The cell spacer receives the ATM cell, the CDV, and the cell arrival time t. If the cell is input at any time, it is stored in the cell buffer, and the stored cell buffer address is stored in the bucket of the slot that is CDV later than the current time. Registering the buffer address and reading the cell buffer address registered in the corresponding slot and outputting the cell when the output time arrives, thereby delaying the input cell by CDV to perform spacing for cell matching. Way. The method of claim 4, wherein the method of registering a cell buffer address with the bucket comprises: The bucket is composed of one cell counter indicating the number of cells registered in the corresponding cell slot and seven cell pointers for registering the cell buffer address where the cell is stored. If a cell is input at any time t, and CDV is Δ, To know the number of cells registered in the corresponding cell slot, read the memory in (t + Δ) * 8, If the number of cells read is n, write n + 1 again in (t + Δ) * 8, A cell spacer control method for an ATM matching device, comprising registering a cell in a bucket calendar by writing a cell buffer address in (t + Δ) * 8 + n + 1. The method of claim 5, wherein the registered cell buffer address is read. Read the cell counter registered at t * 8 at any time t, and save the counter. From t * 8 + 1, the cell pointer is read and stored in the emission FIFO until the counter becomes zero. If the counter is 0 when the counter is read, it indicates that there is no cell to output to the corresponding slot, and thus does not take action.