KR100242470B1 - Semiconductor memory device and its fabricating method - Google Patents

Abstract

The present invention is to increase the capacitor capacity of the DRAM, to form an interlayer insulating film on the semiconductor substrate on which the device is formed to planarize the surface, and different etching rates for a predetermined etching agent on the interlayer insulating film Forming an insulating film pattern having a stacked structure by selectively etching the stacked insulating films, forming a first conductive layer on an entire surface of the substrate, and forming the first conductive layer on the substrate. Selectively etching the insulating layer pattern and the interlayer insulating layer having a stacked structure to form a contact hole exposing a predetermined portion of the substrate, forming a curved side of the contact hole, and forming a second conductive layer on the entire surface of the substrate; And selectively etching the first conductive layer and the second conductive layer.

Description

Semiconductor Memory Device Manufacturing Method

1 is a process flowchart showing a method of manufacturing a semiconductor memory device according to the first embodiment of the present invention.

2 is a process flowchart showing a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: interlayer insulating film 11: first insulating film

12 second insulating film 13 insulating film pattern

14: first conductive layer 15: contact hole

16: second conductive layer 17: capacitor lower electrode

18 dielectric layer 19 capacitor upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a capacitor manufacturing method capable of increasing a capacitor capacity of a DRAM (Dynamic Random Access Memory).

As DRAMs become more integrated, studies are underway to obtain larger capacitances in smaller areas. Among them, a stack structure capacitor, a fin structure capacitor, a finger structure capacitor, and the like are conventional techniques of changing a structure of a capacitor to form a large capacity capacitor. However, because the stacked capacitor occupies a large area in the memory device, it is difficult to secure the capacitor capacity required for the highly integrated device because the capacitor size needs to be reduced according to the increase in the density of the integrated device. Although it is advantageous in terms of securing, there is a problem of increasing the overall step to make the subsequent photo etching process difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a method of manufacturing a capacitor of a semiconductor memory device capable of suppressing an increase in a step according to capacitor formation while increasing a capacitor capacity.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a first step of forming an interlayer insulating film on an upper surface of a semiconductor substrate on which transistors and bit lines are formed; Stacking at least two layers of insulating layers having different etching rates with respect to a predetermined etching agent on the interlayer insulating layer; Selectively etching the stacked insulating films to form an insulating film pattern having a stacked structure; A fourth step of forming a first conductive layer on the semiconductor substrate on which the third step is completed; Forming a contact hole exposing the semiconductor substrate by selectively etching the first conductive layer, the insulating layer pattern, and the interlayer insulating layer; A sixth step of forming a bend in the side surface of the contact hole by treating the insulating layer pattern exposed on the side surface of the contact hole with the etchant; A seventh step of forming a second conductive layer on the contact hole bottom, side surfaces, and the first conductive layer; The second conductive layer and the first conductive layer may be selectively etched, and ends thereof may cover the insulating layer pattern and the interlayer insulating layer around the contact hole, and a center thereof may cover the sidewalls and the bottom of the contact hole, thereby forming an upper portion of the interlayer insulating layer. An eighth step of forming a lower electrode having a curvature in a direction parallel to the semiconductor substrate and having a curvature on the sidewall of the contact hole; And a ninth step of forming a dielectric film and an upper electrode on the lower electrode.

In the third step, at least one insulating layer pattern is formed.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 (a) to 1 (f) illustrate a method of manufacturing a capacitor of a semiconductor memory device according to a first embodiment of the present invention according to a process sequence. Hereinafter, a method of manufacturing a capacitor of a semiconductor memory device will be described.

First, as shown in FIG. 1 (a), a bit line is formed through the same process as a conventional DRAM capacitor manufacturing process. That is, the gate oxide film 3 and the gate electrode 4 are formed in a predetermined region on the semiconductor substrate 1 divided into the active region and the device isolation region by the field oxide film 2, and sidewalls are formed on the sidewalls of the gate electrode 4. After the insulating film 5 is formed, the source 6 and the drain 7 are formed by ion implantation of impurities of opposite conductivity type to the substrate. Subsequently, after forming the first interlayer insulating film 8 on the entire surface of the substrate, the etching layer is selectively etched to form a contact hole exposing the drain 7, and then a bit line connected to the drain 7 through the contact hole. (9) is formed. After the process of forming the bit line 9 is completed, the substrate is formed by depositing borophospho-silicate glass (BPSG) as a second interlayer insulating film 10 on the entire surface of the substrate, or forming an insulating film having a double structure consisting of an oxide film and BPSG. Level the surface. In this case, the thickness of the second interlayer insulating film 10 is set to be at least 1000 μs or more on the gate electrode 4 on the bit line 9 or the field oxide film 2 of the lower layer. Subsequently, for example, PSG (phospho-silicate glass) is deposited on the interlayer insulating film 10, and an oxide film is formed on the first insulating film 11, for example, as a second insulating film 12. At this time, the wet etch rate of the PSG film is at least 10 times faster than the etching rate of the oxide film 12 and the BPSG film 10 above and below the PSG film in HF or buffered oxide etchant (BOE). It is formed by adjusting the concentration of phosphorus in the membrane. For example, it is preferable that the concentration of phosphorus in the PSG film is 7 wt% or more.

Next, as illustrated in FIG. 1B, a predetermined insulating pattern in which the first and second insulating layers are stacked by selectively etching the second insulating layer 12 and the first insulating layer 11 by a photolithography process. (13) is formed. Subsequently, for example, a polysilicon layer 14 is formed as the first conductive layer 14 on the entire substrate.

Subsequently, the polysilicon layer 14, the insulating film pattern 13, the second interlayer insulating film 10 and the first interlayer insulating film 8 are selectively removed by a photolithography process as shown in FIG. 1 (c). As a result, a contact hole 15 exposing the source 6 is formed.

Next, as shown in FIG. 1 (d), a side etch of the contact hole 15 is performed. This etching process is a subsequent process, through which the source region 6 of the substrate passes through the contact hole. ) Is performed together with the cleaning process performed before the capacitor lower electrode forming process connected to That is, in order to prevent the contact resistance between the polysilicon and the source region, which constitute the lower electrode, from being increased by the native oxide formed at the interface between the polysilicon and the source region, it is necessary to use HF or BOE. As shown in FIG. 1 (d), all parts except the contact hole 15 are covered with the polysilicon layer 14, which is the first conductive layer, so that the inside of the contact hole 15 is removed. Only the oxide films of are etched. At this time, since the etching rate of the first insulating film 11 made of the PSG film is 10 times faster than the etching rates of the second interlayer insulating film 10 and the oxide film 12 made of BPSG, as shown in FIG. Likewise, the side surface of the contact hole 15 in which the PSG layer 11 is relatively etched has a curved profile.

Next, as shown in FIG. 1 (e), a second polysilicon layer 16 is formed as a second conductive layer on the entire surface of the substrate. In this case, the polysilicon layer 16 is connected to the source 6 through the contact hole 15. Subsequently, the first polysilicon layer 14 and the second polysilicon layer 16 are selectively etched through a photolithography process so that capacitors are separated for each unit cell of the DRAM. In this manner, the capacitor lower electrode 17 including the first polysilicon layer 14 and the second polysilicon layer 16 is formed. Here, the second polysilicon layer 16 constituting the capacitor lower electrode has a side surface formed along the inner surface of the curved contact hole 15, thereby increasing the area of the capacitor lower electrode, thereby increasing the capacitor capacity. In addition, the lower electrode 17 is curved along the direction of the semiconductor substrate 1 on the second interlayer insulating film 10, and overlaps with the transistor and the bit line 9 to secure a charge storage area while preventing generation of steps. You can prevent it.

Next, as shown in FIG. 1 (f), the capacitor dielectric film 18 is formed on the entire surface of the substrate on which the capacitor lower electrode 17 is formed, for example, an ONO (Oxide / Nitride / Oxide) or NO (Nitride / Oxide) structure. A dielectric film is formed. Subsequently, as the third conductive layer, for example, polysilicon is deposited on the entire surface of the dielectric film 18 to form the capacitor upper electrode 19, the capacitor including the lower electrode 17, the dielectric film 18 and the upper electrode 19. To complete.

Subsequent processes proceed according to a conventional semiconductor memory device manufacturing process.

Meanwhile, the first, second and third conductive layers may be formed by depositing polysilicon doped with impurities or by implanting impurities after depositing polysilicon. At this time, it is preferable to use phosphorus or arsenic as an impurity doped or ion implanted.

Next, a capacitor manufacturing method of a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIGS. 2 (a) and 2 (b).

First, as shown in FIG. 2 (a), the same process as that of FIG. 1 (a) of the first embodiment is performed to form the first and second insulating films 11 and 12.

Subsequently, as illustrated in FIG. 2B, a predetermined insulating pattern in which the first and second insulating layers are stacked by selectively etching the second insulating layer 12 and the first insulating layer 11 by a photolithography process. It forms 13A. In this case, the insulating layer pattern 13A is formed in the region where the capacitor lower electrode is to be formed and the region where the capacitor lower electrode between the unit cell and the cell is separated.

It is preferable to form the insulating film pattern 13A formed in the separation region between the unit cell and the cell as narrow as possible to increase the capacitor capacity. Subsequently, for example, a polysilicon layer 14 is formed on the front surface of the substrate as the first conductive layer.

Since the subsequent steps are the same as those in the first (c) to the first (f) of the first embodiment, description thereof will be omitted.

According to the present invention made as described above, the end portion covers the insulating layer patterns 13 and 13A around the contact hole 15, and a central portion thereof surrounds the contact hole sidewalls and the bottom, so that the inside and the contact hole 15 are formed. Lower electrodes 17 each having a bend may be formed on the interlayer insulating film 10. That is, the lower electrode 17 may be curved in a direction parallel to the substrate, thereby preventing the step difference from deepening.

On the other hand, in the case of the second embodiment, as shown in FIG. 2 (f), not only the contact hole side but also the insulating film pattern formed on the field oxide film, the transistor, and the bit line, the insulating film pattern and adjacent insulating film pattern Since the bend is formed, a larger area of the capacitor lower electrode is secured than in the first embodiment. Therefore, a larger capacitor can be obtained.

In the first and second embodiments, an insulating film pattern having a two-layer structure including first and second insulating films is formed on the interlayer insulating film 10, but it is also possible to form two or more insulating films having different etching rates. . For example, after the PSG film 11 and the oxide film 12 are formed, the PSG film and the oxide film are formed again thereon. In this case, since the PSG film of two layers is etched a lot in the processes of FIGS. 1 (d) and 2 (d), more bends are formed on the side of the contact hole 15, and consequently, the capacitor formed thereon. The surface area of the lower electrode is further increased. Therefore, larger capacitor capacity can be ensured.

As described above, in the manufacturing of the capacitor of the semiconductor memory device, the surface of the contact hole is formed by increasing the surface area by bending the contact hole side by using an insulating film having a stack structure of insulating films having different etching rates. The capacitor capacity is increased by increasing the surface area of the capacitor lower electrode.

In addition, the stacked insulating layer pattern is formed in a region where the step height of the device is lower than that in other areas, so that the step may not be largely generated, thereby facilitating subsequent steps.

The present invention described above will be apparent to those skilled in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It is not limited by the examples and the accompanying drawings.

Claims (11)

A first step of planarizing a surface by forming an interlayer insulating film on the semiconductor substrate where the transistor and the bit line are formed; Stacking at least two layers of insulating layers having different etching rates with respect to a predetermined etching agent on the interlayer insulating layer; Selectively etching the stacked section films to form an insulating layer pattern having a stacked structure; A fourth step of forming a first conductive layer on the semiconductor substrate on which the third step is completed; Forming a contact hole exposing the semiconductor substrate by selectively etching the first conductive layer, the insulating layer pattern, and the interlayer insulating layer; A sixth step of forming a bend in the insulating layer pattern exposed on the side surface of the contact hole by treating the insulating layer pattern exposed on the side surface of the contact hole with the etchant; A seventh step of forming a second conductive layer on the contact hole bottom, side surfaces, and the first conductive layer; The second conductive layer and the first conductive layer may be selectively etched, and ends thereof may cover the insulating layer pattern and the interlayer insulating layer around the contact hole, and a center thereof may cover the sidewalls and the bottom of the contact hole, thereby forming an upper portion of the interlayer insulating layer. An eighth step of forming a lower electrode having a curvature in a direction parallel to the semiconductor substrate and having a curvature on the sidewall of the contact hole; And a ninth step of forming a dielectric film and an upper electrode on the lower electrode. The method of claim 1, wherein in the second step, an insulating film having the laminated structure is formed by sequentially depositing a PSG film and an oxide film on the interlayer insulating film. The method of claim 2, wherein HF or BOE is used as the etchant in the sixth step. The method of claim 3, wherein an etching rate of the PSG layer in the HF or the BOE is at least 10 times faster than that of the oxide layer and the interlayer insulating layer. 5. The method of claim 4, wherein the concentration of phosphorus in the PSG film is at least 7 wt%. The method of claim 1, wherein in the third step, at least one insulating layer pattern is formed. The method of claim 1, wherein the lower electrode overlaps the transistor and the bit line. The method of claim 1, wherein in the first step, the interlayer insulating film is formed by depositing BPSG or by forming an insulating film having a dual structure consisting of an oxide film and a BPSG. The method of claim 1, wherein in the sixth step, the native oxide film of the semiconductor substrate exposed to the bottom of the contact hole is simultaneously removed. The method of claim 1, wherein each of the first conductive layer and the second conductive layer is formed of a polysilicon layer. The method of manufacturing a semiconductor memory device according to claim 1, wherein in the ninth step, the dielectric film is formed of ONO or NO.