KR100226726B1 - Method for forming metal interconnection layer of semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device having a multi-layered metal wiring, wherein a dummy pattern is formed in the step weakness during metal wiring to improve the step and at the same time increase the depth of focus during exposure to prevent short circuit and distortion of the fine pattern. A method of forming a wiring of an element, the method comprising: forming a first insulating layer on a semiconductor substrate having a step by a plurality of partially formed elements; and forming a first metal line on the first insulating layer on the upper side of the device. Forming and planarizing a plurality of insulating layers on the entire surface of the semiconductor substrate including the first metal line, and forming a second metal layer on the insulating layer on the upper side of the first metal line, and then selectively removing the first metal layer. Forming a line and forming a dummy pattern at a portion where the step is most severely generated by the first metal line; And a step of planarizing the entire surface of the semiconductor substrate including the metal line.

Description

Wiring Formation Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming a wiring of a semiconductor device, which is suitable for minimizing a step between metal lines to prevent short circuit of a fine pattern and to improve depth of focus during exposure.

Hereinafter, a wiring forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device.

As shown in FIG. 1A, a BPSG (Borophosphorsilicate Glass) layer 15 is formed as an interlayer insulating film on the semiconductor substrate 11 where the step is generated by the plurality of elements 13 partially formed.

Since the gate and the various elements 13 are partially formed on the semiconductor substrate 11, a step is generated as a whole.

As shown in FIG. 1A, the metal is deposited on the BPSG layer 15 and then selectively removed to form the first metal lines 17.

After the first metal lines 17 are formed, a first tetra-ethyl-ortho-silicate (TEOS) layer 19 and a first spin on SOG are formed on the front surface of the semiconductor substrate 11 including the first metal lines 17. The glass layer 21 and the second TEOS layer 19a are sequentially formed to perform a planarization process.

The planarization process may etch back the first SOG layer 21 formed on the first TEOS layer 19 to improve the step generated by the first metal line 17, and then the second TEOS layer. It forms (19a).

Although not shown in the drawing, via holes are formed by selectively removing the second TEOS layer 19a and the first TEOS layer 19 on the first metal line 17.

Thereafter, the second metal 23 is deposited on the entire surface of the semiconductor substrate 11 including the via holes.

Subsequently, the photosensitive agent 25 is coated on the second metal 23.

Next, as shown in FIG. 1B, the photosensitive agent 25 is patterned through an exposure and development process, and the second metal 23 is selectively removed by an etching process using the patterned photosensitive agent 25 as a mask. The second metal lines 23a are formed on the line 17 and connected to the first metal lines 17 through the via holes.

Thereafter, only the remaining photosensitive agent 25 is removed.

Subsequently, the planarization process is performed again as shown in FIG. 1C. The planarization process is performed as follows.

That is, after forming the third TEOS layer 19b on the entire surface of the semiconductor substrate 11 including the second metal lines 23a, the second SOG layer 21a is formed on the third TEOS layer 19b.

The second SOG layer 21a is etched back to improve the level difference generated by the second metal lines 23a.

Therefore, the level difference generated between the second metal lines 23a may be improved by a small amount by the second SOG layer 21a.

Thereafter, a fourth TEOS layer 19c is formed on the entire surface of the semiconductor substrate 11 including the second SOG layer 21a and the third TEOS layer 19b.

Although not shown in the drawing, the fourth TEOS layer 19c and the third upper portion of the second metal line 23a for the electrical contact between the third metal line and the second metal line 23a to be formed in a later process. The TEOS layer 19b is selectively removed through a photolithography process to form via holes.

Subsequently, as shown in FIG. 1D, a third metal layer 27 is formed on the entire surface of the semiconductor substrate 11 including the via hole.

Then, the photosensitive agent 25a is applied to the entire surface including the third metal layer 27.

Thereafter, the exposure and development steps are carried out, but the exposure step is performed as follows.

First, in setting the focus in the exposure apparatus, the focus is set to be exposed at the middle part of the lowest part as opposed to the highest part.

If the focus is set, the exposure is performed. After the exposure is completed, the developing process is performed.

FIG. 2A illustrates a short circuit of a pattern generated when the focus is set at the highest step, and FIG. 2B illustrates a distortion state of the pattern when focus is set at the lowest step.

As shown in FIG. 2A, a step is generated by the second metal line 23a and the third metal layer 27, and the third metal layer 27 in the portion where the second metal line 23a is not present, and When comparing the third metal layer 27 on the second metal line (23a) has a step with each other.

In this case, if the focus is set when exposing to the highest step, the photoresist 25a of the highest step is precisely removed, but the photoresist 25a of the lowest part is not accurately removed and a part of the short circuit occurs. .

When the focus is set at the lowest point as shown in FIG. 2B, the phenomenon that the photoresist 25a of the portion to be removed is not removed as shown in FIG. 2A does not occur, but the patterned photoresist 25a has a distortion. .

However, such a conventional method of forming a wiring of a semiconductor device has the following problems.

First, when the focus is focused on a high step in order to form a fine pattern on a wafer having a step during exposure, the low step is short-circuited, and conversely, when the focus is focused on a low step, distortion occurs in the photoresist pattern at the high step.

Second, in order to solve the first problem, it is necessary to focus on the middle part of the high and low steps, which makes it difficult to proceed with the process because the width of the focus is reduced and the flexibility according to the change of the process is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming a wiring of a semiconductor device suitable for preventing a short circuit and pattern distortion of a pattern according to a fine pattern by improving a step using a dummy pattern. .

1A to 1D are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device.

2A is a view showing a short state of a micropattern during exposure according to the prior art;

Figure 2b is a view showing a distortion state of the fine pattern during exposure according to the prior art

3A to 3D are cross-sectional views illustrating a method of forming a semiconductor device wiring of the present invention.

* Description of the symbols for the main parts of the drawings *

11,31 semiconductor substrate 17,37 first metal line

23a, 43a: second metal line 27, 47: third metal layer

25, 25a, 49: photosensitive agent 43b: dummy pattern

A method of forming a wiring of a semiconductor device of the present invention for achieving the above object is a step of forming a first insulating layer on a semiconductor substrate having a step by a plurality of partially formed elements, and the first insulation on the upper side of the device Forming a first metal line on the layer; forming and planarizing a plurality of insulating layers on the entire surface of the semiconductor substrate including the first metal line; and forming a second metal layer on the insulating layer above the first metal line. And then selectively removing the first metal line to form a first metal line, and forming a dummy pattern on a portion where the step is most severely caused by the first metal line, and a front surface of the semiconductor substrate including the dummy pattern and the first metal line. It comprises a step of planarizing.

First, in the method of forming a semiconductor device wiring of the present invention, even if the planarization process is performed in the latter part of the wafer processing process, the photoresist pattern may be changed due to an incorrect setting of the depth of focus due to the step between the metal lines according to the design characteristics of the device, or the lack of an acceptable range. In order to improve short circuit or distortion, a dummy pattern is formed in a portion having a high step before the planarization process to secure a margin of focus depth and prevent a short circuit or distortion of a fine pattern.

Hereinafter, a method of forming a wiring of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

3A to 3D are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the present invention.

First, as shown in FIG. 3A, a first insulating layer 35 is formed on a semiconductor substrate 31 having a step difference caused by a plurality of elements 33 partially formed.

In this case, the material of the first insulating layer 35 is BPSG (Borophosphorsilicate Glass).

Although not shown in the drawing, the gate and various elements are partially formed on the semiconductor substrate 31, thereby causing a step in total.

As shown in FIG. 3A, the metal is deposited on the first insulating layer 35 and then selectively removed to form the first metal lines 37.

After forming the first metal lines 37, the second insulating layer 39 and the third insulating layer 41 are sequentially formed on the entire surface of the semiconductor substrate 31 including the first metal lines 37.

The third insulating layer 41 is etched back to remove only the third insulating layer 41 on the second insulating layer 39 on the upper side of the first metal line 37, leaving only the severe step.

In this case, the material of the second insulating layer 39 is tetra-ethyl-ortho-silicate (TEOS) and the material of the third insulating layer 41 is spin on glass (SOG).

Subsequently, a fourth insulating layer 39a is formed on the entire surface of the semiconductor substrate 31 including the second and third insulating layers 39 and 41 to perform a planarization process.

At this time, the material of the fourth insulating layer 39a is TEOS.

Although not shown in the drawing, the second insulating layer 39 and the fourth insulating layer 39a on the first metal line 37 are selectively removed to form via holes, and then the entire surface of the semiconductor substrate 31 including the via holes is formed. The second metal 43 is deposited.

Subsequently, the photosensitive agent 45 is coated on the second metal 43.

The photosensitive agent 45 used at this time is a photoresist.

In forming an exposure mask for exposing the photosensitive agent 45, a step is generated by the first metal line 37 and the second metal line to be formed in a later process, and a dummy pattern is formed at a portion where the step is most severely generated. The mask for forming is formed simultaneously.

The photosensitive agent 45 is exposed by using an exposure mask having a mask for forming the dummy pattern to pattern the photosensitive agent 45.

Subsequently, the second metal 23 is selectively removed by an etching process using the patterned photosensitive agent 45 as a mask to form a second metal line 43a and a dummy pattern 43b as shown in FIG. 3B. .

After removing the photoresist 45, the planarization process is performed as shown in FIG. 3C.

Here, the planarization process is performed as follows.

First, the fifth insulating layer 39b is formed on the entire surface of the semiconductor substrate 11 including the second metal line 43a and the dummy pattern 43b, and the sixth insulating layer 41a is formed on the fifth insulating layer 39b. In order to deposit.

In this case, the material of the fifth insulating layer 39b is TEOS and the material of the sixth insulating layer 41a is SOG.

After the etch back process is performed on the sixth insulating layer 41a thus formed, the seventh insulating layer 39c is formed on the entire surface.

At this time, the material of the seventh insulating layer 39c is TEOS.

Although not shown in the drawings, the via hole is formed by removing a predetermined portion of the seventh insulating layer 39c and the fifth insulating layer 39b on the second metal line 43a.

At this time, the sixth insulating layer 41a does not exist above the second metal line 43a because it is removed through an etch back process.

The via hole is for electrical connection between the second metal line 43a and the third metal line to be formed in a later process.

Next, as shown in FIG. 3D, a third metal layer 47 is formed on the entire surface of the semiconductor substrate 11 including the via hole.

Then, the photosensitive agent 49 is coated on the third metal layer 47.

At this time, the degree of step difference is remarkably improved by the dummy pattern 43b.

The improvement in the degree of step generation means that not only the depth of focus increases when the photosensitive agent 49 is exposed, but also that the photosensitive agent 49 on which the patterning process is completed is distorted or shorted significantly.

As described above, the semiconductor device wiring formation method of the present invention has the following effects.

First, in forming the metal line, the short circuit of the micro pattern is prevented by minimizing the step on the semiconductor substrate.

Second, since the step is minimized, the depth of focus is increased during the exposure process to prevent distortion of the fine pattern.

Claims (3)

Forming a first insulating layer on the semiconductor substrate having a step by a plurality of partially formed elements, Forming a first metal line on the first insulating layer above the device; Forming and planarizing a plurality of insulating layers over the entire surface of the semiconductor substrate including the first metal lines; Forming a first metal line by selectively removing the second metal layer on the insulating layer on the upper side of the first metal line, and then forming a dummy pattern on a portion where the step is most severely caused by the first metal line. Fair, And planarizing the entire surface of the semiconductor substrate including the dummy pattern and the first metal line. The method of claim 1, The flattening process Forming a TEOS layer on the entire surface including the lower metal line; Forming a SOG layer on the TEOS layer, And forming a TEOS layer on the entire surface after etching back the SOG layer. The method of claim 1, The dummy pattern forming process Forming a insulating layer after forming the first metal line and performing planarization; Forming a second metal layer on the insulating layer and then applying a photosensitive agent on the second metal layer; Patterning a photosensitive agent using the exposure mask for forming the second metal line and the dummy pattern; And forming a second metal line and a dummy pattern by selectively removing the second metal layer by an etching process using a patterned exposure mask.

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