KR0179833B1 - Semiconductor package manufacturing method - Google Patents
Semiconductor package manufacturing method Download PDFInfo
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- KR0179833B1 KR0179833B1 KR1019950022837A KR19950022837A KR0179833B1 KR 0179833 B1 KR0179833 B1 KR 0179833B1 KR 1019950022837 A KR1019950022837 A KR 1019950022837A KR 19950022837 A KR19950022837 A KR 19950022837A KR 0179833 B1 KR0179833 B1 KR 0179833B1
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- Prior art keywords
- semiconductor chip
- lead
- leads
- package
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000000465 moulding Methods 0.000 claims abstract description 21
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 18
- 238000005452 bending Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로, 종래에는 패키지의 몸체 외부로 아웃리드가 돌출되어 있는 구조로써, 패키지의 소형화에 한계가 있고, 아웃리드가 외부의 충격에 휨이 발생할 우려가 있으며, 리드의 파인 피치화에 한계가 있는 문제점이 있었다.The present invention relates to a semiconductor package and a method for manufacturing the same. In the related art, an outlead is protruded to the outside of the package body, and there is a limit in miniaturization of the package, and the outlead may be warped by an external impact. There was a problem that the fine pitch of the lead had a limit.
본 발명은 리드(11), 절연테이프(12), 보조프레임(13)으로 구성된 리드 프레임에 반도체 칩(10)을 탑재하고, 그 반도체 칩(10)의 양측 상,하부에 리드(11)를 밴딩하여 밀착고정시켜서 외부단자가 되도록 한 후, 몰딩 컴파운드로 몰딩한 것으로써, 패키지의 소형화를 이룰 수 있고, 외부의 충격으로부터 아웃리드를 보호할 수 있으며, 리드의 파인 피치화가 가능한 것이다.According to the present invention, a semiconductor chip 10 is mounted on a lead frame composed of a lead 11, an insulating tape 12, and an auxiliary frame 13, and the leads 11 are placed on both sides of the semiconductor chip 10. By banding to fix and fix the external terminal and molding with molding compound, the package can be miniaturized, the outlead can be protected from external impact, and the fine pitch of the lead can be achieved.
Description
제1도는 일반적인 반도체 패키지의 구성을 보인 종단면도.1 is a longitudinal sectional view showing a configuration of a general semiconductor package.
제2도는 본 발명 반도체 패키지의 구성을 보인 종단면도.2 is a longitudinal sectional view showing a configuration of a semiconductor package of the present invention.
제3도는 본 발명 반도체 패키지의 리드프레임을 보인 것으로, (a)는 평면도, (b)는 저면도, (c)는 A-A'단면도.3 shows a lead frame of a semiconductor package of the present invention, (a) is a plan view, (b) is a bottom view, and (c) is an AA 'cross-sectional view.
제4도는 본 발명의 리드프레임에 칩이 마운팅된 상태를 보인 종단면도.Figure 4 is a longitudinal cross-sectional view showing a state in which the chip is mounted on the lead frame of the present invention.
제5도는 본 발명의 리드프레임을 칩에 밴딩하여 밀착고정한 상태를 보인 종단면도.5 is a longitudinal sectional view showing a state where the lead frame of the present invention is tightly bonded to the chip.
제6도는 본 발며의 외이어본딩한 상태를 보인 종단면도.Figure 6 is a longitudinal cross-sectional view showing the state of the outer bond of the present foot.
제7도는 본 발명의 반도체 패키지를 몰딩공정으로 완성한 상태를 보인 것으로, (a)는 종단면도, (b)는 측면도, (c)는 저면도.7 shows a state in which the semiconductor package of the present invention is completed by a molding process, wherein (a) is a longitudinal cross-sectional view, (b) is a side view, and (c) is a bottom view.
제8도는 본 발명의 다른 실시예를 보인 것으로, (a)는 리드프레임을 보인 평면도, (b)는 완성된 반도체 패키지의 저면도.Figure 8 shows another embodiment of the present invention, (a) is a plan view showing a lead frame, (b) is a bottom view of the completed semiconductor package.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체 칩 10a : 칩패드10: semiconductor chip 10a: chip pad
11 : 리드 11a : 인너리드11: lead 11a: inner lead
12 : 절연테이프 13 : 보조프레임12: insulating tape 13: auxiliary frame
14 : 금속와이어 15 : 몸체부14 metal wire 15 body
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로, 패키지의 소형화가 가능하고, 리드의 파인 피치(FINE PITCH)화를 실현할 수 있는 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package capable of miniaturizing a package and realizing fine pitch of a lead.
제1도는 일반적인 반도체 패키지의 구성을 보인 종단면도로써, 도시한 바와 같이, 본 발명의 반도체 패키지는 리드프레임(1)의 패들(2)위에 반도체 칩(3)이 부착되어 있고, 그 반도체 칩(3)과 리드프레임(1)의 인너리드(4)는 금속와이어(5)로 전기적인 접속을 이루고 있으며, 상기 반도체 칩(13), 인너리드(4), 금속와이어(5)를 포함하는 일정면적을 몰딩 컴파운드(MOLDING COMPOUND)로 몰딩한 몸체(6)로 구성되어 있다.FIG. 1 is a longitudinal cross-sectional view showing a configuration of a general semiconductor package. As shown in the drawing, a semiconductor chip 3 is attached to a paddle 2 of a lead frame 1, and the semiconductor chip ( 3) and the inner lead 4 of the lead frame 1 are electrically connected to the metal wire 5, and the constant lead including the semiconductor chip 13, the inner lead 4, and the metal wire 5 is formed. It consists of a body 6 molded in an area with a molding compound.
상기 도면중 미설명부호 7은 상기 인너리드(4)에 연결되어 몸체(6)의 외부로 설치되어 있는 아웃리드를 보인 것이다.In the drawing, reference numeral 7 shows an out lead which is connected to the inner lead 4 and installed to the outside of the body 6.
상기와 같이 구성되어 있는 일반적인 반도체 패키지의 제조방법을 살펴보면 다음과 같다.Looking at the manufacturing method of a general semiconductor package configured as described above are as follows.
일반적인 반도체 패키지는 패들(2)의 상부에 접착제(도시되어 있지 않음)를 이용하여 반도체 칩(3)을 부착하는 다이본딩 공정을 수행하는 단계와, 상기 반도체 칩(3)과 인너리드(4)를 금속와이어(5)로 연결하여 전기적인 접속이 되도록 하는 외이어 본딩 공정을 수행하는 단계와, 상기 반도체 칩(3), 금속와이어(5), 인너리드(4)를 포함하는 일정면적을 몰딩 컴파운드로 몰딩하는 몰딩공정을 수행하는 단계와, 트리밍/포밍 공정을 수행하는 단게의 순서로 제조되는 것이다.In a general semiconductor package, a die bonding process of attaching the semiconductor chip 3 using an adhesive (not shown) on the paddle 2 is performed, and the semiconductor chip 3 and the inner lead 4 are formed. Performing a wire bonding process for connecting to the metal wires 5 to make an electrical connection, and molding a predetermined area including the semiconductor chip 3, the metal wires 5, and the inner lead 4. It is manufactured in the order of performing a molding process of molding into a compound, and a step of performing a trimming / forming process.
그러나, 상기와 같은 반도체 패키지는 외부단자의 역할을 하게 되는 아웃리드(7)를 몸체(6)의 양측 외부로 돌출시켜야 하므로 패키지를 소형화 시키는데 한계가 있고, 외부의 충격에 의하여 아웃리드(7)의 휨이 발생할 우려가 있으며, 리드의 파인 피치화가 어려운 문제점이 있었다.However, the semiconductor package as described above has a limitation in miniaturizing the package because the outlead 7, which serves as an external terminal, needs to protrude outward from both sides of the body 6, and the outlead 7 may be affected by an external impact. There is a possibility that warpage may occur, and the fine pitch of the lead is difficult.
이를 감안하여 안출한 본 발명의 목적은 반도체 칩의 신호를 패키지의 외부로 전달하는 리드를 반도체 칩의 양측 상,하에 밀착되도록 밴딩하여 설치함으로써, 패키지를 소형화 시키고, 외부의 충격으로 부터 리드를 보호하며, 리드의 파인 피치화가 가능한 반도체 패키지를 제공함에 있다.The object of the present invention devised in view of this is to install the bands that transmit the signal of the semiconductor chip to the outside of the package to be in close contact with the upper and lower sides of the semiconductor chip, thereby miniaturizing the package and protect the lead from external impact The present invention provides a semiconductor package capable of fine pitch of a lead.
상기와 같은 본 발명의 목적을 달성하기 위하여 반도체 칩과, 상기 반도체 침의 양측 상,하를 감싸도록 밴딩 설치되어 외부로의 전기적인 열결단자가 되는 리드들과, 그 리드들이 나열 부착되는 절연테이프와, 그 절연테이프를 지지하는 보조프레임과, 상기 반도체 칩의 칩 패드들과 상기 리드들의 인너리드를 전기적으로 접속시키는 금속와이어와, 상기 반도체 칩, 금속와이어, 인너리드를 포함하는 일정면적을 몰딩 컴파운드로 몰딩하는 몸체부로 구성되어 있는 것을 특징으로 하는 반도체 패키지가 제공된다.In order to achieve the object of the present invention as described above, the semiconductor chip, the bands are installed so as to surround the upper and lower sides of the semiconductor needle, the leads to be an electrical thermal connector to the outside, and the insulating tape to which the leads are attached And a predetermined area including an auxiliary frame supporting the insulating tape, a metal wire electrically connecting the chip pads of the semiconductor chip and the inner lead of the leads, and the semiconductor chip, the metal wire, and the inner lead. There is provided a semiconductor package comprising a body portion molded into a compound.
또한, 리드들이 나열부착된 절연테이프가 하측에 부착되어 있는 보조프레임의 상면에 반도체 칩을 부착하는 다이본딩 공정을 수행하는 단계와, 상기 반도체 침의 양측에 감싸도록 리드들이 부착된 절연테이프를 밴딩하여 부착하는 밴딩공정을 수행하는 단계와, 상기 반도체 칩의 상면에 설치되어 있는 칩패드와 상기 리드의 인너리드를 금속와이어로 연결하여 전기적인 접속이 되도록 하는 와이어본딩 공정을 수행하는 단계와, 상기 반도체칩, 인너리드, 금속와이어를 포함하는 일정면적을 몰딩 컴파운드로 몰딩하는 몰딩공정을 수행하는 단계의 순서로 제조되는 것을 특징으로하는 반도체 패키지 제조방법이 제공된다.In addition, performing a die-bonding process of attaching a semiconductor chip to the upper surface of the auxiliary frame is attached to the lower side of the insulating tape is attached to the lower side, and bending the insulating tape attached to the lead to wrap on both sides of the semiconductor needle Performing a banding process to attach the metal pads; and a wire bonding process of connecting the chip pads installed on the upper surface of the semiconductor chip and the inner leads of the leads with metal wires to make an electrical connection. Provided is a method of manufacturing a semiconductor package, the method comprising the steps of performing a molding process of molding a predetermined area including a semiconductor chip, an inner lead, and a metal wire into a molding compound.
이하, 상기와 같이 구성되어 있는 본 발명의 반도체 패키지를 첨부된 도면에 의거하여 보다 상세히 설명한다.Hereinafter, the semiconductor package of the present invention configured as described above will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명 반도체 패키지의 구성을 보인 종단면도로써, 도시한 바와 같이, 본 발명의 반도체 패키지는 반도체 칩(10)과, 상기 반도체 칩(10)의 양측 상,하를 감싸도록 밴딩 설치하여 외부로의 전기적인 연결단자가 되는 수개의 리드(11)와, 그 리드(11)가 나열 부착되는 절연테이프(12)와, 그 절연테이프(12)를 지지하는 보조프레임(13)과, 상기 반도체 칩(10)의 칩패드(10a)와 상기 리드(11)의 인너리드(11a)를 전기적으로 접속시키는 금속와이어(14)와, 상기 반도체 칩(10), 금속와이어(14), 인너리드(11a)를 포함하는 일정면적을 몰딩 컴파운드로 몰딩하는 몸체부(15)로 구성되어 있는 것이다.2 is a longitudinal cross-sectional view showing the configuration of the semiconductor package of the present invention. As shown in the drawing, the semiconductor package of the present invention is banded so as to surround the semiconductor chip 10 and upper and lower sides of the semiconductor chip 10. Several leads 11 serving as electrical connection terminals to the outside, an insulating tape 12 on which the leads 11 are attached, an auxiliary frame 13 supporting the insulating tape 12, and A metal wire 14 electrically connecting the chip pad 10a of the semiconductor chip 10 and the inner lead 11a of the lead 11, the semiconductor chip 10, the metal wire 14, and the inner lead. It is composed of a body portion 15 for molding a predetermined area including the (11a) with a molding compound.
도면중 미설명부호 11b는 외부로의 연결단자가 되는 아웃리드이다.In the figure, reference numeral 11b denotes an outlead that becomes a connection terminal to the outside.
이와 같은 반도체 패키지는 리드(11)가 패키지의 상면, 측면, 하면에 외부로 노출되어 있어, 하나의 패키지로 포워드(FORWARD) 타입 또는 리버스(REVERSE) 타입 패키지로 솔더링(SOLDERING)하여 피시비 기판에 실장할 수 있으며, 또한 패키지를 적층하여 사용할 수도 있는 구조인 것이다.In this semiconductor package, the lead 11 is exposed to the top, side, and bottom of the package to the outside, and soldered in a FORWARD or REVERSE type package in one package to be mounted on the PCB. It is also a structure that can be used by stacking the package.
상기와 같이 구성되어 있는 본 발명 반도체 패키지의 제조방법을 제3도 내지 제7도를 참조하여 설명하면 다음과 같다.A method of manufacturing the semiconductor package according to the present invention having the above structure will be described with reference to FIGS. 3 to 7 as follows.
본 발명 반도체 패키지는 리드(11)들이 부착된 절연테이프(12)가 보조프레임(13)의 하측에 부착되어 있고, 이와 같이 절연테이프(12)가 부착되도록 연속적으로 연결되어 있는 보조프레임(13)이 다이본딩장비에서 이송하는 상태에서 보조프레임(13)의 상면에 반도체 칩(10)을 연속적으로 부착하는 다이본딩공정을 수행하는 단계와, 상기 반도체 칩(10)의 양측에 감싸도록 절연테이프(12)와 리드(11)를 밴딩하여 부착하는 밴딩공정을 수행하는 단게와, 상기 반도체 칩(10)의 상면에 설치되어 있는 칩패드(10a)와 상기 리드(11)의 인너리드(11a)를 금속와이어(14)로 연결하여 전기적인 접속이 되도록 하는 와이어본딩 공정을 수행하는 단계와, 상기 반도체칩(10), 인너리드(11a), 금속와이어(14)를 포함하는 일정면적을 몰딩 컴파운드로 몰딩하는 몰딩공정을 수행하는 단계의 순서로 제조되며, 이와 같이 몰딩공정을 마친 다음에는 후공정으로 보조프레임(13)의 연결부분을 절단하여 패키지를 완성하게 된다.In the semiconductor package according to the present invention, the insulating tape 12 to which the leads 11 are attached is attached to the lower side of the auxiliary frame 13, and the auxiliary frame 13 is continuously connected to attach the insulating tape 12 to each other. Performing a die bonding process of continuously attaching the semiconductor chip 10 to the upper surface of the auxiliary frame 13 in the state of transferring from the die bonding equipment, and insulating tape (to be wrapped on both sides of the semiconductor chip 10); 12 and a bending step for bending and attaching the lead 11 to each other, the chip pad 10a provided on the upper surface of the semiconductor chip 10 and the inner lead 11a of the lead 11. Performing a wire bonding process of connecting the metal wires 14 to make an electrical connection, and forming a predetermined area including the semiconductor chip 10, the inner lead 11a, and the metal wires 14 into a molding compound. Performing the molding process of molding It is manufactured in order, and after the molding process is completed, the connection part of the auxiliary frame 13 is cut in a later process to complete the package.
제8도는 본 발명의 다른 실시예를 보인 것으로, 제8도의 (a)와 같이 보조프레임(13)을 사각형으로 하고, 그 보조프레임(13)의 하면에 리드(도시되어 있지 않음)가 부착된 절연테이프(12)를 부착하였으며, 이와 같은 리드프레임을 이용하여 제8도의 (b)에 도시된 바와 같이 패키지 몸체(15)의 4면에 리드(11)가 형성되는 다핀 구조의 패키지 제조가 가능한 것이다.FIG. 8 illustrates another embodiment of the present invention, in which the auxiliary frame 13 has a quadrangular shape as shown in FIG. 8 (a), and a lead (not shown) is attached to the lower surface of the auxiliary frame 13. Insulating tape 12 is attached, and using this lead frame, it is possible to manufacture a package having a multi-pin structure in which leads 11 are formed on four sides of the package body 15 as shown in FIG. will be.
이상에서 상세히 설명한 바와 같이 본 발명의 반도체 패키지는 반도체 칩의 양측 상,하부를 감싸도록 리드를 밴딩하여 설치하고, 그 패키지의 상,하부 혹은 측면에 밀착된 리드가 외부와의 접속단자가 되도록 함으로써, 패키지의 소형화가 가능하고, 외부의 충역에 아웃리드가 휘는 것을 방지할 수 있으며, 리드의 파인 피치화가 가능한 효과가 있는 것이다.As described in detail above, the semiconductor package of the present invention is installed by bending leads so as to surround upper and lower sides of the semiconductor chip, and the leads closely contacted to the upper, lower or side surfaces of the package are connected to the outside. In addition, the package can be miniaturized, the outlead can be prevented from bent outside, and the fine pitch of the lead can be reduced.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950022837A KR0179833B1 (en) | 1995-07-28 | 1995-07-28 | Semiconductor package manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950022837A KR0179833B1 (en) | 1995-07-28 | 1995-07-28 | Semiconductor package manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| KR970008508A KR970008508A (en) | 1997-02-24 |
| KR0179833B1 true KR0179833B1 (en) | 1999-03-20 |
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| KR1019950022837A KR0179833B1 (en) | 1995-07-28 | 1995-07-28 | Semiconductor package manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100814433B1 (en) * | 2006-11-22 | 2008-03-18 | 삼성전자주식회사 | Lead frame unit, semiconductor package having the lead frame unit, method of manufacturing the semiconductor package, stacked semiconductor package having the semiconductor packages and method of manufacturing the stacked semiconductor package |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100819799B1 (en) * | 2005-02-22 | 2008-04-07 | 삼성테크윈 주식회사 | Method for manufacturing the semiconductor package of multi-row lead type |
-
1995
- 1995-07-28 KR KR1019950022837A patent/KR0179833B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100814433B1 (en) * | 2006-11-22 | 2008-03-18 | 삼성전자주식회사 | Lead frame unit, semiconductor package having the lead frame unit, method of manufacturing the semiconductor package, stacked semiconductor package having the semiconductor packages and method of manufacturing the stacked semiconductor package |
Also Published As
| Publication number | Publication date |
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| KR970008508A (en) | 1997-02-24 |
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