KR0179000B1 - Planary method of ic - Google Patents

Planary method of ic Download PDF

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Publication number
KR0179000B1
KR0179000B1 KR1019910000644A KR910000644A KR0179000B1 KR 0179000 B1 KR0179000 B1 KR 0179000B1 KR 1019910000644 A KR1019910000644 A KR 1019910000644A KR 910000644 A KR910000644 A KR 910000644A KR 0179000 B1 KR0179000 B1 KR 0179000B1
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South Korea
Prior art keywords
photoresist film
semiconductor device
film
applying
planarization
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KR1019910000644A
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Korean (ko)
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KR920015582A (en
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박준영
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문정환
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

포토레지스트막을 이용하여 토폴로지가 심한층에 적합한 반도체 장치의 평탄화방법에 관한 것으로, 반도체 장치의 제조공정에 있어서, 웨이퍼상에 유전체막, 제1포토레지스트막을 차례로 도포하는 공정과, 단차가 넓게 형성된 부분 이외의 제1포토레지스트막을 제거하는 공정과, 남아 있는 제1포토레지스트막에 자외선 큐어링을 실시하는 공정과, 전면에 제2포토레지스트막을 도포하는 공정과, 에치백하여 평탄화하는 공정으로 이루어진다.The present invention relates to a planarization method of a semiconductor device suitable for a layer having a high topology by using a photoresist film. The semiconductor device manufacturing process includes a step of sequentially applying a dielectric film and a first photoresist film on a wafer, and a step having a wide step. A process of removing the other first photoresist film, a step of applying ultraviolet curing to the remaining first photoresist film, a process of applying a second photoresist film on the entire surface, and a step of etching back and flattening the film.

반도체 장치의 평탄화를 거의 완벽하면서도 용이하게 얻을 수 있으며, 또한 단순한 공정의 조합이므로 공정상 어려움이 없고 코스트의 감소에 기여할 수 있는 이점이 있다.The planarization of the semiconductor device can be obtained almost completely and easily, and since it is a combination of simple processes, there is no process difficulty and contributing to the reduction of cost.

Description

반도체 장치의 평탄화방법Planarization method of semiconductor device

제1도(a)-(d)는 종래의 평탄화공정도.1 (a)-(d) are conventional planarization process diagrams.

제2도(a)-(g)는 본 발명에 따른 평탄화공정도이다.2 (a)-(g) are planarization process diagrams according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 웨이퍼 12 : 유전체막11 wafer 12 dielectric film

13,14 : 포토레지스트13,14: photoresist

본 발명은 반도체 장치의 제조공정에 관한 것으로, 특히 포토레지스트막을 이용하여 토폴로지가 심한층에 적합한 반도체 장치의 평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a planarization method of a semiconductor device suitable for a layer having a high topology using a photoresist film.

일반적으로, 더블메탈을 사용하는 반도체 장치의 제조시에는 1차메탈을 도포하고 IMD(Inter-Metal-Dielectric)를 증착한 수 콘택을 형성하고 2차메탈을 도포하는 공정을 진행하게 되는데 1차메탈에 의한 토폴로지 때문에 이후 공정 진행에 어려움을 주게 된다.In general, in the manufacture of semiconductor devices using double metal, a process of applying primary metal, forming a water contact in which IMD (Inter-Metal-Dielectric) is deposited, and applying secondary metal is performed. Due to the topology, the process is difficult to proceed later.

이것을 완화시키기 위하여 평탕화공정을 실시하는데 종래에는 유전체막상에 포토레지스트막을 코팅한 후 에칭하는 에치백(Etch-Back) 공정을 사용하였다.In order to alleviate this, a planarization process is performed. In the related art, an etch-back process in which a photoresist film is coated on a dielectric film and then etched is used.

제1도(a)-(d)를 참조하여 설명하면, 우선 토폴로지가 있는 웨이퍼(11)상에 유전체막(2)을 도포한 후(제1도(a)(b)), 그 위에 포토레지스트막(3)을 코팅하고, 유전체막(2)과 포토레지스트막(3)이 비슷한 에치비를 갖는 조건으로 에치백하여 평탄화한다(제1도(c)(d)).Referring to Figs. 1 (a)-(d), first, a dielectric film 2 is applied onto a wafer 11 having a topology (Fig. 1 (a) (b)), and then a photo is placed thereon. The resist film 3 is coated, and the dielectric film 2 and the photoresist film 3 are etched back and planarized under conditions having a similar etch ratio (FIG. 1 (c) (d)).

그 후 완전한 평탄화를 위해서는 상술한 공정을 반복하여 실시하게 된다.Thereafter, the above-described process is repeated for complete planarization.

그러나, 이러한 종래기술은 평탄화의 정도가 우수한 패턴을 얻기 위해서는 에치백 공정을 여러번 반복수행하여야 하는 문제점이 있었다.However, such a prior art has a problem in that the etchback process is repeatedly performed several times in order to obtain a pattern having an excellent flattening degree.

본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 기존의 에치백공정을 사용하면서도 우수한 평탄화를 용이하게 얻을 수 있도록 한 반도체 장치의 평탄화방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a planarization method of a semiconductor device which can easily obtain excellent planarization while using an existing etch back process.

이와 같은 목적을 달성하기 위한 본 발명의 특징은 반도체장치의 제조공정에 있어서, 웨이퍼상에 유전체막, 제1포토레지스트막을 차례로 도포하는 공정과, 단차가 넓게 형성된 부분이외의 제1포토레지스트막을 제거하는 공정과, 남아 있는 제1포토레지스트막에 자외선 큐어링을 실시하는 공정과, 전면에 제2포토레지스트막을 도포하는 공정과, 에치백하여 평탄화하는 공정으로 이루어진 반도체 장치의 평탄화방법에 있다.A feature of the present invention for achieving the above object is a step of sequentially applying a dielectric film, a first photoresist film on the wafer in the manufacturing process of the semiconductor device, and removing the first photoresist film other than the portion having a wide step And a step of applying ultraviolet curing to the remaining first photoresist film, a step of applying a second photoresist film to the entire surface, and a step of etching back and planarizing the semiconductor device.

이하, 본 발명을 첨부도면에 의하여 상세히 설명한다.Hereinafter, the present invention will be described in detail by the accompanying drawings.

제2도(a)-(g)는 본 발명에 따른 평탄화공정도로서, 우선 제2도(a)(b)(c)에 도시한 바와 같이 토폴로지가 있는 웨이퍼(11)상에 유전체막(12)을 도포하고 그 위에 포토레지스트막(13)을 코팅한다.2 (a)-(g) are planarization process diagrams according to the present invention. First, as shown in FIG. 2 (a) (b) (c), the dielectric film 12 is formed on a wafer 11 having a topology. ) Is coated and the photoresist film 13 is coated thereon.

그 후, 제2도(d)와 같이 단차가 넓게 형성된 부분 이외의 포토레지스트막(13)을 제거한 다음, 제2도(e)와 같이 다음에 코팅될 다른 포토레지스트막(14)과의 상호작용을 방지하기 위하여 포토레지스트막(13)에 자외선 큐어링(Ultraviolet Curing)을 실시한다.Thereafter, the photoresist film 13 other than the portion where the step is widened as shown in FIG. 2 (d) is removed, and then mutually with another photoresist film 14 to be coated next, as shown in FIG. Ultraviolet Curing is applied to the photoresist film 13 to prevent the action.

제2도(f)에 도시한 바와 같이, 전면에 다른 포토레지스트막(14)을 코팅한 후, 에치백하여 평탄화하면 제2도(g)와 같은 거의 완벽한 평탄화를 얻을 수 있게 된다.As shown in FIG. 2 (f), after the other photoresist film 14 is coated on the entire surface, it is etched back and planarized to obtain almost perfect planarization as shown in FIG. 2 (g).

이상 설명한 바와 같이, 본 발명에 따르면 반도체 장치의 평탄화를 거의 완벽하면서도 용이하게 얻을 수 있으며, 또한 단순한 공정의 조합이므로 공정상 어려움이 없고 코스트의 감소에 기여할 수 있는 이점이 있다.As described above, according to the present invention, the planarization of the semiconductor device can be obtained almost completely and easily, and since it is a combination of simple processes, there is no process difficulty and contributing to the reduction of cost.

Claims (1)

반도체 장치의 제조공정에 있어서, 웨이퍼상에 유전체막, 제1포토레지스트막을 차례로 도포하는 공정과, 단차가 넓게 형성된 부분 이외의 상기 제1포토레지스트막을 제거하는 공정과, 남아 있는 상기 제1포토레지스트막에 자외선 큐어링을 실시하는 공정과, 전면에 제2포토레지스트막을 도포하는 공정과, 에치백하여 평탄화하는 공정으로 이루어진 반도체 장치의 평탄화방법.In the manufacturing process of a semiconductor device, a step of sequentially applying a dielectric film, a first photoresist film on the wafer, a step of removing the first photoresist film other than the portion having a wide step, and the remaining first photoresist A flattening method of a semiconductor device comprising a step of applying ultraviolet curing to a film, a step of applying a second photoresist film to the entire surface, and a step of etching back and flattening.
KR1019910000644A 1991-01-16 1991-01-16 Planary method of ic KR0179000B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100922074B1 (en) * 2002-12-02 2009-10-16 매그나칩 반도체 유한회사 Method for forming an isolation film in semiconductor device
CN106941075A (en) * 2017-03-08 2017-07-11 扬州国宇电子有限公司 The trench schottky surface planarisation processing technology of semiconductor chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100922074B1 (en) * 2002-12-02 2009-10-16 매그나칩 반도체 유한회사 Method for forming an isolation film in semiconductor device
CN106941075A (en) * 2017-03-08 2017-07-11 扬州国宇电子有限公司 The trench schottky surface planarisation processing technology of semiconductor chip

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Publication number Publication date
KR920015582A (en) 1992-08-27

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