JPS5690355A - Data processing unit - Google Patents

Data processing unit

Info

Publication number
JPS5690355A
JPS5690355A JP16691179A JP16691179A JPS5690355A JP S5690355 A JPS5690355 A JP S5690355A JP 16691179 A JP16691179 A JP 16691179A JP 16691179 A JP16691179 A JP 16691179A JP S5690355 A JPS5690355 A JP S5690355A
Authority
JP
Japan
Prior art keywords
register
address
data
logical
loaded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16691179A
Other languages
Japanese (ja)
Inventor
Hideharu Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16691179A priority Critical patent/JPS5690355A/en
Publication of JPS5690355A publication Critical patent/JPS5690355A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To secure in a main memory device a buffer area which is sufficient in physical viewing, too, by rewriting a register of address conversion table designation to each input/output instruction.
CONSTITUTION: When the channel device 3 accesses the main memory device 1, the address signal 310a of the logical address register 310, and the designating information 315a of the register of address conversion table designation 315 are sent out to the device 1. The contents of the register 315 in this case are read out by the address from the local memory part 321 whenever a data is transferred, are stored in the data buffer register 320 through the two-way bus 321a, and after that, they are provided after passing through the logical operation circuit 322. Also, the logical address of the device 1 from the memory part 321 is loaded to the register 310, and both the address information of the register 310 and the designating information of the register 315 are sent out to the device 1. And, a data is loaded to the register 320 through the bus 2a from the device 1. After that, the number of channel command words to be transferred and the logical address of the device 1 are made +1 and -1, respectively.
COPYRIGHT: (C)1981,JPO&Japio
JP16691179A 1979-12-24 1979-12-24 Data processing unit Pending JPS5690355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16691179A JPS5690355A (en) 1979-12-24 1979-12-24 Data processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16691179A JPS5690355A (en) 1979-12-24 1979-12-24 Data processing unit

Publications (1)

Publication Number Publication Date
JPS5690355A true JPS5690355A (en) 1981-07-22

Family

ID=15839919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16691179A Pending JPS5690355A (en) 1979-12-24 1979-12-24 Data processing unit

Country Status (1)

Country Link
JP (1) JPS5690355A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01145751A (en) * 1987-12-01 1989-06-07 Pfu Ltd Input/output control system

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159625A (en) * 1974-06-13 1975-12-24
JPS533029A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS5322330A (en) * 1976-08-13 1978-03-01 Nec Corp Address conversion system
JPS5434722A (en) * 1977-08-24 1979-03-14 Hitachi Ltd Address converting device
JPS5474632A (en) * 1977-11-28 1979-06-14 Nec Corp Data processor
JPS54142019A (en) * 1978-04-27 1979-11-05 Panafacom Ltd Address expandable treating system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159625A (en) * 1974-06-13 1975-12-24
JPS533029A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS5322330A (en) * 1976-08-13 1978-03-01 Nec Corp Address conversion system
JPS5434722A (en) * 1977-08-24 1979-03-14 Hitachi Ltd Address converting device
JPS5474632A (en) * 1977-11-28 1979-06-14 Nec Corp Data processor
JPS54142019A (en) * 1978-04-27 1979-11-05 Panafacom Ltd Address expandable treating system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01145751A (en) * 1987-12-01 1989-06-07 Pfu Ltd Input/output control system

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