JPS57207942A - Unpacking circuit - Google Patents
Unpacking circuitInfo
- Publication number
- JPS57207942A JPS57207942A JP56094397A JP9439781A JPS57207942A JP S57207942 A JPS57207942 A JP S57207942A JP 56094397 A JP56094397 A JP 56094397A JP 9439781 A JP9439781 A JP 9439781A JP S57207942 A JPS57207942 A JP S57207942A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- unpacking
- circuit
- image
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
Abstract
PURPOSE:To improve the efficiency of a titled circuit by reducing the accessing frequency against the memory and by quickly performing unpackings and transferrings, by eliminating the necessity of unpacking to be performed by software when packed information is transferred by unpacking. CONSTITUTION:An unpacking circuit UC and a data register DR are installed in an intermemory transfer module 3 placed between an image memory 4 coupled with a display device 5 and a main memory 2 coupled with an external memory 6. The transfer module 3 reads out source data stored in Address A of the main memory 2 in accordance with preset command information, sets the data in the register DR, and write them in the image memory 4 through the unpacking circuit UC. Threrfore, transfer of image information stored in the external memory 6 in the form of 16 bits can be completed when the reading out R from the main memory 2 is performed one time and writing W in the image memory 4 is performed four times.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56094397A JPS57207942A (en) | 1981-06-18 | 1981-06-18 | Unpacking circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56094397A JPS57207942A (en) | 1981-06-18 | 1981-06-18 | Unpacking circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57207942A true JPS57207942A (en) | 1982-12-20 |
JPS6145260B2 JPS6145260B2 (en) | 1986-10-07 |
Family
ID=14109126
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56094397A Granted JPS57207942A (en) | 1981-06-18 | 1981-06-18 | Unpacking circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57207942A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008502975A (en) * | 2004-06-16 | 2008-01-31 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Data processing device |
US8587458B2 (en) | 2011-12-07 | 2013-11-19 | International Business Machines Corporation | Unpacking a variable number of data bits |
-
1981
- 1981-06-18 JP JP56094397A patent/JPS57207942A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008502975A (en) * | 2004-06-16 | 2008-01-31 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Data processing device |
US9239702B2 (en) | 2004-06-16 | 2016-01-19 | Intel Corporation | Data processing apparatus |
US8587458B2 (en) | 2011-12-07 | 2013-11-19 | International Business Machines Corporation | Unpacking a variable number of data bits |
Also Published As
Publication number | Publication date |
---|---|
JPS6145260B2 (en) | 1986-10-07 |
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