JP4906135B2 - Memory card - Google Patents

Description

  The present invention relates to a memory card on which a security controller is mounted together with an interface controller and a memory.

  In Patent Document 1, a SIM (Subscriber Identity Module) is installed in a memory card conforming to the MMC standard in order to realize multi-bank and multi-function while maintaining compatibility with the MMC (Multi-Media Card: registered trademark) standard. Thus, a technique for enhancing security is described.

  Patent Document 2 describes a storage device on which a flash memory chip, an IC card chip that executes security processing, and a controller chip that controls them according to instructions from the outside are mounted.

  Non-Patent Document 1 describes a standard for a multimedia card.

International Publication WO01 / 84480 Pamphlet JP 2003-91704 A

The MultiMedia Card System Specification Version 3.3

  The present inventor studied a memory card that implements a multifunction by installing a security controller such as an IC card microcomputer together with an interface controller and a memory.

  First, when the interface controller and the security controller are connected, the operation power supply voltage supplied from the outside is stopped, the supply of the operation power supply voltage for the interface controller and the memory is stopped, and the operation power supply voltage is supplied only to the security controller. It has been clarified that there is an inconvenience in the operation mode in which only the security controller is turned on and the security processing is executed exclusively when it can be supplied. That is, if the operating power is not turned on to the interface controller, the output control state of the output buffer in the interface unit of the interface controller connected to the security controller may be indefinite and in a low impedance state. When a clock or signal for power-on reset or activation of the security controller is supplied from the outside in such a state, the clock or signal flows into the interface section in a low impedance state, resulting in noise that cannot be ignored. It has been found that there is a risk of malfunction. In particular, when the security controller or the like interfaces with the outside in a non-contact manner, there is a concern that the communication sensitivity may be significantly reduced.

  Second, when the security controller has a non-contact interface function, when the connection terminal of the external antenna for improving the communication sensitivity is provided on the wiring board of the card, the arrangement relationship with other connection terminals such as a signal and a clock is changed. The importance of consideration has been found by the inventors. In other words, if the routing of wiring to the connection terminals such as signals and clocks on the wiring board and the routing of wiring to the connection terminals of the external antenna are often complicated, the crosstalk will increase. Noise is superimposed on the signal line and the clock wiring by induction or induction. Alternatively, noise due to crosstalk or induction from the signal line or the clock wiring is superimposed on the high-frequency signal received from the external high-frequency antenna, and an error may occur in the input / output data during the non-contact operation. It is necessary to adopt an arrangement that can suppress the generation of such noise as much as possible for the connection terminal of the external antenna. Furthermore, when the operation power supply voltage level of the security controller is higher than the operation power supply voltage level of the interface controller when the supply of the operation power supply voltage for the interface controller and the memory is stopped and the operation power supply voltage can be supplied to the security controller Therefore, the same consideration as described above is required for the arrangement of the external connection terminals for supplying high-level operation power.

  An object of the present invention is to suppress the occurrence of noise in a memory card that implements a multifunction by mounting a security controller together with an interface controller and a memory.

  An object of the present invention is to suppress the generation of noise in an operation mode in which an operation power is turned on only for a security controller and a security process is executed in a memory card that implements a multifunction by installing a security controller together with an interface controller and a memory. There is.

  Another object is to reduce the power consumption of the entire memory card by separating the operating power of the interface controller and the security controller.

  Another object of the present invention is to arrange a connection terminal for connecting an external antenna to the security controller having a non-contact interface function in a memory card that realizes multi-function by mounting a security controller together with an interface controller and a memory. The purpose is to prevent the generation of noise in relation to other connection terminals.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A memory card according to the present invention includes an interface controller (7) connected to the external connection terminal on a wiring board on which a plurality of external connection terminals are formed, and a memory (8) connected to the interface controller. And a security controller (9) connected to the interface controller, and supply operating power to the security controller separately from the first external connection terminal (C4) that supplies operating power to the interface controller and memory. An interface unit of the interface controller that has a second external connection terminal (C15) that can be connected to the security controller receives an operation power from the second external connection terminal, and operates from the first external connection terminal. The power supply can be stopped.

  Even if the operation power supply to the interface controller is cut off, the interface section (11) is supplied with the operation power to the security controller, so the output of the interface section does not become indefinite, and an indefinite current flows there. It can suppress flowing and becoming noise. In order to prevent any unnecessary current from flowing through the interface unit, the interface unit may be controlled to a high impedance state in a state where the operation power supply from the first external connection terminal is stopped.

  In a specific form of the present invention, the interface unit has a signal level based on a first power supply voltage supplied to the first external connection terminal and a signal level based on a second power supply voltage supplied to the second external connection terminal. Level shift function for performing level shift between the two.

  In a specific form of the present invention, as an interface terminal of the security controller, a third external connection terminal (C11) for inputting a clock signal, a fourth external connection terminal (C13) for data input / output, and a reset signal input 5th external connection terminal (C10). At this time, the third external connection terminal to the fifth external connection terminal can be used by the interface controller as external connection terminals for input / output signals according to the card mode recognized by the interface controller. For example, it is possible to cope with several card modes having different numbers of parallel data input / output bits. When the interface controller uses the third external connection terminal to the fifth external connection terminal as data input / output external connection terminals, the security controller can interface with the outside via the interface controller. At this time, if the third external connection terminal to the fifth external connection terminal are separated from the interface controller by the separation switch circuit (12), they are connected to the third external connection terminal to the fifth external connection terminal. Thus, it is possible to suppress an undesired output of a signal exchanged with the interface controller according to the interface function of the security controller to the external circuit.

  As a specific form of the present invention, the security controller may be an IC card microcomputer capable of a non-contact interface with the outside and / or an IC card microcomputer capable of a contact interface with the outside. . Further, the security controller may be an IC card microcomputer capable of both a non-contact interface and a contact interface.

  As a specific form of the present invention, when the security controller is a microcomputer for an IC card capable of non-contact interface with the outside, an antenna connection terminal capable of connecting a high-frequency antenna for non-contact interface as the external connection terminal In the case of having (C14, C16), it is desirable that the antenna connection terminal is disposed adjacent to the second external connection terminal and in the vicinity of the first external connection terminal. Such an antenna connection terminal is used for connection of an external high-frequency antenna for increasing the sensitivity of the non-contact interface. The voltage applied to the antenna connection terminal is relatively high and the frequency is high. Therefore, if the routing of wiring to the connection terminals such as signals and clocks on the wiring board and the routing of wiring to the connection terminals of the external antenna are complicated, crosstalk will increase. Noise is superimposed on the signal line and the clock wiring by induction or induction. Alternatively, noise due to crosstalk or induction from the signal line or the clock wiring is superimposed on the high-frequency signal received from the external high-frequency antenna, and an error may occur in the input / output data during the non-contact operation. Since the antenna connection terminal is arranged adjacent to the second external connection terminal and in the vicinity of the first external connection terminal, the arrangement is suitable for suppressing noise generation as much as possible.

  The plurality of external connection terminals have a staggered arrangement in which the arrangement in the column direction is shifted between adjacent columns before and after the insertion direction of the memory card. With this staggered arrangement, it is possible to cope with the increase in the number of terminals by a relatively simple configuration in which a large number of slot terminals are alternately arranged in parallel in card slots from which memory cards are attached and detached. For example, the second external connection terminal to the fifth external connection terminal and the antenna connection terminal are arranged in a rear array adjacent to the memory card in the insertion direction. In particular, the second external connection terminal and the antenna connection terminal may be located at the center of the column direction arrangement. The second external connection terminals may be staggered with respect to the antenna connection terminals.

  As yet another specific form of the present invention, when the interface controller, the memory and the security controller are individual semiconductor chips, the semiconductor chip constituting the interface controller is stacked on the semiconductor chip constituting the memory, It is preferable to wire bond the electrodes of the wiring board to the electrode pads arranged along the sides in the same direction of the semiconductor chips. Bonding wires can be shortened and wire interference is reduced.

  [2] A memory card according to the present invention includes a wiring board on which a plurality of external connection terminals are formed, an interface controller connected to the external connection terminals, a memory connected to the interface controller, and a security controller. And a second external connection terminal capable of supplying operating power to the security controller separately from the first external connection terminal that is mounted and supplies operating power to the interface controller and the memory. An IC card microcomputer capable of a non-contact interface, wherein the external connection terminal has an antenna connection terminal to which an antenna for a non-contact interface can be connected, and the antenna connection terminal is the second external connection terminal Adjacent to the first external connection end It is disposed in the vicinity of.

  The plurality of external connection terminals have a staggered arrangement in which the arrangement in the column direction is shifted between adjacent columns before and after the insertion direction of the memory card. Due to this staggered arrangement, the card slot can be made multi-terminal with a relatively simple configuration in which a large number of slot terminals are alternately arranged in parallel with different projection amounts. For example, the second external connection terminal to the fifth external connection terminal and the antenna connection terminal are arranged in a rear array adjacent to the memory card in the insertion direction. In particular, the second external connection terminal and the antenna connection terminal may be located at the center of the column direction arrangement. The second external connection terminals may be staggered with respect to the antenna connection terminals.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In a memory card that implements a multifunction by installing a security controller together with an interface controller and a memory, it is possible to suppress the occurrence of noise in an operation mode in which only the security controller is turned on to perform security processing.

  In a memory card that realizes multi-function by installing a security controller together with an interface controller and memory, the arrangement of connection terminals for connecting an external antenna to the security controller having a non-contact interface function is related to other connection terminals. It is possible to prevent the generation of noise.

  It is possible to suppress the generation of noise in a memory card that implements a multifunction by installing a security controller together with an interface controller and a memory.

It is a block diagram which shows an example of the memory card based on this invention. It is explanatory drawing which shows the outline of communication portable terminal devices, such as a mobile telephone to which the memory card based on this invention is applied. It is explanatory drawing which illustrates the function allocation of the external connection terminal according to the card mode of a memory card. It is a circuit diagram which illustrates the output buffer which can be controlled to a high output impedance state in response to a power supply stop. It is explanatory drawing which shows the example which employ | adopted the bus switch in order to eliminate the output indefinite state of the said interface part at the time of power supply interruption. It is a circuit diagram which shows the circuit using a differential amplifier for level shift. It is a block diagram which shows the 2nd structural example of the memory card based on this invention. It is a block diagram which shows the 3rd structural example of the memory card based on this invention. It is a block diagram which shows the 4th structural example of the memory card based on this invention. It is a block diagram which shows the 5th structural example of the memory card based on this invention. It is a block diagram which illustrates the detail of an interface controller. It is a block diagram which shows the specific example of a dual way IC card microcomputer. It is explanatory drawing which shows an external appearance when the memory card based on this invention is sealed in the package of the standard size of MMC standard. It is explanatory drawing which shows an external appearance when the memory card based on this invention is sealed in the half size package of a MMC specification. It is explanatory drawing which shows the example which changed the part with respect to the shape of the external connection terminal of FIG.13 and FIG.14. It is explanatory drawing which shows the example which reduced the number of external connection terminals with respect to the external connection terminal of FIG.13 and FIG.14. It is a top view which illustrates the stack mounting structure of the said interface controller, flash memory, and IC card microcomputer which were each made into the semiconductor integrated circuit chip | tip separately. It is a longitudinal cross-sectional view of the mounting structure of FIG. FIG. 19 is a longitudinal sectional view showing a structure in which two IC card microcomputers are stacked on the stack structure of FIGS. 17 and 18; FIG. 11 is a plan view showing still another stack mounting structure of the interface controller, the flash memory, and the IC card myco that are each made into individual semiconductor integrated circuit chips. It is a longitudinal cross-sectional view with respect to the mounting structure of FIG. FIG. 22 is a longitudinal sectional view showing a structure in which two IC card microcomputers are stacked on the stack structure of FIGS. 20 and 21. It is explanatory drawing which shows the card slot in which a memory card and a memory card are inserted. It is explanatory drawing which shows the 1st process in which the memory card of FIG. 23 is inserted in a card slot. It is explanatory drawing which shows the 2nd process in which the memory card of FIG. 23 is inserted in a card slot. It is explanatory drawing which shows the 3rd process in which the memory card of FIG. 23 is inserted in a card slot.

《Communication portable terminal device》
FIG. 2 shows an outline of a communication portable terminal device such as a cellular phone to which a memory card according to an example of the present invention is applied. The communication portable terminal device 1 includes, for example, a microprocessor (MPU) 2 that controls the entire system, a baseband processing unit (BB) 3 that performs baseband processing such as modulation and demodulation for mobile communication, and a prescribed high frequency. A high-frequency unit (RFcl) 4 that performs transmission and reception and a memory card (MRYC) 5 are included. The MRYC 5 is detachably attached to a card slot (not shown) of the communication portable terminal device 1. MPU2 is positioned as a card host for MRYC5.

  MRYC5 has multi-functions such as memory storage function, high-level security processing function for e-commerce, low-level security processing function for charging in transportation, etc., content data encryption / decryption processing function, etc. provide.

<< MRYC with built-in IC card microcomputer >>
FIG. 1 illustrates the configuration of MRYC5. The MFMC 5 is an interface controller 7, a flash memory 8 connected to the interface controller 7, and a security controller connected to the interface controller 7 on a wiring board on which a plurality of external connection terminals C 1 to C 16 are formed. An IC (Integrated Circuit) card microcomputer (also referred to as an IC card microcomputer) 9 is mounted. The interface controller 7, the flash memory 8, and the IC card microcomputer 9 are each constituted by individual semiconductor integrated circuit chips.

  The interface controller 7 has an external interface function as a memory card, a memory interface function according to the specifications of the flash memory, and an IC card microcomputer interface function for interfacing with an IC card microcomputer using a memory card command. Here, MRYC5 satisfies the external interface specification as a memory card compliant with the multimedia card standard.

  The flash memory 8 is an electrically erasable and writable nonvolatile memory. The flash memory 8 includes a nonvolatile memory cell transistor (also referred to as a flash memory cell) that is electrically erasable and writable, although not particularly illustrated. The flash memory cell is not particularly shown, but a so-called stacked gate structure having a floating gate, or a so-called split gate structure comprising a memory transistor portion and an select transistor portion having an ONO (oxide nitride oxide) gate insulating film. Have In the flash memory cell, the threshold voltage increases when electrons are injected into the floating gate or the like, and the threshold voltage decreases when electrons are extracted from the floating gate or the like. The flash memory cell stores information corresponding to the level of the threshold voltage with respect to the word line voltage for reading data. Although not particularly limited, in this specification, a state in which the threshold voltage of the memory cell transistor is low is referred to as an erased state, and a state in which the threshold voltage is high is referred to as a written state.

  Although not shown in particular, the IC card microcomputer 9 includes a CPU, a non-volatile memory for storing the operation program and control information used for authentication, and performs authentication processing according to the operation program. Here, the IC card microcomputer 9 is a contact / non-contact dual-way IC card capable of a contact interface and a non-contact interface with the outside. The contact interface is performed by serial communication using a 1-bit data input / output terminal I / O, a clock terminal CLK, and a reset terminal RES. The non-contact interface is performed by high-frequency communication using an antenna connected to the terminals TML1 and TML2. In the figure, the external antenna 10 and the tuning capacitor 13 are representatively shown. Although not specifically shown, the non-contact interface is provided with an internal antenna connected to the terminals TML1 and TML2 inside the MRYC5 package or on the circuit board, and when the external antenna 10 is connected to the terminals C14 and C16, the internal antenna can be separated by a switch. A configuration may be provided.

  Among the external connection terminals C1 to C16, functions and arrangement of C1 to C7 conform to the MMC standard, and C8 to C13 correspond to a multi-bit data bus. C14 to C16 are newly established.

  FIG. 3 shows the function assignment of the external connection terminals C1 to C16 according to the card mode of MRYC5. The 1-bit mode, 4-bit mode, and 8-bit mode mean the number of data input / output bits with respect to the outside of MRYC5. Only the non-contact card function means a case where an IC card microcomputer having only a non-contact interface function is mounted as an external interface function, and details of this example will be described later. In the figure, RSV (for MMC) is a reserve terminal in MMC mode, CS (for SPI) is a chip select terminal in SPI mode, CMD is a command terminal, Vss1 and Vss2 are circuit ground terminals, Vdd is a power supply terminal, and CLK is a memory. Card clock terminal, DAT is serial data input / output terminal, RES-ic is IC card microcomputer reset terminal, CLK-ic is IC card microcomputer clock terminal, Vcc-ic is IC card microcomputer power supply terminal, LA and LB are An antenna connection terminal, Vcc-IC is a dedicated power supply terminal for the IC card microcomputer, and DAT0 to DAT7 are parallel data input / output terminals.

  As is apparent from FIG. 3, C1 to C9 are basically assigned to the memory card interface function, and C10 to C16 are assigned to the IC card interface function. However, although C10 to C13 are assigned to the IC card interface function in the 1-bit mode and the 4-bit mode, they are assigned to the memory card interface function as parallel data input / output terminals of DAT4 to DAT7 in the 8-bit mode. The difference in function assignment of the terminals C10 to C13 appears as wirings L1 to L4 connecting the interface controller 7 and the IC card microcomputer 9 in the circuit of FIG. In short, the wirings L1 to L4 assigned to the connection to the external connection terminals C10 to C13 in the interface unit 11 of the interface controller 7 are connected to the terminals Vcc, I / O-ic, CLK-ic, and RES-ic of the IC card microcomputer 9. To do. In the 8-bit mode, the separation switch circuit 12 is cut off by the control of the interface controller 7 when the interface controller 7 communicates with the IC card microcomputer 9, and separates the connection with the external connection terminals C10, C11, C13. When the interface controller 7 communicates with the outside using C12 as DAT6, the connection with the terminal Vcc of the IC card microcomputer 9 is separated, and the functions of the data terminals DAT4 to DAT7 assigned to the external connection terminals C10 to C13 in the 8-bit mode Selection is performed on the MRYC 5 side based on the difference between the functions of the terminals Vcc, I / O, CLK, and RES connected to the wirings L1 to L4.

  Here, the operation power supply to the IC card microcomputer 9 will be described with reference to FIG. In addition to the external connection terminal (first external connection terminal) C4 for supplying the operation power supply Vdd to the interface controller 7 and the flash memory 8, an external connection end terminal (for supplying the operation power supply Vcc-IC to the IC card microcomputer 9) A second external connection terminal) C15. The operation power supply to the IC card microcomputer 9 is performed by C12 and C15 in the configuration of FIG. 1, but the operation power supply by C12 is not essential. C15 can be substituted. Note that the switch SW1 of the separation switch circuit 12 is a switch that is required by adding the terminal C15. That is, Vcc-IC is always supplied from C15 to the wiring L4 regardless of the usage form of C12.

  The terminal C15 also supplies operating power to the interface unit 11, and when the supply of operating power Vdd from C4 is stopped, the input impedance of the input / output circuit in the interface unit 11 connected to the wirings L1 to L4 is reduced or the output is undefined. Eliminate. That is, when the supply of the power supply Vdd from C4 is stopped in order to suppress wasteful power consumption when only the IC card microcomputer 9 of MRYC5 is operated, the output state of the output buffer in the interface unit 11 becomes indefinite. In this state, when the IC card microcomputer 9 is operated by performing a power-on reset of the IC card microcomputer 9 with a contact interface using C10 to C13, for example, a clock signal from C11 flows into the output buffer of the interface unit 11. Overcurrent flows or a signal input / output via C13 flows into the output buffer of the interface unit 11 and overcurrent flows. Such an overcurrent becomes noise and increases wasteful power consumption. Further, such noise deteriorates the sensitivity and communication characteristics at the non-contact interface via the antenna 10. When the supply of the operating power supply Vdd to the interface controller 7 is stopped, the output power of the output buffer of the interface section 11 connected to the wirings L1 to L4 is indefinite by supplying the operating power supply Vcc-IC for the IC card microcomputer 9 from the C15 to the interface section 11. Cancel the condition.

  In order to eliminate the indefinite state, for example, the output buffer connected to the wirings L1 to L4 is controlled to be in a high impedance state in response to the supply stop of the power supply Vdd.

  FIG. 4 illustrates an output buffer that can be controlled to a high impedance state in response to the stop of the supply of the power supply Vdd. The output buffer 15 includes, for example, a series circuit of a CMOS inverter 16 using Vdd as an operation power supply and a CMOS clocked inverter 17 using Vcc-IC as an operation power supply. The CMOS clocked inverter 17 mainly includes a series circuit of p-channel MOS transistors Qp1 and Qp2 and n-channel MOS transistors Qn3 and Qn4, and includes an inverter 18 and a power supply voltage detector 19 that switch-control the MOS transistors Qp1 and Qn4. The power supply voltage detector 19 is a detection signal that is set to the high level of the Vcc-IC level when the power supply voltage Vdd is turned on and exceeds the operation guarantee voltage, and to the low level that is the ground voltage Vss of the circuit when the supply of the power supply voltage Vdd is cut off. 20 is output. The inverter 18 uses Vcc-IC as an operation power supply. As a result, when Vdd is supplied with Vcc-IC turned on, the clocked inverter 17 is enabled for output operation, and when supply of Vdd is cut off, the clocked inverter 17 is controlled to a high impedance state. Is done. The power source Vdd is connected to the power source of the clocked inverter 17 through the high resistance R1 in order to stabilize the operation when the Vcc-IC is shut off.

  In FIG. 4, it is considered that the levels of Vdd and Vcc-IC are different and Vdd ≦ Vcc-IC. That is, when the logic threshold voltage (VTL) of the inverter 16 is Vdd / 2, the logic threshold voltage of the clocked inverter 17 is also set to Vdd / 2. In short, the output buffer 15 has a level shift function for performing a level shift between the signal belt by the power supply voltage Vdd and the signal level by the power supply voltage Vcc-IC.

  Note that the output indefinite state of the interface unit when the power supply Vdd is shut off is not limited to the high impedance control in the output buffer 15 having the level shift function, and as illustrated in FIG. A bus switch 21 that is turned off when the power supply Vdd is cut off is used for disconnection from the card microcomputer, and a circuit using the differential amplifier shown in FIG. In the circuit of FIG. 6, the power source Vdd is connected to the power source of the differential amplifier via the high resistance R1 in order to stabilize the operation when the Vcc-IC is shut off.

  FIG. 7 shows a second configuration example of MRYC5. In contrast to FIG. 1, the separation switch circuit 12 is composed of only the switch SW1. When the interface controller 7 communicates with the IC card microcomputer 9 in the 1-bit mode or the 4-bit mode, a switch that is cut off by the control of the interface controller 7 and separates the connection with the external connection terminals C10, C11, and C13 is unnecessary. It was. Functions of data terminals DAT4 to DAT7 assigned to the external connection terminals C10 to C13 in the 8-bit mode and functions of terminals Vcc, I / O, CLK, and RES connected to the wirings L1 to L4 in the 1-bit mode or the 4-bit mode The selection based on the difference may be performed outside the MRYC 5. Other configurations are the same as those in FIG.

  FIG. 8 shows a third configuration example of MRYC5. In contrast to the configuration of FIG. 1, the operation power supply to the IC card microcomputer is performed only at the terminal C15. The switch SW1 becomes unnecessary. Although not shown in particular, it is possible to employ a configuration in which the entire separation switch circuit 12 is eliminated by combining FIGS.

  FIG. 9 shows a fourth configuration example of MRYC5. The MRYC 5 shown in the figure does not show the separation switch circuit 12, but has only the IC card microcomputer 9 having the connection relationship shown in FIG. 7 or 8 and the contact interface, and only the interface unit 11 of the interface controller 7. Another IC card microcomputer 24 to be connected is mounted. Other configurations are the same as those in FIG. In this embodiment, the IC card microcomputer 24 operates as a coprocessor of the interface controller 7 and does not operate independently by the IC card microcomputer 24 alone.

  FIG. 10 shows a fifth configuration example of MRYC5. The MRYC 5 shown in the figure is configured by further mounting another IC card microcomputer 25 having only a non-contact interface with respect to the configuration of FIG. 7 or FIG. Supply of operating power to the IC card microcomputer 9 is performed by C12 (Vcc-ic), and supply of operating power to the IC card microcomputer 25 is performed by C15 (Vcc-IC). Since the IC card microcomputer 25 having a non-contact interface can use the induced electromotive force generated by the electromagnetic wave crossing the antenna 11 as its operation power supply, the operation power supply from the C15 to the IC card microcomputer 25 is not essential. When the operation of the IC card microcomputer 25 is stabilized by stabilizing the power supply, the operation power supply from the C15 is meaningful.

  FIG. 11 illustrates details of the interface controller 7. The interface controller 7 includes a host interface circuit 30, a microcomputer 31, a flash controller 32, a buffer controller 33, a buffer memory 34, and an interface unit 11. The buffer memory 34 is composed of DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). An IC card microcomputer 9 is connected to the interface circuit 11. The microcomputer 31 includes a CPU (central processing unit) 37, a program memory (PGM) 38 that holds an operation program for the CPU 37, a work memory (WRAM) 39 that is used as a work area for the CPU 37, and the like. The control program of the interface control mode corresponding to the MMC specification is held by the PGM 38.

  When the host interface circuit 30 issues a memory card initialization command, it enables the microcomputer 31 to execute a control program in an MMC interface control mode by an interrupt. The microcomputer 31 controls the external interface operation by the host interface circuit 30 by executing the control program, controls the access (write, erase and read operations) and data management to the flash memory 8 by the flash controller 32, and the buffer. The controller 33 controls format conversion between a data format specific to the memory card and a common data format for the memory.

  The buffer memory 34 temporarily holds data read from the flash memory 8 or data written to the flash memory 8. The flash controller 32 operates the flash memory 8 as a hard disk compatible file memory and manages data in units of sectors.

  The flash controller 32 includes an ECC circuit (not shown), adds an ECC code when storing data in the memory, and performs error detection / correction processing using the ECC code on the read data.

  FIG. 12 illustrates details of the IC card microcomputer 9. The IC card microcomputer 9 includes a CPU 41, a RAM (random access memory) 42 as a work RAM, a timer 43, an EEPROM (electrically erasable and programmable read only memory) 44, a coprocessor unit 45, a mask. A ROM (Read Only Memory) 46, a system control logic 47, an input / output port (I / O port) 48, a data bus 49, an address bus 50, and an RF unit 51 are provided.

  The mask ROM 46 is used to store an operation program (encryption program, decryption program, interface control program, etc.) and data of the CPU 41. The RAM 42 serves as a work area for the CPU 41 or a temporary storage area for data, and is composed of, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). When an IC card command is supplied to the I / O port 48, the system control logic 47 decodes it and causes the CPU 41 to execute a processing program necessary for executing the command. That is, the CPU 41 accesses the mask ROM 46 with an address instructed by the system control logic 47, fetches an instruction, decodes the fetched instruction, and performs operand fetch and data operation based on the decoding result. The coprocessor unit 45 performs a remainder calculation process in RSA or elliptic curve cryptographic calculation according to the control of the CPU 41. The I / O port 48 has a 1-bit input / output terminal I / O, and is used both for data input / output and external interrupt signal input. The I / O port 48 is coupled to a data bus 49, to which the CPU 41, RAM 42, timer 43, EEPROM 44, coprocessor unit 45 and the like are connected. The system control logic 47 controls the operation mode and interrupt of the IC card microcomputer 9 and further includes a random number generation logic used for generating an encryption key. When the reset operation is instructed by the reset signal RES, the IC card microcomputer 9 is initialized, and the CPU 41 starts executing instructions from the top address of the program in the mask ROM 46. The IC card microcomputer 9 is operated in synchronization with the clock signal CLK.

  The EEPROM 44 is electrically erasable and writable, and is used as an area for storing data such as ID information and authentication certificate used to identify an individual. A flash memory or a ferroelectric memory may be employed in place of the EEPRPM 44. The IC card microcomputer 9 supports one or both of a contact interface using an external connection terminal as an interface with the outside and a non-contact interface using an antenna. The RF unit 51 for performing a non-contact interface has chip antenna terminals TML1 and TML2. When power is supplied from the RF unit 51 via the antenna, or when a non-contact interface is selected via the internal bus by the system control logic 47, the RF unit 51 causes the antenna to transmit a predetermined electromagnetic wave (for example, a high-frequency wave). An operating power source is generated using an induced electromotive force generated by crossing a magnetic flux or a microwave as an operating power source, and an internal clock signal CLK based on the induced current corresponding to the frequency of the predetermined radio wave, the predetermined radio wave Internal data separated by the RF unit 51 and further a reset signal RES are generated, and information is input / output from the antenna in a non-contact manner. In the IC card microcomputer 9, the RF unit 51 that operates via the non-contact interface is preferably configured by a small-scale circuit independent of the IC card operating CPU 41 that operates via the contact interface. The RF unit 51 includes a circuit necessary for contactless card operation, such as a contactless card processor, a memory used for a control program area and a work area of the processor, and an RF transmission / reception and power supply circuit unit. As described above, the RF unit 51 is composed of an independent small-scale circuit such as a processor function and its control program. Therefore, for example, even in an environment where power supply via a contact terminal cannot be obtained, external induction It becomes easy to operate the circuit with electric power. The RF unit 51 can also input and output data between the non-contact interface part and the contact interface part via the internal data bus 49 and the address bus 50.

  The security processing operation in MRYC5 will be described. For example, user identification information is stored in the secure area of the flash memory 8. When downloading the content data, the license information encrypted with the user identification information as a secret key is downloaded together. A decryption key for decrypting the content data is included in the license information, and the license information is decrypted using the user identification information as the decryption key. This protects the copyright of the content data. Such security processing is performed by program control by the microcomputer 31.

  A security process by the IC card microcomputer 9 will be described. For example, the IC card microcomputer 9 realizes an authenticated function by an evaluation / certification organization of ISO / IEC15408 that can be used for an electronic payment service or the like. The EEPROM 44 has a predetermined authentication certificate, and when there is an authentication request from the host, the authentication certificate is sent, and subsequent communication processing is made possible on the condition that authentication is obtained for this. . Such a security processing operation program is stored in the mask ROM 46. It is desirable from the viewpoint of security that the authentication process by the IC card microcomputer 9 is performed in an environment closed inside the IC card microcomputer 9. In this respect, it is meaningful to perform only an external interface through the external connection terminals C10 to C13 or an antenna by turning on only the power source of the IC card microcomputer 9. If there is no security problem in terms of use or technology, it is possible to perform security processing via the interface controller 7. Further, in the process from the manufacture of MRYC to the product shipment, various application software can be easily written to the IC card microcomputer 9 and the card issuance process can be performed via the external connection terminals C10 to C13.

  For example, as described above, when the IC card microcomputer 9 has been authenticated by an ISO / IEC15408 evaluation / certification organization that can be used for an electronic payment service or the like, MRYC5 is inserted into a card holder such as a cash card, credit card, or commuter pass, These card functions can be realized using a non-contact interface.

  Considering that the IC card microcomputer 9 is used for high-level security processing such as electronic payment, a power-on reset that initializes all internal states against the abnormal state of the IC card microcomputer 9 is sent to the interface controller 7 and the like. It is more likely to be performed more frequently. Considering this, since the IC card microcomputer 9 has dedicated power supply terminals C12 (Vcc-ic) and C15 (Vcc-IC), the IC card microcomputer 9 can be freely operated without resetting the entire MRYC5. Power-on reset is possible. As a result, the security of MRYC 5 can be improved while ensuring security.

《MRYC external connection terminal arrangement》
FIG. 13 shows an appearance when the MRYC 5 is sealed in an MMC standard half size package. FIG. 14 shows an external appearance when the MRYC 5 is sealed in a standard size package of the MMC standard. Both drawings clearly show the arrangement of the external connection terminals, and both arrangements are equal. The function assignment of each of the terminals C1 to C16 is as described with reference to FIG. C1 to C7 correspond to the primitive MMC standard. C8 to C9 are expansion terminals for 4-bit mode, C10 to C13 are IC card microcomputer contact interfaces and expansion terminals for 8-bit mode, C14 and C16 are expansion terminals for external antenna connection, and C15 is dedicated to the IC card microcomputer This is an expansion terminal for power supply. C1 to C16 have a staggered arrangement in which the arrangement in the column direction is shifted between adjacent columns before and after the memory card insertion direction (arrow X direction). The first column is C1 to C7. C8 to C13 constitute a second row spaced from the first external connection terminal row. The sizes of the external connection terminals C10 to C13 are the same as the sizes of the external connection terminals C1 to C7 within a certain range. The external connection terminal of C8 is arranged in the first row and extends to a position adjacent to the terminal C7 at one end in the row direction of the connector terminal row in the row direction, and the external connection terminal of C9 is arranged in the first row. It is arranged and extends to a position adjacent to the terminal C1 of the terminal row, partially overlapping in the row direction. The first row of external connection terminal rows and the second row of external connection terminal rows are arranged in a staggered manner with the row direction arrangement of the external connection terminals shifted from each other in the row direction, except for C4 and C15. Yes.

  Due to the zigzag arrangement, the card slot (not shown) in which the MRYC 5 is mounted is made into a multi-terminal by a relatively simple configuration in which a large number of slot terminals (pins) are alternately arranged in parallel with different projection amounts. Can respond. In view of the increase in the number of terminals, terminals C14 to C16 newly provided in the area between the C11 and C12 in the rear row are also arranged in a staggered manner.

  When the antenna connection terminals C14 and C16 that can be connected to the high-frequency antenna 10 for the non-contact interface are provided as the external connection terminals, the antenna connection terminals C14 and C16 are connected to the external connection terminal C15 as the IC card microcomputer dedicated power supply terminal. Adjacent to the external connection terminal C4 for supplying power Vdd. Such antenna connection terminals C14 and C16 are used for connection of an external high-frequency antenna in order to increase the sensitivity of the non-contact interface in the IC card microcomputer. The voltage applied to the antenna connection terminals C14 and C16 is relatively high and the frequency is high. Therefore, the routing of the wiring to the connection terminals such as signals and clocks on the wiring board of the MRYC 5 and the routing of the wiring to the connection terminals C14 and C16 of the external antenna are complicated and may be close to each other or straddle. When the number increases, noise is superimposed on the signal line and the clock wiring due to crosstalk or induction. Alternatively, noise due to crosstalk or induction from the signal line or the clock wiring is superimposed on the high frequency signal received from the external high frequency antenna, and an error may occur in the data separated by the RF unit 51. Since the antenna connection terminals C14 and C16 are arranged adjacent to the external connection terminal C15 serving as the IC card microcomputer dedicated power supply terminal and in the vicinity of the external connection terminal C4 for supplying the power Vdd, the arrangement minimizes the generation of noise. The arrangement is suitable for suppressing.

  The shape of the external connection terminal described in FIGS. 13 and 14 can be partially changed as shown in FIG. Here, the shapes of C9 and C8 are shortened. This is intended to correspond to the card slot in which the position of the terminal contacting C8 and C9 of the card slot is in the first row. Also, as illustrated in FIG. 16, the number of external connection terminals can be reduced. The external connection terminals C8 and C9 are abolished, and the terminal arrangement takes into account the MMC standard 1-bit mode and IC card microcomputer contact interface support. 15 and 16, the staggered arrangement of the external connection terminals and the arrangement relationship between the antenna connection terminals C14 and C16 and the IC card microcomputer dedicated power supply terminal C15 are followed as they are.

《Insertion into card slot and power supply》
23 to 26 show the process of inserting a memory card into the card slot and the power supply to the memory card obtained by considering the process.

  FIG. 23 shows a memory card 5 and a card slot 70 into which the memory card 5 is inserted. The card slot 70 has a sensor 71 for detecting the insertion of the memory card 5 and external connection terminals C1 to C16 of the memory card 5. Terminals 72 to 87 are provided in contact with each other, and an external antenna 88 is connected to the terminals 85 and 87.

  FIG. 24 shows a first process in which the memory card 5 is inserted into the card slot 70. In the stage of the first process, the terminal 86 connected to the terminal C15 is in contact with the terminal C4 of the memory card 5, and the terminals 79 to 85, 87 of the card slot 70 are the terminals C1 to C1 of the first row of the memory card 5. This indicates that there is a possibility of contact with C9. A terminal C15 of the memory card 5 is a terminal for supplying a potential Vcc-IC and is supplied with the same or higher potential as the power supply Vdd supplied to the interface controller 7 and the flash memory 8. In this state, the Vcc-IC is supplied to the interface controller 7 and the flash memory 8, and the terminals 79 to 85 and 87 of the card slot 70 are brought into contact with the terminals C1 to C9 of the first column of the memory card 5, so that an electrical circuit is obtained. May be formed. Since the external antenna 88 generates a potential in accordance with an external electric field, the terminals 85 and 87 may come into contact with terminals other than the antenna connection terminals C14 and C16, and this potential may be applied to the interface controller 7.

  FIG. 25 shows a second process in which the memory card 5 is inserted into the card slot 70. In the stage of the second process, the terminals 79 to 85 and 87 of the card slot 70 do not contact the terminals C1 to C9 of the first row of the memory card 5, but the terminals 75 and 86 of the card slot 70 are not connected to the memory card 5. There is a possibility that Vcc-IC is supplied to a circuit (not shown) for supplying Vdd to the terminal 75, which is connected via the external connection terminal C4. Further, when the terminal 75 and the terminal 86 are in contact with the terminal C4, the Vcc-IC is supplied to the interface controller 7 and the flash memory 8, and the terminals 72 to 74 and 76 to 80 are in contact with the terminals C1 to C3 and C5 to C9. Therefore, there is a possibility that a circuit is electrically formed.

  FIG. 26 shows a third process in which the memory card 5 is inserted into the card slot 70. In the stage of the third process, the terminals 72 to 87 of the card slot 70 and the terminals C1 to C16 of the memory card 5 are appropriately connected.

  The problems that may occur in the process shown in FIGS. 24 and 25 include a solution in the memory card 5 and a solution in the host device having the card slot 70.

  As a solution in the memory card 5, a power circuit is provided between the terminal C4, the interface controller 7 and the flash memory 8, and after detecting that the power Vdd is supplied from the terminal C4, the interface controller 7 In addition, supply of operating power to the flash memory 8 may be started, and the terminals C1 to C13 may be connected to the interface controller 7.

  On the other hand, a solution in the host device can be solved by starting the supply of the Vcc-IC and the supply of the potential generated in the external antenna 88 in the third process. In other words, after the sensor 71 detects that the terminals 72 to 87 of the card slot 70 are not in process contact with the terminals C1 to C16 of the memory card, the supply of Vcc-IC may be started. The terminals of the memory card 5 and the card slot 70 are formed so that the terminals 85 and 87 of the card slot 70 do not cause stepwise contact with the terminals of the memory card 5, or between the external antenna 88 and the terminals 85 and 87. A switch circuit that can be electrically connected / disconnected is provided, and after the sensor 71 detects that no process contact is made, the external antenna 88 may be electrically connected to the terminals 85 and 87.

  The potentials Vdd, Vss1, and Vss2 may be constantly supplied, or may be started after the sensor 71 detects that the memory card 5 has been inserted into the card slot 70. This is because the terminals 74 and 77 of the card slot 70 are supply terminals for a reference potential, and there is no process contact in the illustrated structure. Further, since the terminal 75 is a supply terminal for Vdd having the same potential as or lower than that of the Vcc-IC, a circuit (not shown) for supplying the Vcc-IC even if it is connected to the terminal 86 via the terminal C4. This is because it is considered that no particular problem will occur even if Vdd is supplied to.

<Pulling out from card slot and supplying power>
Although not shown, the case where the memory card 5 is pulled out from the card slot 70 will be considered. In this case, when the memory card 5 is pulled out from the card slot 70 during the data erasing or data writing operation in the flash memory 8, the supply of the operating power to the flash memory 8 is interrupted, which is undesirable. In some cases, the memory card 5 itself cannot be recognized due to data corruption or a state called depletion. In order to avoid such a situation, when the host device detects that the memory card 5 is pulled out from the card slot 70 by the sensor 71, the host device notifies the memory card 5 via a predetermined terminal, and The potential Vdd may be supplied from the terminal 86. Accordingly, the potential Vdd can be supplied to the terminal C4 from the second process of FIG. 25 to the first process of FIG. Further, in order to increase the contact time of the terminal 74 with the terminal C3, specifically, the terminal 74 is made as long as the terminal 84 and the contact point with the terminal C3 is made longer. It becomes possible to maintain an electrical connection. As a result, the memory card 5 can complete the writing of data, or can secure a time for performing at least the process of avoiding the depletion state in response to the detection notification from the sensor 71.

《Chip stack structure》
FIG. 17 is a plan view showing a stack mounting structure of the interface controller 7, the flash memory 8, and the IC card microcomputer 9 each formed as an individual semiconductor integrated circuit chip, and FIG. 18 is a longitudinal section of the mounting structure. Shown schematically. External connection electrodes C1 to C16 are formed on one surface of a wiring substrate 60 such as a glass epoxy resin substrate on which a required wiring layer is formed, and a number of bonding pads 61 connected to the required wiring are formed on the other surface. ing. The bonding pad 61 is formed of a conductive pattern such as aluminum, copper or iron alloy. The external connection electrodes C1 to C16 are formed by applying gold plating, nickel plating, palladium plating or the like to a conductive pattern such as aluminum, copper, or iron alloy. The connection between the external connection electrodes C1 to C16 and the bonding pad 61 is performed by a wiring pattern (not shown) on the wiring board 60 and a through hole penetrating the wiring board 60 in the thickness direction. On the wiring board 60, two individual flash memories 8 are stacked in a shifted manner, and an interface controller 7 formed as a single chip is stacked thereon. The wiring substrate 60 and the chip, and the chip and the chip are bonded by the die bond agent 62. In the stacked three chips, the electrode pads 64 are arranged along the sides in the same direction in the stacked state, and the bonding pads 61 corresponding to the wiring board are wired to the arranged electrode pads 64 by the bonding wires 65. Bonded. Since the bonding electrode pads 64 of the three stacked chips are arranged along the sides in the same direction in the stacked state, the bonding wire 65 can be shortened and the interference of the wire 65 is also reduced. The single chip IC card microcomputer 9 is die bonded to the wiring substrate 60 as a single unit, and the chip electrode pads are bonded to the corresponding bonding pads of the circuit board. The chips stacked on the wiring board 60 are sealed with a resin mold or the like. Reference numeral 66 denotes a mold sealing region.

  FIG. 19 shows a structure in which the IC card microcomputer 9 is stacked in two chips with respect to the stack structure shown in FIGS. If the chips of the two IC card microcomputers 9 are the same type and the same size, the electrode pads on the chips are hidden if they are directly stacked. In that case, a spacer dummy chip 67 may be sandwiched between them. Of course, the dummy chip 67 is smaller than the IC card microcomputer chip.

  FIG. 20 is a plan view showing still another stack mounting structure of the interface controller 7, the flash memory 8, and the IC card microcomputer 9 each formed as an individual semiconductor integrated circuit chip, and FIG. 21 shows the mounting structure. A longitudinal section is schematically shown. The difference from FIGS. 17 to 19 is that two flash memories 8 made into individual chips are stacked, and an interface controller 7 and an IC card microcomputer 9 made into individual chips are stacked separately. Other configurations are the same as those of the stack structure of FIGS. 17 and 18, and members having the same functions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 22 shows a structure in which two IC card microcomputers 9 are stacked with respect to the stack structure shown in FIGS. Since the chips of the two IC card microcomputers 9 are the same type and the same size, they are not directly stacked, and a spacer dummy chip 67 is sandwiched between them. The flash memory 8 can be a chip stack of one chip or three or more chips as required.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the present invention can be widely applied not only to MMC standard memory cards but also to multi-function memory cards conforming to other standards. Therefore, the function, arrangement, number, etc. of the external connection terminals can be changed as appropriate. The memory is not limited to a flash memory, and may be a memory of other storage format such as a ferromagnetic memory. The security controller is not limited to the one that realizes an authenticated function by an ISO / IEC 15408 evaluation / certification organization. It may be a microcomputer that performs simple encryption / decryption.

DESCRIPTION OF SYMBOLS 5 Memory card 7 Interface controller 8 Flash memory 9 Dual way IC card microcomputer 10 Antenna 11 Interface part 12 Separation switch circuit C4 Vdd supply external connection terminal (first external connection terminal)
C12 Vcc-ic supply external connection terminal C15 Vcc-IC supply external connection terminal (second external connection terminal)
C11 CLK-ic assignment external connection terminal (third external connection terminal)
C13 I / O-ic assignment external connection terminal (fourth external connection terminal)
C10 RES-ic assignment external connection terminal (fifth external connection terminal)
C14, C16 External connection terminal for antenna connection 12 Separation switch circuit 15 Output buffer 17 Clocked inverter 24 Contact interface type IC card microcomputer 25 Non-contact interface type IC card microcomputer 60 Circuit board 61 Electrode (bonding pad) on wiring board
64 Electrode Pad on Semiconductor Chip 65 Bonding Wire

Claims (5)

On the wiring board on which a plurality of external connection terminals are formed, an interface controller connected to the external connection terminals, a memory connected to the interface controller, and a security controller are mounted,
A second external connection terminal capable of supplying operating power to the security controller separately from the first external connection terminal supplying operating power to the interface controller and the memory;
The security controller is an IC card microcomputer capable of non-contact interface with the outside,
An antenna connection terminal capable of connecting an antenna for a non-contact interface as the external connection terminal;
The antenna connection terminal is disposed adjacent to the first external connection terminal adjacent to the second external connection terminal, and closer to the second external connection terminal than the first external connection terminal. memory card being arranged. Wherein the plurality of external connection terminals, a memory card 請 Motomeko 1, wherein it has a staggered arrangement arranged in the column direction is shifted between rows mutually adjacent in the longitudinal insertion direction of the memory card. 3. The memory card according to claim 2, wherein the second external connection terminal and the antenna connection terminal are arranged in a rear array adjacent to each other in the memory card insertion direction . The second claim 3 Symbol mounting a memory card of the external connection terminal and the antenna connection terminal is characterized in that positioned at the center of the column direction arrangement. It said second external connection terminal according to claim 4 Symbol placing memory card characterized in that it is staggered with respect to the antenna connection terminal.

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