JP3772740B2 - Manufacturing method of electronic parts - Google Patents

Manufacturing method of electronic parts Download PDF

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JP3772740B2
JP3772740B2 JP2001389556A JP2001389556A JP3772740B2 JP 3772740 B2 JP3772740 B2 JP 3772740B2 JP 2001389556 A JP2001389556 A JP 2001389556A JP 2001389556 A JP2001389556 A JP 2001389556A JP 3772740 B2 JP3772740 B2 JP 3772740B2
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substrate
electrode
circuit element
sealing frame
bonding
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JP2003188294A (en
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好司 村田
昭大 三輪
通伸 前阪
広貴 堀口
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は回路素子を基板上に金属突起電極を介して実装し、回路素子の回路部を気密的に封止した電子部品の製造方法に関するものである。
【０００２】
【従来の技術】
従来、弾性表面波素子（ＳＡＷ素子）、高周波デバイスなどの電子部品の製造方法として、回路素子に設けられた回路部と基板に設けられた電極のいずれか一方に金属突起電極を設け、回路素子の表面と基板の表面とのいずれか一方に、回路素子の回路部を取り囲む封止枠を設け、回路素子と基板とを対面させて回路部と基板の電極とを金属突起電極によって接合するとともに、回路素子と基板との間の空間を封止枠によって気密的に封止する電子部品の製造方法が提案されている（例えば特開２０００−７７９７０号公報参照）。上記突起電極として例えばＡｕバンプが使用され、封止枠としてはんだ等の卑金属材料が使用されている。そして、突起電極の高さを封止枠の高さに比べて高くしてある。
【０００３】
上記回路素子を基板にマウントするには、まず熱圧着ツールによって回路素子の背面を吸着し、圧着ステージ上に位置決めされた基板に対して回路素子の回路部を対面させて接合する。この時、突起電極の高さが封止枠の高さに比べて高いので、熱圧着ツールを下降させると、まず突起電極が回路素子の電極パッドに当たる。この状態で熱圧着ツールを加熱しかつ加圧することで、熱および圧力によって突起電極が押しつぶされ、封止枠が回路素子の環状電極に接触し、溶融する。そして、熱によって突起電極と素子の電極パッドとが拡散接合される。このように従来の製造方法では、突起電極の接合と封止枠の接合とを同時に行っている。
【０００４】
【発明が解決しようとする課題】
突起電極としてＡｕを用いた場合には、高温下で熱圧着しても突起電極に酸化膜が形成されず、接合性が良好である。しかし、はんだのような卑金属よりなる封止枠は、熱圧着時に酸化されやすく、表面にできた酸化膜が接合の障害になり、封止不良を招く問題がある。同様に、封止枠と接合される電極も、酸化することではんだ濡れ性が低下し、封止不良の原因になる。
【０００５】
また、突起電極の接合と封止枠の接合とを同時に行うので、素子１個当たりの作業時間がかかり、生産性がよくない。例えば、Ａｕバンプを熱圧着する場合、その接合時間として２秒程度必要であり、はんだ封止のための加熱時間が約２０秒／個必要である。そのため、突起電極の接合と封止枠の接合とを同時に熱圧着していたのでは、素子１個当たり２０秒以上の接合時間を必要とし、生産性が低下してしまう。しかも、封止枠にかかる熱履歴が長くなり、長時間加熱されることで、封止枠の酸化が進行するとともに、電極のはんだ食われが発生して信頼性を低下させる可能性があった。
【０００６】
一方、複数の回路素子を大型の集合基板に対して一括して熱圧着することで、生産性を向上させる方法も提案されている。しかし、Ａｕバンプを使用した場合、接合に必要な荷重が１バンプ当たり約３Ｎ必要であり、３０バンプ以上の接合になると、約９０Ｎもの高荷重が必要になる。このような高荷重を加えながら、個々の回路素子を集合基板に対して精度よく位置決めし、かつ確実に接合することは非常に難しい。そのため、集合基板に一括熱圧着を行うにしても限度があり、精度と生産性を両立させるのは難しかった。
【０００７】
そこで、本発明の目的は、卑金属よりなる封止枠の酸化を抑制して封止不良をなくすことができる電子部品の製造方法を提供することにある。
他の目的は、精度を確保しながら生産性を向上させることが可能な電子部品の製造方法を提供することにある。
【０００８】
【課題を解決するための手段】
上記目的を達成するため、請求項１に係る発明は、回路素子に設けられた回路部と基板に設けられた電極のいずれか一方に金属突起電極を設け、回路素子の表面と基板の表面とのいずれか一方に、回路素子の回路部を取り囲む卑金属よりなる封止枠を設け、回路素子と基板とを対面させて回路部と基板の電極とを上記突起電極によって接合するとともに、回路素子と基板との間の空間を上記封止枠によって気密的に封止する電子部品の製造方法において、上記封止枠が酸化しない条件で、少なくとも上記突起電極を対向する回路素子の回路部または基板の電極に、超音波と圧力とを加えて仮接合する工程と、低酸素濃度雰囲気で、所定温度に加熱しながら加圧することにより、上記突起電極を対向する回路素子の回路部または基板の電極に本接合すると同時に、上記封止枠を対向する回路素子の表面または基板の表面に接合して封止する工程と、を有し、上記仮接合工程は、個々の回路素子に対して個別に実施し、上記本接合・封止工程は、複数の回路素子に対して同時に実施することを特徴とする電子部品の製造方法を提供する。
【０００９】
本発明では、仮接合工程を封止枠が酸化しない条件下で超音波加圧によって実施し、卑金属よりなる封止枠の表面に酸化膜が形成されるのを防止する。超音波加圧による振動で、突起電極と対向する接合電極の表面の酸化膜や汚染層が除去され、それぞれの新生面が接し合い、短時間で接合される。この状態では、突起電極と接合電極とは、完全な接合状態とする必要はなく、その後の本接合・封止工程までの間に剥離しない程度に接合してあればよい。次に、低酸素濃度雰囲気で熱圧着を行い、封止枠の酸化を防止しながら、封止枠の溶融，接合を行い、回路素子と基板との間の空間を気密的に封止する。熱を加えるので、大気中では封止枠が酸化してしまうからである。これと同時に、突起電極と回路素子の回路部または基板の電極とを完全に拡散接合（本接合）させる。
このように、封止枠の酸化を防止しながら封止を行うことができるので、封止性が向上する。なお、封止枠の酸化だけでなく、封止枠と接合される接合電極の酸化も防止できる。そのため、この接合電極を卑金属で形成することも可能である。
【００１０】
本発明では、突起電極による仮接合を行った後で、突起電極の本接合と封止枠による封止とを同時に行う。つまり、仮接合工程と本接合・封止工程とを分離している。仮接合とは、工程での振動やハンドリングで回路素子と基板とが外れない程度の強度で回路素子と基板とを仮止めするだけであるから、超音波の出力を小さくして超音波による位置ずれを小さくし、精度のよい位置決めを行うことができる。一方、本接合時には仮接合によって既に位置決めされているので、本接合時に新たに位置決めする必要がなく、簡単な装置で確実な接合が可能となる。また、仮接合は超音波加圧を用いているので、短時間で接合可能であるが、本接合・封止は熱圧着を用いているので、時間がかかる。本発明では仮接合と本接合・封止とを分離することで、それぞれの工程を最も効率のよい条件で実施することができる。
【００１１】
従来のように１回の熱圧着で接合と封止とを実施した場合には、接合後の回路素子を基板から剥離することができず、もし回路素子の不良を発見しても基板を再利用できない。これに対し、本発明では仮接合と本接合・封止とを分離しているので、仮接合の終了した部品（本接合前の部品）に対して、種々の追加作業を実施することが可能である。例えば、仮接合段階で回路素子の電気的特性の測定を行い、もし不良品である場合には、突起電極を対向する接合電極から剥離し、回路素子を基板から取り外すことで、基板を再利用することが可能である。
また、本発明では、仮接合工程を、個々の回路素子に対して個別に実施し、本接合・封止工程を、複数の回路素子に対して同時に実施している。
すなわち、精度を必要とする仮接合工程をワンバイワンで実施し、時間のかかる熱圧着工程をマルチ化することで、タクト時間を短縮でき、生産性の向上を実現できる。そして、本接合・封止工程は、仮接合工程によって予め位置決めされた素子と基板とに対して熱圧着を実施すればよいので、位置ずれが発生せず、高精度な電子部品を得ることができる。
【００１２】
請求項２のように、仮接合工程を常温で超音波と圧力とを加えて実施してもよい。
仮接合工程を常温で実施すれば、封止枠が自然酸化以上に酸化しないので、格別な酸化防止のための設備を必要とせず、仮接合が簡単になる。
また、回路素子が弾性表面波素子の場合、常温で仮接合を行なうことで、素子の焦電荷の発生をゼロにし、焦電破壊を防止できる。また、本接合時（熱圧着時）には基板が金属製の熱板上に設置されるので、焦電荷が突起電極、基板を通って熱板へ逃げることにより、焦電破壊を防止できる。
【００１３】
請求項３のように、仮接合工程を、低酸素濃度雰囲気で所定温度に加熱しながら超音波と圧力とを加えて実施してもよい。
超音波と圧力と熱とを加えて実施すると、より短時間で突起電極と対向する電極とを接合できるが、熱によって封止枠が酸化しやすくなる。そこで、低酸素濃度雰囲気で実施することで、封止枠の酸化を防止できる。
【００１５】
請求項４のように、基板として複数個分の大きさを有する集合基板を使用し、この集合基板に複数の回路素子を個別に仮接合した後、複数の回路素子を同時に集合基板に対して本接合・封止するのが望ましい。
この場合には、本発明の効果に加え、仮接合が終了した部品を一々整列させる必要がなく、集合基板に回路素子を仮接合したまま熱圧着工程へ移行させればよいので、作業効率が一層効率化される。なお、本接合・封止工程が終了した集合基板は、その後で１素子毎にカットする必要がある。
【００１６】
請求項５のように、突起電極をＡｕを主成分とする接合材で構成するのがよい。突起電極としてははんだバンプなどの卑金属材料で形成することも可能であるが、Ａｕバンプの場合、接合が容易であるし、酸化しないので接合部の電気抵抗を小さくできる利点がある。
【００１７】
請求項６のように、封止枠をはんだを主成分とする接合材で構成するのがよい。はんだの場合、比較的低温で溶融させることができるので、回路素子への熱的ダメージが少なくて済む。しかも、はんだ封止枠は、例えば印刷法によってはんだペーストを基板または回路素子に塗布し、はんだペーストをリフローソルダリングした後で洗浄し、フラックス残渣を取り除けば、簡単に形成できる。そのため、コストを低減できるとともに、フラックスレスで封止できる。
【００１８】
請求項７のように、突起電極の高さを封止枠より高く形成し、仮接合工程において突起電極のみを対向する回路素子の回路部または基板の電極に仮接合するのがよい。
突起電極のみを回路部または基板電極に仮接合すれば、超音波が封止枠に漏れることがなく、効率よく突起電極に集中し、短時間で仮接合できる。
なお、封止枠を突起電極と同一高さ、あるいは突起電極より高くすることも可能であるが、仮接合時に封止枠と回路素子または基板とが接触し、突起電極と接合電極との接合信頼性が低下する可能性がある。
【００１９】
請求項８のように、基板と回路素子に、それぞれ封止枠を介して接合される環状電極を設け、環状電極は共に直線部と角部とを有する略多角形の形状をなしており、少なくとも基板の環状電極の角部にアールを設けるのが望ましい。
従来技術では、基板の封止用環状電極に形成された環状のはんだ封止枠の高さが、その表面張力により、封止枠の角部（コーナ部）で高く、直線部で低くなっていた。その結果、
（１）仮接合時に封止枠が邪魔になり、バンプが電極に接したり、接しなかったりして仮接合が安定しない、
（２）バンプ寸法を大きくしてこれを回避しても、パッドサイズが大きくなり、素子寸法も大きくなってしまう、
（３）加熱・加圧してはんだ封止させる際、その高さの差のため、はんだ枠の高さが低い部位が接合されず、封止不良が発生する、
（４）封止時間が長くなり、生産コストが上昇する、といった課題があった。
そこで、請求項８のように基板の環状電極の角部にアールを設けると、その上に形成されるはんだ封止枠の直線部と角部の高さの差が小さくなり、上記（１）〜（４）の課題を解決できる。なお、回路素子の環状電極については、少なくとも封止枠と接合される面積があればよく、必ずしも角部にアールを必要としない。
【００２０】
請求項９のように、上記角部のアールのうち、内側アールの曲率半径が直線部の幅の１．５倍以上であり、かつアールの幅と直線部の幅とがほぼ等しいのがよい。
環状電極の角部にアールを設けた場合に、内側アールの曲率半径を直線部の幅の１．５倍以上とし、かつアールの幅と直線部の幅とをほぼ等しくすると、その上に形成されるはんだ封止枠の直線部の高さと角部の高さとがほぼ等しくなり、仮接合の安定性が向上する。また、はんだ封止枠の高さバラツキを小さくすることで、本接合時にはんだ封止枠と対向する環状電極とを確実に接触させることができ、封止不良を低減できる。また、封止時間を短縮でき、生産コストを下げることができる。
【００２１】
請求項１０のように、回路素子として、高周波素子または弾性表面波素子を用いるのがよい。
すなわち、封止枠の内部を中空構造とすることによって、ＧＨｚ帯で使用されるような高周波素子では、比誘電率を小さくして消費電力を低減できる効果があり、また弾性表面波素子のような振動を利用した素子の場合、振動がダンピングされず、良好な特性を得ることができる。
【００２２】
【発明の実施の形態】
図１〜図３は、本発明にかかる電子部品の第１の実施例を示す。
この電子部品は、パッケージ基板１に回路素子１０をフェースダウン実装したものである。
パッケージ基板１は、アルミナなどのセラミック基板、セラミックからなる誘電体基板、多層セラミック基板、ガラス基板、結晶性の基板、ガラスエポキシ樹脂などの気密性を有する基板よりなる。この基板１の表面には、複数の島状の接合電極２と、これら電極２を取り囲む環状電極３とが形成されている。上記接合電極２はスルーホールに導電材料を埋設した接続部４を介して裏面側に形成された表面実装のための外部電極５と接続されている。また、環状電極３は、図示しないアース側電極と接続されている。
【００２３】
上記環状電極３上には、図３に示すように、はんだ封止枠６が所定高さｈ1 （例えば２０〜４０μｍ）に形成されている。はんだ封止枠６は、例えば印刷法によってはんだペーストを基板１の環状電極３上に塗布し、はんだペーストをリフローソルダリングした後で洗浄し、フラックス残渣を取り除くことで、簡単に形成できる。なお、封止枠６の形成方法は、ＳＪ法などのプリコートや、メッキ、蒸着、スパッタなどの方法を用いてもよい。封止枠６の材料も溶融可能な金属であれば、はんだに限らない。
【００２４】
この実施例の回路素子１０は弾性表面波チップであり、水晶やＬｉＴａＯ3 、ＬｉＮｂＯ3 等からなる圧電基板１１の表面（図１では下面）に、Ａｌ等からなる２組のＩＤＴ電極１２とＴｉ／Ｎｉ／Ａｕ等からなる４個の入出力電極１３とを形成したものである。ＩＤＴ電極１２と入出力電極１３とは相互に接続されている。また、回路素子１０の表面には、ＩＤＴ電極１２と入出力電極１３とを取り囲む環状電極１４が形成されている。
【００２５】
図３に示すように、入出力電極１３のそれぞれには突起電極１５が固定されている。突起電極１５としては、Ａｕ，Ａｇ，Ｐｄ，Ｃｕを主成分とする金属バンプや、はんだバンプなどを用いることができる。突起電極１５は、めっき法、ワイヤボンディング法などを用いて形成されるが、ここではワイヤボンディング法によりＡｕバンプを形成した。突起電極１５の高さｈ2 は、例えば４０〜５０μｍであり、基板１に形成された半田封止枠６の高さより高く（望ましくは約１０μｍ以上高く）するのが望ましい。
【００２６】
上記基板１と回路素子１０とは、その縦横の寸法がほぼ同一に形成され、基板１の接合電極２と回路素子１０の入出力電極１３とが対応する位置に形成され、かつ基板１の環状電極３と回路素子１０の環状電極１４とが対応する位置に形成されている。
なお、回路素子１０の環状電極１４および基板１の環状電極３には、Ｎｉ／Ａｕメッキ電極を用いている。Ｎｉははんだ食われを防止するためであり、はんだ食われを防止できる金属であれば、Ｐｔ，Ｐｄ，Ｃｕ等でもよい。Ａｕは半田濡れ性を確保するためであり、Ａｇ，Ｓｎ，Ｐｔ，Ｃｕなどの濡れ性が確保できる金属であればよい。
【００２７】
ここで、上記基板１と回路素子１０との接合方法について、図４を参照して説明する。
まず図４の（ａ）のように、封止枠６を形成した基板１と、突起電極１５を形成した回路素子１０とを準備する。
次に、図４の（ｂ）のように、基板１をそのはんだ封止枠６を上側にむけて支持台Ａの上に載置し、位置決めする。一方、回路素子１０の裏面（ＩＤＴ電極１２を設けていない面）をボンディングツールＢで吸着し、基板１の接合電極２と回路素子１０の入出力電極１３とが上下に対応し、かつ基板１の環状電極３と回路素子１０の環状電極１４とが上下に対応するように位置決めし、突起電極１５を基板１の接合電極２に対して、ボンディングツールＢによって超音波と加圧とを付加して仮接合する。常温下で仮接合が実施されるので、はんだ封止枠６の酸化が進むことがない。仮接合条件は、突起電極１５と基板１の接合電極２とが仮接合された状態で、はんだ封止枠６と対向する回路素子１０の環状電極１４とが接触しない条件が望ましく、本実施例では、加圧荷重１．５Ｎ／バンプ、超音波出力０．５Ｗ、時間１．０ｓ、温度２５℃とした。超音波出力が比較的低いので、基板１と回路素子１０との位置精度が向上するとともに、パッド直下でのマイクロクラックの発生を防止できる。
次に、図４の（ｃ）のように、仮接合した基板１を加熱ステージＣ上にのせ、熱圧着ツールＤを回路素子１０の背面に押し当てて熱圧着し、本接合する。本実施例での熱圧着条件は、加圧荷重２．０Ｎ／バンプ、加熱温度２７０℃、加熱時間２０ｓとし、低酸素濃度下、例えば窒素雰囲気にして酸素濃度を１０ｐｐｍ以下としている。熱圧着によって、突起電極１５の高さが例えば２０〜２５μｍまで押し潰され、突起電極１５と基板１の接合電極２とを拡散接合させる。これと同時に、溶融した封止枠６が回路素子１０の環状電極１４に濡れ広がり、基板１と回路素子１０との間の空間が封止される。
最後に、基板１と回路素子１０とを冷却することで、接合と封止とが完了し、気密封止型の電子部品が得られる（図４の（ｄ）参照）
【００２８】
なお、図４の（ｃ）では、熱圧着をワンバイワンで実施する例を示したが、実際には数百個あるいはそれ以上の個数の電子部品に対して、同時に熱圧着を実施するのが望ましい。この場合、仮接合した複数の基板１（および回路素子１０）をトレーに整列させ、これを加熱ステージＣに載置して熱圧着を実施するのがよい。
加熱ステージＣは金属製の熱板よりなり、接地されている。そのため、熱圧着時に弾性表面波チップである回路素子１０から発生する焦電荷が突起電極１５、基板１を通って加熱ステージＣへ逃げることにより、回路素子１０の焦電破壊を防止できる。
上記実施例では、はんだを充分に濡れ拡がらせるために約２０秒間加熱・加圧したが、突起電極１５の接合ができ所望のバンプ高さになるのであれば、２０秒間も加圧する必要はなく、例えば０．５秒間の加熱・加圧と１９．５秒間の加熱でもよい。
【００２９】
上記のように常温で超音波・加圧により仮接合することと、低酸素濃度下で熱圧着することで、はんだ封止枠６の酸化を防止し、はんだ酸化膜による封止不良を少なくできる。また、熱圧着時に突起電極１５と接合電極２とを加熱・加圧することで、突起電極１５の固相接合を進め、接合を強固にしている。さらに、加圧によって突起電極１５の高さをコントロールすることで、封止枠６の潰し過ぎによるはんだのはみ出しや、バンプ１５へのショートを抑え、回路素子１０の環状電極１４が確実に溶融したはんだに当たり、接合して封止性を確保することができる。
【００３０】
表１は、仮封止時の温度と酸素濃度とを変化させた場合に、封止後の封止良品率を、封止枠６のはんだとしてＳｎＣｕを用いた場合と、ＳｎＡｇを用いた場合とで比較したものである。なお、突起電極としてＡｕバンプを使用した。
仮封止条件
雰囲気：Ｎ2 雰囲気，酸素濃度は１０ｐｐｍ〜大気
荷重：仮封止できるように１〜４Ｎの範囲で設定した。
超音波出力：０．５Ｗ
温度：常温〜１８０℃
本接合・封止条件
雰囲気：Ｎ2 雰囲気，酸素濃度は１０ｐｐｍ
接合温度：２８０℃
荷重：６Ｎ
検査方法
グロスリークテスト、ファインリークテストを併用。
【００３１】
【表１】

Figure 0003772740
表１から明らかなように、温度もしくは酸素濃度が高くなればなるほど、封止良品率が低下していることがわかる。これより、仮接合時に加熱すると、封止枠６の表面の酸化膜が自然酸化膜以上に厚く形成され、封止枠６の接合性（はんだの場合は濡れ性）を低下させて封止不良が発生してしまう。
したがって、温度を１００℃未満、望ましくは常温にするか、あるいは酸素濃度を１０００ｐｐｍ以下とすることで、封止枠６の酸化膜形成を抑制できる。
【００３２】
表２は、下記条件にて仮接合後、本接合・封止の際の酸素濃度を変化させた時の封止良品率を示す。なお、封止枠のはんだとしてＳｎＣｕを使用し、突起電極としてＡｕバンプを使用した。
仮封止条件
雰囲気：大気
荷重：４Ｎ
超音波出力：０．５Ｗ
温度：常温
本接合・封止条件
雰囲気：Ｎ2 雰囲気，酸素濃度は１０ｐｐｍ〜大気
接合温度：２８０℃
荷重：６Ｎ
検査方法
グロスリークテスト、ファインリークテストを併用。
【００３３】
【表２】
Figure 0003772740
表２から、酸素濃度が高くなればなるほど、封止良品率が低下していることがわかる。これより、封止枠６の酸化膜増大が封止不良の原因であると言える。熱圧着時の酸素濃度を５００ｐｐｍ以下とすることで、封止良品率を１００％とすることができた。
【００３４】
表３は本接合・封止の際の熱圧着時間と封止良品率との関係を示す。
【表３】
Figure 0003772740
表３から、封止を確実に行うには、熱圧着時間を５秒以上必要とすることがわかる。したがって、熱圧着工程をマルチ化することで、生産性を向上させることができる。
【００３５】
図５，図６は本発明にかかる電子部品の第２実施例を示す。
この例は、生産性を高めるため、パッケージ基板１として例えば数百個分の大きさを持つ集合基板１Ａを使用したものである。図では、説明を簡単にするため６個分の大きさの集合基板１Ａを示している。
集合基板１Ａの上面には、複数の島状の接合電極２と、これら接合電極２を取り囲む複数の環状電極３とが、縦横に配列されて形成されている。また、接合電極２はスルーホールに導電材料を埋設した接続部４を介して裏面側に形成された表面実装のための外部電極５と接続されている。上記環状電極３には第１実施例と同様の方法ではんだ封止枠６が形成される。
一方、回路素子１０は第１実施例と同様の素子であり、図１〜図３と同一部分には同一符号を付して重複説明を省略する。
【００３６】
次に、集合基板１Ａと回路素子１０との接合方法について、図７を参照して説明する。
図７の（ａ）のように、集合基板１Ａを、そのはんだ封止枠６を上側に向けて支持台Ａの上に位置決めする。一方、回路素子１０の裏面（ＩＤＴ電極１２を設けていない面）をボンディングツールＢで吸着し、支持台Ａの上方へ移動させる。そして、ボンディングツールＢによって超音波と加圧とを付加して突起電極１５を集合基板１Ａの接合電極２に対して位置決めして仮接合する。この仮接合を個々の回路素子１０に対してワンバイワンで実施し、集合基板１Ａの全ての部位に回路素子１０を仮接合する。なお、仮接合の条件は図４の（ｂ）と同様である。次に、図７の（ｂ）のように、仮接合した集合基板１Ａを加熱ステージＣ上にのせ、広面積の熱圧着ツールＤを仮接合した回路素子１０の背面に押し当てて熱圧着し、本接合する。本接合は、集合基板１Ａに仮接合された全ての回路素子１０に対して同時に実施する。つまり、マルチで実施する。熱圧着によって、突起電極１５と集合基板１Ａの接合電極２とが拡散接合すると同時に、溶融した封止枠６が回路素子１０の環状電極１４に濡れ広がり、集合基板１Ａと回路素子１０との間の空間が封止される。なお、本接合の条件は、図４の（ｃ）と同様である。最後に、図７の（ｃ）のように、本接合と封止とが終了した集合基板１Ａを破線ＣＬでダイシングすることにより、図１に示す気密封止型の電子部品が得られる。なお、ダイシングに代えて、集合基板１Ａに溝やミシン穴などを形成してブレイクしてもよいし、レーザーカット等の別の方法を用いてもよい。
【００３７】
上記のように、各接合電極２に対して回路素子１０の突起電極１５を超音波と加圧とを用いてワンバイワンで仮接合し、その後で熱圧着による本接合・封止をマルチで実施している。したがって、ｎ個の一括処理を行うことで、封止枠６の形成、熱圧着にかかる時間を１／ｎにできる。例えば、１個の素子の熱圧着に２０秒以上かかる場合であっても、２００個分の集合基板を使用すれば、１個当たりの熱圧着時間は０．１秒となり、生産性の大幅な向上を実現できる。
また、仮接合段階で１枚の集合基板１Ａに多数の回路素子１０が搭載されているので、本接合・封止に際して仮接合済みの電子部品をトレーなどに整列する必要もなく、整列時間を短縮できる。
【００３８】
図８は本発明にかかる他の製造方法を示す。
この製造方法は、仮接合の終了した部品（本接合前の部品）に対して、特性評価などの追加作業を実施し、不良品の場合には回路素子を取外して基板を再利用するものである。
まず回路素子に突起電極を形成し（ステップＳ１）、基板に封止枠を形成し（ステップＳ２）、この回路素子を基板に対して仮接合する（ステップＳ３）。次に、仮接合された回路素子の特性評価を行う（ステップＳ４）。特性評価によって良品であると評価された場合には、そのまま本接合・封止工程を実施する（ステップＳ５）。
特性評価において不良品であると評価された場合には、基板から回路素子を取り外し（ステップＳ６）、新たな回路素子をこの基板に仮接合し（ステップＳ３）、以後同様の工程を繰り返す。仮接合では、突起電極と基板の接合電極とが完全な接合状態ではないので、回路素子を基板から取り外した際、突起電極と接合電極とが容易に剥離し、接合電極に傷が残ることがない。また、仮接合段階では封止枠が対向する回路素子に接触していないので、封止枠が損傷することもない。したがって、基板を再利用することができる。
【００３９】
図９は本発明にかかる電子部品の第３実施例を示す。なお、第１実施例（図２，図３参照）と同一部分には同一符号を付して重複説明を省略する。
この電子部品の特徴は、パッケージ基板１に設けられた環状電極３および回路素子１０の表面に設けられた環状電極１４が、それぞれ直線部３ａ，１４ａと角部とを持つ略方形状をなしており、その角部にアール３ｂ，１４ｂ（但し、３ａ，３ｂは図示されていない）を設けた点にある。環状電極３のアール３ｂは、その上に形成されるはんだ封止枠６の直線部６ａと角部６ｂとの高さバラツキを小さくするためである。なお、回路素子１０の環状電極１４には必ずしもアール１４ｂを設ける必要はないが、基板１の環状電極３と同一形状とするのがよい。
【００４０】
図１０は基板１の環状電極３の一部の拡大図である。
環状電極３の直線部３ａの幅をｄ、角部３ｂのアールの幅をＤ、角部３ｂのアールのうち内側の曲率半径をＲｉとすると、Ｒｉを直線部３ａの幅ｄの１．５倍以上とし、かつアールの幅Ｄと直線部３ａの幅ｄとをほぼ等しく設定するのが望ましい。すなわち、
Ｒｉ≧１．５ｄ
ｄ≒Ｄ
ここでは、ｄ＝０．２ｍｍ、Ｄ＝０．２ｍｍ、Ｒｉ＝０．３ｍｍとした。
【００４１】
上記基板１と回路素子１０との接合封止方法は次の通りである。
まず、例えば突起電極１５としてＡｕバンプを使用し、窒素雰囲気中で、例えば５Ｎ／バンプの荷重で加熱＋超音波＋圧力を加え、Ａｕバンプ１５を例えば高さ５０μｍから３５〜４０μｍまで潰し、Ａｕバンプ１５と基板１の電極２とを仮接合させた。さらに、加熱＋圧力を加え、本接合した。このとき、封止枠６が回路素子１０の環状電極１４に接触して、例えば高さ３０μｍから２５μｍに潰され、基板１と回路素子１０との間の空間を封止した。
【００４２】
図１１は、環状電極３の角部３ｂの内側アールの曲率半径Ｒｉと、封止枠６の直線部６ａと角部（アール）６ｂとの高さの差との関係を表したものである。
図から明らかなように、曲率半径Ｒｉを大きくしていくと、封止枠６の直線部６ａと角部６ｂとの高さの差が次第に小さくなっていくことがわかる。
特に、曲率半径Ｒｉ（＝０．３ｍｍ）を直線部３ａの幅ｄ（＝０．２ｍｍ）の１．５倍とすることで、封止枠６の直線部６ａと角部６ｂとの高さの差を３μｍ以下とすることができた。その結果、封止枠６の頂面が平坦化され、仮接合時に封止枠が邪魔になり、バンプが電極に接したり、接しなかったりして仮接合が安定しないといった不具合を解消できた。
【００４３】
【表４】
Figure 0003772740
表４は、環状電極３の角部３ｂの内側アールの曲率半径Ｒｉと、本接合時の封止時間、封止良品率との関係を示したものである。
曲率半径Ｒｉを大きくすることで、封止枠６の高さバラツキを小さくでき、ひいては本接合時に封止枠６と環状電極１４とを全周で確実に接触させることが可能となり、封止不良を低減できた。また、封止時間も短縮できることから、生産性を向上させることができる。
【００４４】
本発明は上記実施例に限定されるものではない。
上記実施例では、封止枠を基板または集合基板に形成したが、回路素子側に形成してもよい。また、封止枠を回路素子または基板の一方にのみ形成したものに限らず、双方に設けてもよい。その場合には、封止枠同士が接合して封止する。
突起電極が封止枠より高く形成したものに限らず、両者が同一高さであってもよい。この場合には、仮接合工程の際に両者が超音波加圧によって仮接合される。封止枠は、全体が卑金属で構成されたものに限らず、少なくともその表面が卑金属で構成されたものであればよい。
封止枠は回路素子と基板との間を封止するだけでなく、例えば基板に形成されるアース側回路パターンと接続するようにしてもよい。したがって、基板に形成される環状電極をアース回路の一部として使用してもよい。
突起電極としてＡｕバンプを使用したが、例えばはんだバンプ、Ｃｕバンプ、Ａｌバンプなどの卑金属バンプを使用してもよい。この場合には、仮接合時に超音波による振動で、突起電極と接合電極の表面の酸化膜や汚染層が除去されるので、多少の自然酸化膜があっても接合することが可能である。
本発明の回路素子は弾性表面波素子に限るものではなく、一主面に回路面を持ち、他主面に回路面を持たない素子であれば、高周波デバイス、半導体チップなど他の回路素子であってもよいことは勿論である。
【００４５】
【発明の効果】
以上の説明で明らかなように、本発明によれば、仮接合工程を封止枠が酸化しない条件下で超音波加圧を行い、さらに低酸素濃度雰囲気で熱圧着を行うことで、封止枠の酸化を防止しながら突起電極の接合と封止枠の封止とを実施することができる。そのため、封止不良を解消できる。
また、突起電極による仮接合を行った後で、突起電極の本接合と封止枠による封止とを行うので、仮接合時には超音波の出力を小さくして超音波による位置ずれを小さくし、精度のよい位置決めを行うことができる。一方、本接合時には仮接合によって既に位置決めされているので、本接合時に新たに位置決めする必要がなく、簡単な装置で確実な接合が可能となる。そのため、本接合・封止をマルチ化することが容易になり、生産性の向上を実現できる。
さらに、本発明では、仮接合工程を、個々の回路素子に対して個別に実施し、本接合・封止工程を、複数の回路素子に対して同時に実施するので、精度を必要とする仮接合工程をワンバイワンで実施し、時間のかかる熱圧着工程をマルチ化することで、タクト時間を短縮でき、生産性の向上を実現できる。
【図面の簡単な説明】
【図１】本発明にかかる電子部品の第１実施例の断面図である。
【図２】図１に示す電子部品の突起電極および封止枠を形成する前の分解斜視図である。
【図３】図１に示す電子部品の突起電極および封止枠を形成した後の分解斜視図である。
【図４】図１に示す電子部品の製造工程図である。
【図５】本発明の第２実施例であって、突起電極および封止枠を形成する前の分解斜視図である。
【図６】図５に示す実施例の突起電極および封止枠を形成した後の分解斜視図である。
【図７】図５に示す実施例の製造工程図である。
【図８】本発明にかかる製造工程の他の実施例のフローチャート図である。
【図９】本発明にかかる電子部品の第２実施例の分解斜視図である。
【図１０】図９における基板の環状電極の部分拡大図である。
【図１１】環状電極の角部の内側アールの曲率半径Ｒｉと、封止枠の直線部と角部（アール）との高さの差との関係を表した図である。
【符号の説明】
１ 基板
２ 接合電極
３ 環状電極
６ 封止枠
１０ 回路素子
１２ ＩＤＴ電極（回路部）
１３ 入出力電極（回路部）
１４ 環状電極
１５ 突起電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an electronic component in which a circuit element is mounted on a substrate via a metal protruding electrode, and a circuit portion of the circuit element is hermetically sealed.
[0002]
[Prior art]
Conventionally, as a method of manufacturing electronic components such as surface acoustic wave elements (SAW elements) and high-frequency devices, a metal protrusion electrode is provided on one of a circuit portion provided on a circuit element and an electrode provided on a substrate. A sealing frame surrounding the circuit portion of the circuit element is provided on one of the surface of the substrate and the surface of the substrate, the circuit element and the substrate are faced to each other, and the circuit portion and the electrode of the substrate are joined by the metal protrusion electrode. An electronic component manufacturing method has been proposed in which a space between a circuit element and a substrate is hermetically sealed with a sealing frame (see, for example, Japanese Patent Application Laid-Open No. 2000-77970). For example, Au bumps are used as the protruding electrodes, and a base metal material such as solder is used as the sealing frame. The height of the protruding electrode is made higher than the height of the sealing frame.
[0003]
In order to mount the circuit element on the substrate, the back surface of the circuit element is first sucked by a thermocompression bonding tool, and the circuit portion of the circuit element is faced and bonded to the substrate positioned on the crimping stage. At this time, since the height of the protruding electrode is higher than the height of the sealing frame, when the thermocompression bonding tool is lowered, the protruding electrode first hits the electrode pad of the circuit element. By heating and pressurizing the thermocompression bonding tool in this state, the protruding electrode is crushed by heat and pressure, and the sealing frame contacts the annular electrode of the circuit element and melts. Then, the protruding electrode and the electrode pad of the element are diffusion-bonded by heat. Thus, in the conventional manufacturing method, bonding of the protruding electrodes and bonding of the sealing frame are performed simultaneously.
[0004]
[Problems to be solved by the invention]
When Au is used as the protruding electrode, an oxide film is not formed on the protruding electrode even when thermocompression bonding is performed at a high temperature, and the bonding property is good. However, a sealing frame made of a base metal such as solder is likely to be oxidized at the time of thermocompression bonding, and there is a problem that an oxide film formed on the surface becomes an obstacle to bonding and causes a sealing failure. Similarly, the electrodes joined to the sealing frame also oxidize, so that the solder wettability is lowered, which causes a sealing failure.
[0005]
In addition, since the bonding of the protruding electrodes and the bonding of the sealing frame are performed simultaneously, it takes a work time per element and the productivity is not good. For example, when thermocompression bonding of Au bumps is required, the bonding time is about 2 seconds, and the heating time for solder sealing is about 20 seconds / piece. For this reason, if the bonding of the protruding electrodes and the bonding of the sealing frame are performed by thermocompression at the same time, a bonding time of 20 seconds or more per element is required, and productivity is lowered. In addition, the heat history applied to the sealing frame becomes long, and the heating of the sealing frame progresses, so that the oxidation of the sealing frame progresses and the solder erosion of the electrode occurs, which may reduce the reliability. .
[0006]
On the other hand, a method for improving productivity by collectively thermocompression bonding a plurality of circuit elements to a large aggregate substrate has been proposed. However, when Au bumps are used, a load required for bonding requires about 3N per bump, and when bonding of 30 bumps or more, a load as high as about 90N is required. While applying such a high load, it is very difficult to position each circuit element with respect to the collective substrate with high accuracy and to reliably bond the circuit elements. Therefore, there is a limit even if batch thermocompression bonding is performed on the collective substrate, and it is difficult to achieve both accuracy and productivity.
[0007]
Accordingly, an object of the present invention is to provide a method for manufacturing an electronic component capable of eliminating sealing defects by suppressing oxidation of a sealing frame made of a base metal.
Another object is to provide an electronic component manufacturing method capable of improving productivity while ensuring accuracy.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is provided with a metal protrusion electrode on one of a circuit portion provided on a circuit element and an electrode provided on the substrate, and the surface of the circuit element, the surface of the substrate, A sealing frame made of a base metal surrounding the circuit portion of the circuit element is provided on either one of the circuit element, the circuit element and the substrate are opposed to each other, and the circuit portion and the electrode of the substrate are joined by the protruding electrode. In a method for manufacturing an electronic component in which a space between a substrate and a sealing frame is hermetically sealed, a circuit element or a substrate of a circuit element facing at least the protruding electrode is provided under the condition that the sealing frame is not oxidized. Applying ultrasonic waves and pressure to the electrodes and temporarily bonding them, and applying pressure while heating to a predetermined temperature in a low oxygen concentration atmosphere, the protruding electrodes are applied to the circuit portion of the circuit element or the electrode of the substrate facing each other. Book And at the same time if the step of sealing by bonding to the surface or surfaces of the substrate of the circuit element which faces the sealing frame,The temporary bonding step is performed individually for each circuit element, and the main bonding / sealing step is simultaneously performed for a plurality of circuit elements.Manufacturing method of electronic parts characterized by the aboveI will provide a.
[0009]
In this invention, a temporary joining process is implemented by ultrasonic pressurization on the conditions which a sealing frame does not oxidize, and prevents that an oxide film is formed on the surface of the sealing frame which consists of base metals. The oxide film and the contamination layer on the surface of the bonding electrode facing the protruding electrode are removed by vibration caused by ultrasonic pressure, and the new surfaces are brought into contact with each other and bonded in a short time. In this state, the protruding electrode and the bonding electrode do not need to be in a completely bonded state, and may be bonded to the extent that they do not peel off until the subsequent main bonding / sealing process. Next, thermocompression bonding is performed in a low oxygen concentration atmosphere, the sealing frame is melted and bonded while preventing the sealing frame from being oxidized, and the space between the circuit element and the substrate is hermetically sealed. This is because heat is applied and the sealing frame is oxidized in the atmosphere. At the same time, the protruding electrode and the circuit portion of the circuit element or the electrode of the substrate are completely diffusion bonded (main bonding).
Thus, since sealing can be performed while preventing oxidation of the sealing frame, sealing performance is improved. Note that not only the oxidation of the sealing frame but also the oxidation of the bonding electrode bonded to the sealing frame can be prevented. Therefore, it is possible to form this joining electrode with a base metal.
[0010]
In the present invention, after the temporary bonding by the protruding electrode, the main bonding of the protruding electrode and the sealing by the sealing frame are simultaneously performed. That is, the temporary bonding process and the main bonding / sealing process are separated. Temporary bonding means that the circuit element and the substrate are only temporarily fixed to such an extent that the circuit element and the substrate are not detached by vibration or handling in the process. The shift can be reduced and accurate positioning can be performed. On the other hand, since the positioning is already performed by the temporary bonding at the time of the main bonding, it is not necessary to perform a new positioning at the time of the main bonding, and the reliable bonding can be performed with a simple device. In addition, since the ultrasonic bonding is used for the temporary bonding, the bonding can be performed in a short time. However, since the main bonding / sealing uses the thermocompression bonding, it takes time. In the present invention, by separating the temporary bonding and the main bonding / sealing, the respective steps can be performed under the most efficient conditions.
[0011]
When bonding and sealing are performed by one thermocompression bonding as in the past, the circuit element after bonding cannot be peeled off from the substrate, and if the circuit element is found to be defective, the substrate must be re-mounted. Not available. On the other hand, since the present invention separates the temporary bonding and the main bonding / sealing, various additional operations can be performed on the parts for which the temporary bonding has been completed (the parts before the main bonding). It is. For example, the electrical characteristics of the circuit element are measured at the temporary bonding stage. If it is a defective product, the protruding electrode is peeled off from the opposing bonding electrode and the circuit element is removed from the substrate to reuse the substrate. Is possible.
In the present invention, the temporary bonding process is performed individually for each circuit element, and the main bonding / sealing process is performed simultaneously for a plurality of circuit elements.
That is, by performing the temporary joining process that requires accuracy on a one-by-one basis and making the time-consuming thermocompression bonding process multiple, the tact time can be shortened and the productivity can be improved. In the main joining / sealing process, it is only necessary to perform thermocompression bonding on the element and the substrate that have been positioned in advance in the temporary joining process, so that a positional deviation does not occur and a highly accurate electronic component can be obtained. it can.
[0012]
As in claim 2, the temporary joining step may be performed by applying ultrasonic waves and pressure at room temperature.
If the temporary bonding process is performed at room temperature, the sealing frame does not oxidize more than natural oxidation, so that special oxidation prevention equipment is not required and temporary bonding is simplified.
Further, when the circuit element is a surface acoustic wave element, by performing temporary bonding at room temperature, the generation of pyroelectric charges in the element can be reduced to zero and pyroelectric breakdown can be prevented. Further, since the substrate is placed on a metal hot plate at the time of main bonding (at the time of thermocompression bonding), pyroelectric breakdown can be prevented by escaping to the hot plate through the protruding electrodes and the substrate.
[0013]
As in claim 3, the temporary joining step may be performed by applying ultrasonic waves and pressure while heating to a predetermined temperature in a low oxygen concentration atmosphere.
When the ultrasonic wave, the pressure and the heat are applied, the electrode facing the protruding electrode can be joined in a shorter time, but the sealing frame is easily oxidized by the heat. Therefore, the oxidation of the sealing frame can be prevented by carrying out in a low oxygen concentration atmosphere.
[0015]
Claim 4In this way, a collective substrate having a plurality of sizes is used as a substrate, and a plurality of circuit elements are individually temporarily joined to the collective substrate, and then the plurality of circuit elements are simultaneously bonded to the collective substrate. It is desirable to seal.
In this case,Effects of the present inventionIn addition, it is not necessary to align the parts that have been temporarily joined, and it is only necessary to shift to the thermocompression bonding process with the circuit elements temporarily joined to the collective substrate, thereby further improving the work efficiency. In addition, it is necessary to cut the collective substrate after the main joining / sealing process for each element thereafter.
[0016]
Claim 5As described above, the protruding electrode is preferably made of a bonding material mainly composed of Au. The bump electrode can be formed of a base metal material such as a solder bump. However, the Au bump has an advantage that the bonding is easy and the electric resistance of the bonded portion can be reduced because it is not oxidized.
[0017]
Claim 6As described above, the sealing frame is preferably composed of a bonding material mainly composed of solder. In the case of solder, since it can be melted at a relatively low temperature, thermal damage to the circuit element can be reduced. Moreover, the solder sealing frame can be easily formed by, for example, applying a solder paste to a substrate or circuit element by a printing method, washing the solder paste after reflow soldering, and removing the flux residue. Therefore, cost can be reduced and sealing can be performed without flux.
[0018]
Claim 7As described above, it is preferable that the height of the protruding electrode be higher than that of the sealing frame, and in the temporary bonding step, only the protruding electrode is temporarily bonded to the circuit portion of the circuit element facing or the electrode of the substrate.
If only the protruding electrode is temporarily bonded to the circuit portion or the substrate electrode, the ultrasonic wave does not leak into the sealing frame, but is efficiently concentrated on the protruding electrode, and can be temporarily bonded in a short time.
The sealing frame can be the same height as the protruding electrode or higher than the protruding electrode. However, the sealing frame and the circuit element or the substrate are in contact with each other at the time of temporary bonding, and the protruding electrode and the bonding electrode are bonded. Reliability may be reduced.
[0019]
Claim 8In this way, the substrate and the circuit element are each provided with an annular electrode joined through a sealing frame, and both the annular electrodes have a substantially polygonal shape having straight portions and corner portions, and at least of the substrate It is desirable to provide rounds at the corners of the annular electrode.
In the prior art, the height of the annular solder sealing frame formed on the annular electrode for sealing the substrate is high at the corner (corner portion) of the sealing frame and low at the straight portion due to the surface tension. It was. as a result,
(1) The sealing frame becomes an obstacle at the time of temporary bonding, and the bump is in contact with the electrode or is not in contact, and the temporary bonding is not stable.
(2) Even if this is avoided by increasing the bump size, the pad size increases and the device size also increases.
(3) When soldering by heating and pressurizing, due to the difference in height, the part where the solder frame is low is not joined, and sealing failure occurs.
(4) There is a problem that the sealing time becomes long and the production cost increases.
Therefore,Claim 8If the corners of the annular electrode of the substrate are provided as in the above, the difference in height between the straight portion and the corner of the solder sealing frame formed thereon becomes small, and the above (1) to (4) The problem can be solved. In addition, about the annular electrode of a circuit element, what is necessary is just to have at least an area joined to the sealing frame, and the corners do not necessarily need a radius.
[0020]
Claim 9As described above, it is preferable that the radius of curvature of the inner radius is not less than 1.5 times the width of the straight portion, and the radius and the width of the straight portion are substantially equal.
When the radius is provided at the corner of the annular electrode, the radius of curvature of the inner radius is set to 1.5 times or more of the width of the straight portion, and the radius and the width of the straight portion are substantially equal to each other. The height of the straight portion and the corner portion of the solder sealing frame to be made are substantially equal, and the stability of temporary joining is improved. Further, by reducing the height variation of the solder sealing frame, the annular electrode facing the solder sealing frame can be reliably brought into contact during the main joining, and sealing failure can be reduced. Further, the sealing time can be shortened and the production cost can be reduced.
[0021]
Claim 10As described above, a high-frequency element or a surface acoustic wave element is preferably used as the circuit element.
That is, by making the inside of the sealing frame into a hollow structure, a high-frequency element such as that used in the GHz band has an effect of reducing the relative permittivity and reducing the power consumption, and like a surface acoustic wave element. In the case of an element using a simple vibration, the vibration is not damped and good characteristics can be obtained.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
1 to 3 show a first embodiment of an electronic component according to the present invention.
This electronic component is obtained by mounting a circuit element 10 face-down on a package substrate 1.
The package substrate 1 is made of an airtight substrate such as a ceramic substrate such as alumina, a dielectric substrate made of ceramic, a multilayer ceramic substrate, a glass substrate, a crystalline substrate, or a glass epoxy resin. A plurality of island-shaped joining electrodes 2 and an annular electrode 3 surrounding these electrodes 2 are formed on the surface of the substrate 1. The bonding electrode 2 is connected to an external electrode 5 for surface mounting formed on the back surface side via a connection portion 4 in which a conductive material is embedded in a through hole. The annular electrode 3 is connected to a ground side electrode (not shown).
[0023]
On the annular electrode 3, as shown in FIG. 3, a solder sealing frame 6 has a predetermined height h.1   (For example, 20 to 40 μm). The solder sealing frame 6 can be easily formed by applying a solder paste onto the annular electrode 3 of the substrate 1 by, for example, a printing method, washing the solder paste after reflow soldering, and removing the flux residue. The sealing frame 6 may be formed by a pre-coating method such as SJ method, plating, vapor deposition, sputtering, or the like. The material of the sealing frame 6 is not limited to solder as long as it can be melted.
[0024]
The circuit element 10 of this embodiment is a surface acoustic wave chip, which is a crystal or LiTaO.Three LiNbOThree Two sets of IDT electrodes 12 made of Al or the like and four input / output electrodes 13 made of Ti / Ni / Au or the like are formed on the surface (lower surface in FIG. 1) of the piezoelectric substrate 11 made of. The IDT electrode 12 and the input / output electrode 13 are connected to each other. An annular electrode 14 surrounding the IDT electrode 12 and the input / output electrode 13 is formed on the surface of the circuit element 10.
[0025]
As shown in FIG. 3, a protruding electrode 15 is fixed to each of the input / output electrodes 13. As the protruding electrode 15, a metal bump mainly composed of Au, Ag, Pd, or Cu, a solder bump, or the like can be used. The protruding electrode 15 is formed using a plating method, a wire bonding method, or the like. Here, Au bumps are formed by a wire bonding method. Height h of protruding electrode 152 Is, for example, 40 to 50 μm, and is preferably higher than the height of the solder sealing frame 6 formed on the substrate 1 (desirably higher by about 10 μm or more).
[0026]
The substrate 1 and the circuit element 10 are formed to have substantially the same vertical and horizontal dimensions, the bonding electrode 2 of the substrate 1 and the input / output electrode 13 of the circuit element 10 are formed at corresponding positions, and the annular shape of the substrate 1 is formed. The electrode 3 and the annular electrode 14 of the circuit element 10 are formed at corresponding positions.
Ni / Au plated electrodes are used for the annular electrode 14 of the circuit element 10 and the annular electrode 3 of the substrate 1. Ni is for preventing solder erosion, and Pt, Pd, Cu or the like may be used as long as the metal can prevent solder erosion. Au is for ensuring solder wettability, and any metal that can ensure wettability such as Ag, Sn, Pt, or Cu may be used.
[0027]
Here, a method of joining the substrate 1 and the circuit element 10 will be described with reference to FIG.
First, as shown in FIG. 4A, the substrate 1 on which the sealing frame 6 is formed and the circuit element 10 on which the protruding electrode 15 is formed are prepared.
Next, as shown in FIG. 4B, the substrate 1 is placed on the support base A with its solder sealing frame 6 facing upward and positioned. On the other hand, the back surface of the circuit element 10 (the surface on which the IDT electrode 12 is not provided) is adsorbed by the bonding tool B, the bonding electrode 2 of the substrate 1 and the input / output electrode 13 of the circuit element 10 correspond to each other vertically, and the substrate 1 The annular electrode 3 and the annular electrode 14 of the circuit element 10 are positioned so as to correspond to each other vertically, and the protruding electrode 15 is applied to the bonding electrode 2 of the substrate 1 with ultrasonic waves and pressure by the bonding tool B. And temporarily joined. Since temporary joining is performed at room temperature, the solder sealing frame 6 is not oxidized. The temporary bonding condition is preferably a condition in which the protruding electrode 15 and the bonding electrode 2 of the substrate 1 are temporarily bonded, and the annular electrode 14 of the circuit element 10 facing the solder sealing frame 6 is not in contact. Then, the pressure load was 1.5 N / bump, the ultrasonic output was 0.5 W, the time was 1.0 s, and the temperature was 25 ° C. Since the ultrasonic output is relatively low, the positional accuracy between the substrate 1 and the circuit element 10 can be improved, and the occurrence of microcracks directly under the pad can be prevented.
Next, as shown in FIG. 4C, the temporarily bonded substrate 1 is placed on the heating stage C, and the thermocompression bonding tool D is pressed against the back surface of the circuit element 10 to perform thermocompression bonding. The thermocompression bonding conditions in this example are a pressure load of 2.0 N / bump, a heating temperature of 270 ° C., a heating time of 20 s, and a low oxygen concentration, for example, a nitrogen atmosphere, and an oxygen concentration of 10 ppm or less. By the thermocompression bonding, the height of the protruding electrode 15 is crushed to 20 to 25 μm, for example, and the protruding electrode 15 and the bonding electrode 2 of the substrate 1 are diffusion bonded. At the same time, the melted sealing frame 6 spreads over the annular electrode 14 of the circuit element 10, and the space between the substrate 1 and the circuit element 10 is sealed.
Finally, the substrate 1 and the circuit element 10 are cooled to complete the joining and sealing, thereby obtaining a hermetically sealed electronic component (see FIG. 4D).
[0028]
Although FIG. 4C shows an example in which thermocompression bonding is performed one-by-one, it is actually preferable to perform thermocompression bonding simultaneously on hundreds or more electronic components. . In this case, it is preferable to align the plurality of temporarily bonded substrates 1 (and circuit elements 10) on a tray and place them on the heating stage C to perform thermocompression bonding.
The heating stage C is made of a metal hot plate and is grounded. Therefore, pyroelectric breakdown of the circuit element 10 can be prevented by the pyroelectric charge generated from the circuit element 10 which is a surface acoustic wave chip during thermocompression escaping through the protruding electrode 15 and the substrate 1 to the heating stage C.
In the above embodiment, the solder was heated and pressed for about 20 seconds to sufficiently spread the solder. However, if the bump electrode 15 can be joined and the desired bump height is obtained, it is necessary to press for 20 seconds. For example, heating / pressurization for 0.5 seconds and heating for 19.5 seconds may be used.
[0029]
As described above, temporary bonding by ultrasonic wave and pressure at room temperature and thermocompression bonding under a low oxygen concentration can prevent the solder sealing frame 6 from being oxidized and reduce the sealing failure due to the solder oxide film. . Further, by heating and pressurizing the protruding electrode 15 and the bonding electrode 2 at the time of thermocompression bonding, the solid-phase bonding of the protruding electrode 15 is advanced and the bonding is strengthened. Furthermore, by controlling the height of the protruding electrode 15 by pressurization, solder protrusion due to excessive crushing of the sealing frame 6 and short circuit to the bump 15 are suppressed, and the annular electrode 14 of the circuit element 10 is reliably melted. It hits the solder and can be joined to ensure sealing performance.
[0030]
Table 1 shows the ratio of non-defective products after sealing when SnCu is used as the solder of the sealing frame 6 and SnAg when the temperature and oxygen concentration during temporary sealing are changed. And compared. Note that Au bumps were used as the protruding electrodes.
Temporary sealing conditions
Atmosphere: N2 Atmosphere, oxygen concentration is 10ppm to the atmosphere
Load: It set in the range of 1-4N so that temporary sealing could be performed.
Ultrasonic output: 0.5W
Temperature: normal temperature to 180 ° C
Main joining and sealing conditions
Atmosphere: N2 Atmosphere and oxygen concentration is 10ppm
Joining temperature: 280 ° C
Load: 6N
Inspection method
Combined with gross leak test and fine leak test.
[0031]
[Table 1]
Figure 0003772740
As is apparent from Table 1, it can be seen that the higher the temperature or oxygen concentration, the lower the non-defective product rate. As a result, when heated at the time of temporary bonding, the oxide film on the surface of the sealing frame 6 is formed thicker than the natural oxide film, and the bonding property (wetting in the case of solder) of the sealing frame 6 is lowered, resulting in poor sealing. Will occur.
Therefore, the oxide film formation of the sealing frame 6 can be suppressed by setting the temperature to less than 100 ° C., desirably room temperature, or setting the oxygen concentration to 1000 ppm or less.
[0032]
Table 2 shows the non-defective product ratio when the oxygen concentration is changed during temporary bonding and sealing after temporary bonding under the following conditions. In addition, SnCu was used as the solder for the sealing frame, and Au bumps were used as the protruding electrodes.
Temporary sealing conditions
Atmosphere: Air
Load: 4N
Ultrasonic output: 0.5W
Temperature: normal temperature
Main joining and sealing conditions
Atmosphere: N2 Atmosphere, oxygen concentration is 10ppm to the atmosphere
Joining temperature: 280 ° C
Load: 6N
Inspection method
Combined with gross leak test and fine leak test.
[0033]
[Table 2]
Figure 0003772740
From Table 2, it can be seen that the higher the oxygen concentration, the lower the non-defective product rate. From this, it can be said that the increase in the oxide film of the sealing frame 6 is the cause of the sealing failure. By setting the oxygen concentration at the time of thermocompression bonding to 500 ppm or less, the sealing non-defective rate was able to be 100%.
[0034]
Table 3 shows the relationship between the thermocompression bonding time and the non-defective product rate during the main joining and sealing.
[Table 3]
Figure 0003772740
From Table 3, it can be seen that the thermocompression bonding time is required to be 5 seconds or more in order to reliably perform the sealing. Therefore, productivity can be improved by making the thermocompression bonding process multi-purpose.
[0035]
5 and 6 show a second embodiment of an electronic component according to the present invention.
In this example, a collective substrate 1A having a size of several hundred pieces, for example, is used as the package substrate 1 in order to increase productivity. In the figure, a collective substrate 1A having a size of six is shown for ease of explanation.
On the upper surface of the collective substrate 1A, a plurality of island-shaped joining electrodes 2 and a plurality of annular electrodes 3 surrounding the joining electrodes 2 are formed so as to be arranged vertically and horizontally. The bonding electrode 2 is connected to an external electrode 5 for surface mounting formed on the back surface side via a connection portion 4 in which a conductive material is embedded in the through hole. A solder sealing frame 6 is formed on the annular electrode 3 by the same method as in the first embodiment.
On the other hand, the circuit element 10 is the same element as in the first embodiment, and the same parts as those in FIGS.
[0036]
Next, a method for joining the collective substrate 1A and the circuit element 10 will be described with reference to FIG.
As shown in FIG. 7A, the collective substrate 1A is positioned on the support base A with the solder sealing frame 6 facing upward. On the other hand, the back surface (the surface on which the IDT electrode 12 is not provided) of the circuit element 10 is adsorbed by the bonding tool B and is moved above the support base A. Then, ultrasonic waves and pressure are applied by the bonding tool B, and the protruding electrodes 15 are positioned and temporarily bonded to the bonding electrodes 2 of the collective substrate 1A. This temporary bonding is performed on each circuit element 10 in a one-by-one manner, and the circuit elements 10 are temporarily bonded to all portions of the collective substrate 1A. The conditions for the temporary joining are the same as those in FIG. Next, as shown in FIG. 7B, the temporarily bonded collective substrate 1A is placed on the heating stage C, and a large-area thermocompression bonding tool D is pressed against the back surface of the temporarily bonded circuit element 10 for thermocompression bonding. This will be joined. The main bonding is performed simultaneously on all the circuit elements 10 temporarily bonded to the collective substrate 1A. In other words, it is implemented in multi. By the thermocompression bonding, the protruding electrode 15 and the joining electrode 2 of the collective substrate 1A are diffusion-bonded, and at the same time, the molten sealing frame 6 spreads and spreads on the annular electrode 14 of the circuit element 10, and between the collective substrate 1A and the circuit element 10 The space is sealed. The conditions for the main joining are the same as those in FIG. Finally, as shown in FIG. 7C, the hermetically sealed electronic component shown in FIG. 1 is obtained by dicing the assembled substrate 1A after the final bonding and sealing with a broken line CL. Instead of dicing, the aggregate substrate 1A may be broken by forming grooves or sewing holes, or another method such as laser cutting may be used.
[0037]
As described above, the protruding electrode 15 of the circuit element 10 is temporarily bonded to each bonding electrode 2 by one-by-one using ultrasonic waves and pressurization, and then the main bonding / sealing by thermocompression bonding is performed in multiple. ing. Therefore, by performing n batch processes, the time required for forming the sealing frame 6 and thermocompression bonding can be reduced to 1 / n. For example, even if it takes 20 seconds or more for thermocompression bonding of a single element, if 200 aggregate substrates are used, the thermocompression bonding time per unit is 0.1 seconds, which greatly improves productivity. Improvements can be realized.
In addition, since a large number of circuit elements 10 are mounted on one collective substrate 1A at the temporary bonding stage, it is not necessary to align the temporarily bonded electronic components on a tray or the like at the time of main bonding / sealing, and the alignment time can be reduced. Can be shortened.
[0038]
FIG. 8 shows another manufacturing method according to the present invention.
In this manufacturing method, additional work such as characteristic evaluation is performed on the parts that have been temporarily joined (the parts before the final joining), and in the case of defective products, circuit elements are removed and the board is reused. is there.
First, protruding electrodes are formed on the circuit element (step S1), a sealing frame is formed on the substrate (step S2), and the circuit element is temporarily bonded to the substrate (step S3). Next, the characteristics of the temporarily joined circuit elements are evaluated (step S4). When it is evaluated that the product is good by the characteristic evaluation, the main joining / sealing process is performed as it is (step S5).
When it is evaluated as a defective product in the characteristic evaluation, the circuit element is removed from the substrate (step S6), a new circuit element is temporarily joined to the substrate (step S3), and the same process is repeated thereafter. In the temporary bonding, the protruding electrode and the bonding electrode of the substrate are not in a completely bonded state. Therefore, when the circuit element is removed from the substrate, the protruding electrode and the bonding electrode may be easily peeled off and scratches may remain on the bonding electrode. Absent. Further, since the sealing frame is not in contact with the opposing circuit element in the temporary bonding stage, the sealing frame is not damaged. Therefore, the substrate can be reused.
[0039]
FIG. 9 shows a third embodiment of the electronic component according to the present invention. In addition, the same code | symbol is attached | subjected to the same part as 1st Example (refer FIG. 2, FIG. 3), and duplication description is abbreviate | omitted.
This electronic component is characterized in that the annular electrode 3 provided on the package substrate 1 and the annular electrode 14 provided on the surface of the circuit element 10 have a substantially rectangular shape having straight portions 3a and 14a and corner portions, respectively. The corners are provided with rounds 3b and 14b (however, 3a and 3b are not shown). The radius 3b of the annular electrode 3 is to reduce the height variation between the straight portion 6a and the corner portion 6b of the solder sealing frame 6 formed thereon. The circular electrode 14 of the circuit element 10 does not necessarily need to be provided with the radius 14b, but may have the same shape as the annular electrode 3 of the substrate 1.
[0040]
FIG. 10 is an enlarged view of a part of the annular electrode 3 of the substrate 1.
When the width of the straight portion 3a of the annular electrode 3 is d, the width of the corner 3b is D, and the inner radius of curvature of the corner 3b is Ri, Ri is 1.5 of the width d of the straight portion 3a. It is desirable that the radius D and the width d of the linear portion 3a are set to be approximately equal. That is,
Ri ≧ 1.5d
d ≒ D
Here, d = 0.2 mm, D = 0.2 mm, and Ri = 0.3 mm.
[0041]
A method for bonding and sealing the substrate 1 and the circuit element 10 is as follows.
First, for example, an Au bump is used as the protruding electrode 15, and heating + ultrasonic wave + pressure is applied in a nitrogen atmosphere, for example, with a load of 5 N / bump, and the Au bump 15 is crushed from, for example, a height of 50 μm to 35 to 40 μm. The bump 15 and the electrode 2 of the substrate 1 were temporarily joined. Further, heating and pressure were applied to perform the main joining. At this time, the sealing frame 6 was in contact with the annular electrode 14 of the circuit element 10 and crushed to a height of 30 μm to 25 μm, for example, to seal the space between the substrate 1 and the circuit element 10.
[0042]
FIG. 11 shows the relationship between the radius of curvature Ri of the inner radius of the corner 3 b of the annular electrode 3 and the difference in height between the straight portion 6 a and the corner (r) 6 b of the sealing frame 6. .
As can be seen from the figure, as the radius of curvature Ri is increased, the difference in height between the straight portion 6a and the corner portion 6b of the sealing frame 6 gradually decreases.
In particular, by setting the curvature radius Ri (= 0.3 mm) to 1.5 times the width d (= 0.2 mm) of the straight portion 3a, the height of the straight portion 6a and the corner portion 6b of the sealing frame 6 is increased. Difference of 3 μm or less. As a result, the top surface of the sealing frame 6 is flattened, and the sealing frame becomes an obstacle at the time of temporary bonding, and the problem that the temporary bonding is not stable due to bumps contacting or not contacting the electrodes can be solved.
[0043]
[Table 4]
Figure 0003772740
Table 4 shows the relationship between the curvature radius Ri of the inner radius of the corner 3b of the annular electrode 3, the sealing time at the time of the main joining, and the sealing good product rate.
By increasing the curvature radius Ri, the height variation of the sealing frame 6 can be reduced, and as a result, the sealing frame 6 and the annular electrode 14 can be reliably brought into contact with the entire circumference at the time of main joining, resulting in poor sealing. Was able to be reduced. Further, since the sealing time can be shortened, productivity can be improved.
[0044]
The present invention is not limited to the above embodiments.
In the above embodiment, the sealing frame is formed on the substrate or the collective substrate, but it may be formed on the circuit element side. Further, the sealing frame is not limited to being formed only on one of the circuit element or the substrate, and may be provided on both. In that case, the sealing frames are joined and sealed.
The protruding electrodes are not limited to be formed higher than the sealing frame, and both may be the same height. In this case, both are temporarily joined by ultrasonic pressure during the temporary joining step. The sealing frame is not limited to one that is entirely made of a base metal, but may be any one that at least the surface thereof is made of a base metal.
The sealing frame may not only seal between the circuit element and the substrate, but may be connected to, for example, a ground circuit pattern formed on the substrate. Therefore, the annular electrode formed on the substrate may be used as a part of the earth circuit.
Although Au bumps are used as the protruding electrodes, for example, base metal bumps such as solder bumps, Cu bumps, and Al bumps may be used. In this case, since the oxide film and the contamination layer on the surface of the bump electrode and the bonding electrode are removed by vibration by ultrasonic waves at the time of temporary bonding, bonding can be performed even if there is some natural oxide film.
The circuit element of the present invention is not limited to a surface acoustic wave element, and any other circuit element such as a high-frequency device or a semiconductor chip may be used as long as the element has a circuit surface on one main surface and no circuit surface on the other main surface. Of course there may be.
[0045]
【The invention's effect】
As is clear from the above explanation,The present inventionAccording to the present invention, ultrasonic bonding is performed under the condition that the sealing frame does not oxidize in the temporary bonding step, and further, thermocompression bonding is performed in a low oxygen concentration atmosphere, thereby preventing the sealing frame from being oxidized. And sealing of the sealing frame can be performed. Therefore, sealing failure can be eliminated.
In addition, after performing temporary bonding with the protruding electrode, the main bonding of the protruding electrode and sealing with the sealing frame are performed, so that during the temporary bonding, the output of the ultrasonic wave is reduced to reduce the displacement due to the ultrasonic wave, Accurate positioning can be performed. On the other hand, since the positioning is already performed by the temporary bonding at the time of the main bonding, it is not necessary to perform a new positioning at the time of the main bonding, and the reliable bonding can be performed with a simple device. For this reason, it becomes easy to multiplex the main joining / sealing, and the productivity can be improved.
Furthermore, in the present invention, the temporary bonding process is performed individually for each circuit element, and the main bonding / sealing process is performed simultaneously for a plurality of circuit elements. By implementing the process on a one-by-one basis and making the time-consuming thermocompression bonding process multiple, the tact time can be shortened and the productivity can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a first embodiment of an electronic component according to the present invention.
FIG. 2 is an exploded perspective view before forming bump electrodes and a sealing frame of the electronic component shown in FIG.
3 is an exploded perspective view after forming protruding electrodes and a sealing frame of the electronic component shown in FIG. 1; FIG.
4 is a manufacturing process diagram of the electronic component shown in FIG. 1. FIG.
FIG. 5 is an exploded perspective view of a second embodiment of the present invention before forming protruding electrodes and a sealing frame.
6 is an exploded perspective view after forming the bump electrodes and the sealing frame of the embodiment shown in FIG. 5. FIG.
7 is a manufacturing process diagram of the embodiment shown in FIG. 5; FIG.
FIG. 8 is a flowchart of another embodiment of the manufacturing process according to the present invention.
FIG. 9 is an exploded perspective view of a second embodiment of the electronic component according to the present invention.
10 is a partially enlarged view of the annular electrode of the substrate in FIG. 9. FIG.
FIG. 11 is a diagram showing the relationship between the curvature radius Ri of the inner radius of the corner portion of the annular electrode and the height difference between the straight portion and the corner portion (R) of the sealing frame.
[Explanation of symbols]
1 Substrate
2 Junction electrodes
3 ring electrode
6 Sealing frame
10 Circuit elements
12 IDT electrode (circuit part)
13 Input / output electrodes (circuit part)
14 ring electrode
15 Projection electrode

Claims (10)

回路素子に設けられた回路部と基板に設けられた電極のいずれか一方に金属突起電極を設け、回路素子の表面と基板の表面との少なくとも一方に、回路素子の回路部を取り囲む卑金属よりなる封止枠を設け、回路素子と基板とを対面させて回路部と基板の電極とを上記突起電極によって接合するとともに、回路素子と基板との間の空間を上記封止枠によって気密的に封止する電子部品の製造方法において、
上記封止枠が酸化しない条件で、少なくとも上記突起電極を対向する回路素子の回路部または基板の電極に、超音波と圧力とを加えて仮接合する工程と、
低酸素濃度雰囲気で、所定温度に加熱しながら加圧することにより、上記突起電極を対向する回路素子の回路部または基板の電極に本接合すると同時に、上記封止枠によって回路素子と基板との間を封止する工程と、を有し、
上記仮接合工程は、個々の回路素子に対して個別に実施し、
上記本接合・封止工程は、複数の回路素子に対して同時に実施することを特徴とする電子部品の製造方法。A metal protrusion electrode is provided on one of the circuit portion provided on the circuit element and the electrode provided on the substrate, and at least one of the surface of the circuit element and the surface of the substrate is made of a base metal surrounding the circuit portion of the circuit element. A sealing frame is provided so that the circuit element and the substrate face each other and the circuit portion and the electrode of the substrate are joined by the protruding electrode, and the space between the circuit element and the substrate is hermetically sealed by the sealing frame. In the manufacturing method of electronic parts to be stopped,
Under the condition that the sealing frame does not oxidize, at least the protruding electrode is temporarily bonded to the circuit part of the circuit element or the electrode of the substrate by applying ultrasonic waves and pressure; and
By applying pressure while heating to a predetermined temperature in a low oxygen concentration atmosphere, the protruding electrode is finally bonded to the circuit portion of the circuit element or the electrode of the substrate, and at the same time, between the circuit element and the substrate by the sealing frame. includes a step of sealing, the a,
The temporary bonding step is performed individually for each circuit element,
The said joining and sealing process is implemented simultaneously with respect to a some circuit element, The manufacturing method of the electronic component characterized by the above-mentioned . 上記仮接合工程は、常温で超音波と圧力とを加えることを特徴とする請求項１に記載の電子部品の製造方法。The method of manufacturing an electronic component according to claim 1, wherein the temporary bonding step applies ultrasonic waves and pressure at room temperature. 上記仮接合工程は、低酸素濃度雰囲気で所定温度に加熱しながら超音波と圧力とを加えることを特徴とする請求項１に記載の電子部品の製造方法。2. The method of manufacturing an electronic component according to claim 1, wherein in the temporary bonding step, ultrasonic waves and pressure are applied while heating to a predetermined temperature in a low oxygen concentration atmosphere. 上記基板は複数個分の大きさを有する集合基板であり、
この集合基板に複数の回路素子を個別に仮接合した後、複数の回路素子を同時に上記集合基板に対して本接合・封止することを特徴とする請求項１ないし３のいずれかに記載の電子部品の製造方法。The substrate is a collective substrate having a plurality of sizes.
After individually provisionally joining a plurality of circuit elements on the aggregate substrate, according to any one of claims 1 to 3, characterized in that the bonding and sealing a plurality of circuit elements simultaneously to the assembly substrate Manufacturing method of electronic components. 上記突起電極はＡｕを主成分とする接合材からなることを特徴とする請求項１ないし４のいずれかに記載の電子部品の製造方法。The protruding electrode manufacturing method of electronic component according to any one of claims 1 to 4, characterized in that it consists of joining material mainly composed of Au. 上記封止枠ははんだを主成分とする接合材からなることを特徴とする請求項１ないし５のいずれかに記載の電子部品の製造方法。It said sealing frame method for manufacturing the electronic component according to any one of claims 1 to 5, characterized in that it consists of joining material mainly composed of solder. 上記突起電極の高さは上記封止枠より高く形成され、上記仮接合工程において突起電極のみを対向する回路素子の回路部または基板の電極に仮接合することを特徴とする請求項１ないし６のいずれかに記載の電子部品の製造方法。The height of the protruding electrode is formed to be higher than the sealing frame, claims 1, characterized in that temporarily joined to the circuit part or the substrate of the electrode of the circuit element which faces only projecting electrodes in the temporary bonding step 6 The manufacturing method of the electronic component in any one of. 上記基板と回路素子には、それぞれ上記封止枠を介して接合される環状電極が設けられ、
上記環状電極は共に直線部と角部とを有する略多角形の形状をなしており、
少なくとも基板の環状電極の角部にアールが設けられていることを特徴とする請求項１ないし７のいずれかに記載の電子部品の製造方法。The substrate and the circuit element are each provided with an annular electrode joined via the sealing frame,
Both of the annular electrodes have a substantially polygonal shape having straight portions and corner portions,
Method of manufacturing an electronic component according to any of claims 1 to 7, characterized in that the radius is provided at the corners of at least the substrate of the annular electrode. 上記角部のアールのうち、内側アールの曲率半径が上記直線部の幅の１．５倍以上であり、かつ上記アールの幅と上記直線部の幅とがほぼ等しいことを特徴とする請求項８に記載の電子部品の製造方法。Of Earl of the corner, the claims of curvature of the inner radius radius is at least 1.5 times the width of the linear portion, and the width of the width and the linear portion of the radius is equal to or approximately equal 9. A method for producing an electronic component according to 8 . 上記回路素子は、高周波素子または弾性表面波素子であることを特徴とする請求項１ないし９のいずれかに記載の電子部品の製造方法。The circuit element, method for manufacturing the electronic component according to any one of claims 1 to 9, characterized in that a high frequency device or a surface acoustic wave device.
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