JP2017055338A - Semiconductor device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption; and provide an integrated semiconductor device; and provide a highly reliable semiconductor device.SOLUTION: A semiconductor device has a sample hold circuit and a first circuit. The first circuit has an amplifier; and the sample hold circuit has a buffer circuit, a first transistor with a channel length not less than 1 nm and not more than 500 nm, a second transistor, a first capacitive element and a second capacitive element. One of a source and a drain of the first transistor is electrically connected with one electrode of the first capacitive element, one electrode of the second capacitive element and one of a source and a drain of the second transistor. The first transistor has a function of retaining charge in one of the source and the drain of the first transistor by being turned off. The buffer circuit has a function of being subjected to stoppage of power voltage supply after retaining charge.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and an electronic device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a memory device, a driving method thereof, or a driving method thereof. A manufacturing method can be mentioned as an example.

  Note that in this specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like that can function by utilizing semiconductor characteristics. As an example, a semiconductor device such as a transistor or a diode is a semiconductor device. As another example, the circuit including a semiconductor element is a semiconductor device. As another example, a device including a circuit including a semiconductor element is a semiconductor device.

  An analog-digital conversion circuit (hereinafter referred to as an AD converter), which is a kind of semiconductor device that uses semiconductor characteristics, is mounted on various devices. Patent Document 1 discloses a configuration of an AD converter that reduces power consumption.

US Patent Application Publication No. 2012/0112937

  Generally, the AD converter is always supplied with power, and continues to output digital data while analog data is being input. That is, power is continuously consumed while power is supplied.

  In order to reduce power consumption, there are means such as lowering the driving voltage, lowering the driving frequency, or providing a period for stopping the supply of power. However, lowering the driving voltage and frequency is directly related to the resolution of the AD converter and the sampling rate, leading to performance degradation. In addition, intermittent power supply can be stopped by using a flash memory for holding analog data, but a dedicated high-voltage generation circuit and peripheral circuits are required. Will increase.

  An object of one embodiment of the present invention is to provide a novel semiconductor device, a novel electronic device, or the like.

  Another object of one embodiment of the present invention is to provide a semiconductor device or the like with a novel structure that can reduce power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that does not deteriorate the performance of an AD converter, such as resolution and sampling rate. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that does not require a dedicated high-voltage generation circuit or peripheral circuit for holding analog data. To do.

  Another object of one embodiment of the present invention is to provide an integrated semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device.

  Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not disturb the existence of other problems. Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above-described description and / or other problems.

One embodiment of the present invention includes a sample and hold circuit and a first circuit. The first circuit includes an amplifier. The sample and hold circuit includes a buffer circuit, a first transistor, and a second circuit. The first transistor has a channel length of 1 nm to 500 nm, the first transistor includes an oxide semiconductor, The gate capacitance of the first transistor is 0.1 μF · cm ⁻² or more and 1 μF · cm ⁻² or less, and the capacitance of the second capacitor is 0.3 times or more of the gate capacitance of the first transistor. 7 times or less, one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor, and one of the source and the drain of the first transistor is a second capacitor One side of the element One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, and the first transistor is turned off to turn on the first transistor A semiconductor having a function of holding charge in one of a source and a drain of a transistor, and a buffer circuit having a function of stopping supply of a power supply voltage after holding the charge in one of a source and a drain of the first transistor Device.

Alternatively, one embodiment of the present invention includes a sample-hold circuit and a first circuit, the first circuit includes a comparator, the sample-hold circuit includes a buffer circuit, a first transistor, The first transistor includes a second transistor, a first capacitor, and a second capacitor, the channel length of the first transistor is greater than or equal to 1 nm and less than or equal to 500 nm, and the first transistor includes an oxide semiconductor. The first transistor has a gate capacitance of 0.1 μF · cm ^{−2 to} 1 μF · cm ⁻² , and the second capacitor has a capacitance of 0.3 times or more the gate capacitance of the first transistor. 0.7 or less, one of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor, and the one of the source and the drain of the first transistor is of One of the electrodes of the quantum element is electrically connected, one of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor, and the first transistor is turned off Thus, the buffer circuit has a function of holding electric charge in one of the source and the drain of the first transistor, and the buffer circuit stops supplying the power supply voltage after holding the electric charge in one of the source and the drain of the first transistor. This is a semiconductor device having a function.

  In the above structure, the first circuit preferably includes a third transistor, and one of the source and the drain of the first transistor is preferably electrically connected to the gate of the third transistor. In the above structure, the output from the buffer circuit is input to the other of the source and the drain of the first transistor, and the signal corresponding to the charge held in one of the source and the drain of the first transistor is the first It is preferable to be input to the circuit. In the above structure, the semiconductor device preferably includes a digital-analog conversion circuit, and the digital-analog conversion circuit is preferably connected to the first circuit. In the above structure, the semiconductor device preferably includes a successive approximation register and a timing controller.

  Another embodiment of the present invention includes a buffer circuit, a first transistor, a second transistor, and a capacitor, and the channel length of the first transistor is greater than or equal to 1 nm and less than or equal to 500 nm. The transistor includes an oxide semiconductor, one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor, and one of the source and the drain of the first transistor is The first transistor is electrically connected to one of the source and the drain of the first transistor, the first potential is applied to the other of the source and the drain of the second transistor, and the second transistor is turned on to turn on the source of the first transistor. Alternatively, the first charge corresponding to the first potential is applied to one of the drains, and then turned off to hold the first charge. A second potential is applied to the other of the source and the drain of the first transistor. When the first transistor is turned on, the second potential corresponding to the second potential is applied to one of the source or the drain of the first transistor. The semiconductor device has a function of holding the second charge by turning off after applying the charge, and the buffer circuit has a function of stopping the supply of the power supply voltage after holding the second charge. is there.

  Another embodiment of the present invention includes a buffer circuit, a first transistor, a second transistor, a capacitor, and a second capacitor, and the channel length of the first transistor is 1 nm or more. The first transistor includes an oxide semiconductor, the capacitance of the second capacitor is 0.3 to 0.7 times the gate capacitance of the first transistor, and the first transistor One of the source and the drain of the transistor is electrically connected to one electrode of the capacitor, and the one of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor One of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor, and the other of the source and the drain of the second transistor A first potential is applied, and the second transistor is turned on to apply a first charge corresponding to the first potential to one of a source or a drain of the first transistor, and then is turned off. The first transistor has a function of holding the first charge, and the second potential is applied to the other of the source and the drain of the first transistor, and the third potential is applied to the gate of the first transistor. , The fourth potential is applied to the other electrode of the second capacitor, the second charge corresponding to the second potential is applied to one of the source and the drain of the first transistor, The transistor 1 has a function of holding the second charge by being turned off, and the buffer circuit is a semiconductor device having a function of stopping the supply of the power supply voltage after holding the second charge. .

In the above structure, the difference between the first potential and the second potential is preferably greater than 0.1 V and less than 4 V. In the above structure, the potential difference of the third potential with respect to the second potential is preferably different in polarity from the potential difference of the fourth potential with respect to the second potential. In the above structure, the gate capacitance of the first transistor is preferably 0.1 μF · cm ^{−2 to} 1 μF · cm ⁻² . In the above structure, the output from the buffer circuit is input to the other of the source and the drain of the first transistor, and the signal corresponding to the charge held in one of the source and the drain of the first transistor is the first It is preferable to be input to the circuit. In the above structure, the semiconductor device preferably includes a digital-analog conversion circuit. In the above structure, the semiconductor device preferably includes a successive approximation register and a timing controller.

  Another embodiment of the present invention is an electronic device including any of the above semiconductor devices and a display portion.

  Note that other aspects of the present invention are described in the following embodiments and drawings.

  One embodiment of the present invention can provide a novel semiconductor device, a novel electronic device, or the like.

  Alternatively, according to one embodiment of the present invention, a semiconductor device or the like having a novel structure that can reduce power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like having a novel structure that does not deteriorate the performance of an AD converter, such as resolution and sampling rate, can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like having a novel structure which does not require a dedicated high-voltage generation circuit or a peripheral circuit for holding analog data can be provided.

  According to one embodiment of the present invention, an integrated semiconductor device can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided.

  Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the above effects and / or other effects. Therefore, one embodiment of the present invention may not have the above-described effects depending on circumstances.

FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. 4 is a timing chart for describing one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. 4A and 4B are a block diagram and a waveform diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 6 is a waveform diagram for describing one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. 4 is a timing chart for describing one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 6 is a schematic diagram for illustrating one embodiment of the present invention. FIG. 6 is a schematic diagram for illustrating one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating one embodiment of the present invention. An electronic device for describing one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. 4 is a timing chart for describing one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. 4 is a timing chart for describing one embodiment of the present invention. FIG. 6 is a schematic diagram for illustrating one embodiment of the present invention. FIG. 6 is a schematic diagram for illustrating one embodiment of the present invention. FIG. 6 is a schematic diagram for illustrating one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating a structural example of a transistor. 10A and 10B are a cross-sectional view and an energy band diagram illustrating a structural example of a transistor. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. FIG. 10 is a cross-sectional view illustrating a structural example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating a structural example of a transistor. FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device. FIG. 6 is an external view illustrating a configuration example of a display device. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation.

  Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  In the present specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It is also possible. In addition, for example, a component referred to as “first” in one embodiment of the present specification may be omitted in another embodiment or in the claims.

  Note that in the drawings, the same element, an element having a similar function, an element of the same material, an element formed at the same time, or the like may be denoted by the same reference numeral, and repeated description thereof may be omitted.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention is described.

  FIG. 1 is a block diagram illustrating a structure of a semiconductor device of one embodiment of the present invention.

  The semiconductor device 100 preferably includes a sample and hold circuit 101 (also referred to as a sample and hold circuit; abbreviated as S & H in the drawing) and a circuit 102.

  The sample-and-hold circuit 101 is a circuit having a function of receiving analog data potential (analog potential Vin) and holding charges according to the analog potential Vin in accordance with control of the control signal S1.

  As an example, the sample hold circuit 101 includes a buffer circuit 111, a transistor 112, and a capacitor 113. The output terminal of the sample hold circuit 101 is provided on one of the source and the drain of the transistor 112. An input terminal of the sample hold circuit 101 is provided on the other of the source and the drain of the transistor 112. Note that a node at one of the source and the drain of the transistor 112 is referred to as a node ND for description.

  FIGS. 1B and 1C show an example in which a sensor circuit 121 (Sensor in the drawing) that generates an analog potential Vin is connected to an input terminal Vin as a more specific example of the semiconductor device 100. A circuit other than the sensor circuit may be connected to the input terminal Vin.

  As shown in FIG. 1B, the sample and hold circuit 101 preferably includes a transistor 117. When the sample hold circuit 101 includes the transistor 117, for example, the potential difference applied between the source and the drain of the transistor 112 can be reduced. In addition, as illustrated in FIG. 1C, the sample and hold circuit 101 preferably includes a capacitor 116. When the sample and hold circuit 101 includes the capacitor 116, for example, fluctuations and distortions in the output potential from the sample and hold circuit 101 can be reduced.

  One of a source and a drain of the transistor 112 is electrically connected to one electrode of the capacitor 113. One of the source and the drain of the transistor 112 is electrically connected to one of the source and the drain of the transistor 117.

The buffer circuit 111 has a function of amplifying and outputting a signal such as analog data input to the sample and hold circuit 101. Here, in the example shown in FIGS. 1B and 1C, the potential VDD is input to the buffer circuit 111 via the switch SW. The switch SW is controlled by a control signal _PSW . Here, the potential VDD may be used as a power source of a circuit included in the semiconductor device 100 in some cases. For example, the potential VDD is used as a power source for the buffer circuit 111.

The transistor 112 is a transistor having a function of extremely low current flowing between a source and a drain in an off state. As the transistor having such a function, a transistor having an oxide semiconductor in a channel formation region (OS transistor) is preferable. The OS transistor will be described in detail in an embodiment described later. In the drawing, in order to clearly indicate that the transistor is an OS transistor, “OS” is added to the circuit symbol of the OS transistor. One of the source and the drain of the transistor 112 is connected to the input terminal of the sample and hold circuit 101. The gate of the transistor 112 is connected to a wiring that supplies a control signal S1. One of the source and the drain of the transistor 112 is connected to the output terminal of the sample hold circuit 101 or the node ND. Here, the potential of the node ND is V _ND .

  The capacitor 113 has a function of holding charge corresponding to the analog potential Vin by turning off the transistor 112. Note that FIG. 1 illustrates a structure in which the capacitor 113 is provided on one of the source and the drain of the transistor 112, that is, the node ND side; however, the capacitor 113 is not necessarily provided, and the gate capacitance or the like at the input terminal of the circuit 102. It can be omitted by using. Note that a circuit including a transistor 112 and a capacitor 113 that holds electric charge in accordance with the analog potential Vin is illustrated as a first circuit 10.

  The circuit 102 preferably includes an amplifier, for example. An example of an amplifier is an operational amplifier.

Alternatively, the circuit 102 preferably includes a comparator, for example. For example, the circuit 102 compares the magnitude relationship between the potential V _ND corresponding to the analog potential Vin held by the sample hold circuit 101 and the analog potential DACout output from the digital-analog converter circuit 104, and the signal cmpout is determined according to the magnitude relationship. It is preferable to have a function of outputting.

  The circuit 102 preferably includes an input terminal 241, an input terminal 242, and an output terminal 251. The sample hold circuit 101 is preferably electrically connected to the input terminal 241. For example, in the circuit 102, a signal is output from the output terminal 251 in accordance with the magnitude relationship between the potential input to the input terminal 241 and the potential input to the input terminal 242.

  Next, an operation example of the semiconductor device 100 will be described by focusing on the operation of the sample hold circuit 101, and effects of one embodiment of the present invention will be described in detail.

  A semiconductor device 100 illustrated in FIG. 1B illustrates a sample hold circuit 101 and a circuit 102. The sample hold circuit 101 shows a switch SW for supplying power to the buffer circuit 111.

The switch SW is controlled to be turned on or off by a control signal _PSW . When the switch SW is turned on, the node V _VDD becomes the potential VDD, and power can be supplied to the ground potential GND. The power supply can be stopped by turning off the switch SW.

  When the switch SW is turned on and the transistor 112 is turned on by the control signal S1, the charge corresponding to the analog potential Vin is transmitted to the node ND. Next, after the transistor 112 is turned off, the switch SW is turned off, and supply of power to the buffer circuit 111 is stopped. Since the off-state current of the transistor 112 in the off state is extremely low as described above, the charge corresponding to the analog potential Vin transmitted to the node ND remains off even when the supply of power to the buffer circuit 111 is stopped. Can be maintained by maintaining. Therefore, the supply of power to the sensor circuit 121 that supplies the analog potential can also be stopped.

  In order to improve the driving performance of the transistor and the degree of circuit integration, it is required to shorten the channel length of the transistor.

  In a transistor using conventional silicon, germanium, and a compound thereof, it is preferable to increase the gate electric field in order to suppress the short channel effect particularly in an element having a fine channel length, and to increase the gate electric field. It is preferable to reduce the thickness of the gate insulating film.

  On the other hand, a transistor including an oxide semiconductor is a storage transistor using electrons as a majority carrier. Therefore, the influence of DIBL (Drain-Induced Barrier Lowering), which is one of the short channel effects, is smaller than that of an inverting transistor having a pn junction. In other words, a transistor including an oxide semiconductor has resistance to a short channel effect.

  Since resistance to the short channel effect is high, a transistor using an oxide semiconductor can have a thicker gate insulating film than a conventional transistor using silicon or the like. For example, a thin gate insulating film having a thickness of about 10 nm may be used for a minute transistor having a channel length and a channel width of 50 nm or less. Here, for example, silicon oxide or the like can be used as the gate insulating film. By increasing the thickness of the gate insulating film, parasitic capacitance can be reduced. Therefore, the dynamic characteristics of the circuit may be improved. Further, by increasing the thickness of the gate insulating film, leakage current may be reduced and power consumption may be reduced.

  In a transistor using an intrinsic or substantially intrinsic oxide semiconductor, when the distance between the source electrode and the drain electrode is sufficiently small, the energy at the lower end of the conduction band is lowered due to the influence of the electric field between the source and the drain, and the conduction is reduced. The energy at the bottom of the belt and the Fermi level are close. This phenomenon is called a “Condition Band Lowering Effect” (CBL effect). Since the drain current starts to flow from a low gate voltage near 0 V in the Vg-Id characteristic due to the CBL effect, the driving voltage of the transistor may be lowered.

  Here, a CAAC-OS film is preferably used as the oxide semiconductor. The CAAC ratio of the CAAC-OS film is preferably high. By increasing the CAAC ratio, for example, the influence of carrier scattering of the transistor can be reduced, and high field-effect mobility can be obtained. In addition, since the influence of grain boundaries can be reduced, variation in on-state characteristics of transistors can be reduced. Therefore, a highly reliable semiconductor device can be obtained. In addition, by using a transistor with small variation, a driving voltage can be reduced and power consumption can be reduced. For example, a CAAC-OS film with a low defect density can be realized. In addition, a CAAC-OS film with few impurities can be realized. By reducing the defect density, for example, extremely low off-current characteristics can be realized.

  The semiconductor device of one embodiment of the present invention can include a transistor including an oxide semiconductor, so that the short channel effect can be suppressed and miniaturization of the circuit can be realized.

  In addition, since the drain electric field becomes stronger as the channel length becomes finer, in a conventional transistor using silicon or the like, the reliability deterioration due to hot carrier deterioration becomes more remarkable particularly when the channel length is fine. . On the other hand, an oxide semiconductor has a large band gap (for example, 2.5 eV or more for an oxide semiconductor containing indium, gallium, and zinc), is difficult to excite electrons, and has a large effective mass of holes. In some cases, avalanche collapse or the like is less likely to occur as compared with a transistor using the above. Therefore, for example, hot carrier deterioration due to avalanche collapse may be suppressed.

  By increasing the thickness of the gate insulating film, the breakdown voltage of the gate insulating film can be increased, and the transistor can be driven with a higher gate voltage than a conventional transistor using silicon or the like. Further, by suppressing hot carrier deterioration, the transistor can be driven with a high drain voltage without increasing the channel length. Accordingly, the reliability of the transistor can be increased in a circuit to which a high voltage is input, and the channel length can be reduced, so that the degree of circuit integration can be increased.

  In a conventional transistor using silicon or the like, the channel length is preferably set to, for example, 300 nm or more in order to ensure a breakdown voltage between the source and the drain in a circuit having a VDD potential of 3V. Here, the VDDV potential is used as a power source, for example. The gate insulating film is preferably 3 nm or less in terms of silicon oxide, and the physical thickness of the gate insulating film is preferably 6 nm or more in order to suppress the leakage current of the gate insulating film. On the other hand, in a transistor including an oxide semiconductor, a withstand voltage between the source and the drain may be sufficiently ensured even in a circuit having a VDD potential of 3 V, for example, with a channel length of 200 nm or less. In addition, the short channel effect may be suppressed even in a gate insulating film of, for example, 10 nm or more in terms of silicon oxide. That is, a transistor including an oxide semiconductor is preferable because the transistor can be miniaturized and leakage current of the gate insulating film can be suppressed.

  Here, according to one embodiment of the present invention, further miniaturization can be realized in a transistor including an oxide semiconductor. For example, in a circuit with a VDD potential of 3 V, the channel length may be 100 nm or less. That is, according to one embodiment of the present invention, the degree of circuit integration can be increased. Further, according to one embodiment of the present invention, a sufficient withstand voltage between the source and the drain of the transistor can be ensured.

  FIG. 2A is a timing chart illustrating an example of the operation of the sample hold circuit 101 illustrated in FIG. A hatched portion 231 in the figure represents a state in which previous data is held.

First, at time T1, the control signal _{PSW is set} to the high level. By setting the control signal _PSW to the high level, the switch SW is turned on, the node _VVDD becomes the potential VDD, and power is supplied to the ground potential GND. The potential Vin is amplified by the buffer circuit 111 and output as the potential Vbout. Then, the control signal S4 is set to the high level. Then, since the transistor 117 is turned on and the transistor 112 is also turned off, the potential of the node ND rises to the potential Va that is the potential of the input terminal a.

  Next, at time T2, the control signal S4 is set to the low level and the control signal S1 is set to the high level. Then, the transistor 117 is turned off and the transistor 112 is turned on. At this time, a potential difference between the potential Va and the potential Vbout is applied between the source and the drain of the transistor 112. The potential of the node ND is the potential Vbout.

  Here, by applying the potential Va to the node ND in advance, the difference in potential between the source and the drain of the transistor 112 can be made smaller than the potential difference between the potential Vbout and the ground potential GND at the time T2. Thus, the channel length of the transistor 112 can be further shortened.

  Here, the channel length of the transistor 112 is, for example, preferably 1 nm to 500 nm, more preferably 3 nm to 200 nm, and still more preferably 5 nm to 100 nm. More preferably, they are 10 nm or more and less than 60 nm, More preferably, they are 10 nm or more and less than 30 nm.

In the transistor 112, the gate capacitance per unit volume is, for example, preferably 1 fF · [mu] m ^-2 or 10 fF · [mu] m ^-2 or less, more preferably 2 fF · [mu] m ^-2 or more 9ff · [mu] m ^-2 or less.

  As the gate insulating film of the transistor 112, for example, a silicon oxide film thicker than 3 nm and thinner than 40 nm can be used. For the gate insulating film, a material having a higher dielectric constant such as hafnium oxide or silicon nitride can be used. As the gate insulating film of the transistor 112, for example, an insulating film having a thickness equivalent to a silicon oxide film and greater than 3 nm and less than 40 nm can be used. Here, the thickness in terms of silicon oxide film can be calculated as [physical film thickness of gate insulating film × dielectric constant of silicon oxide ÷ dielectric constant of gate insulating film].

  For example, the difference between the potential Va and the ground potential GND is preferably not less than 0.3 times and not more than 0.7 times the difference between the potential VDD and the ground potential GND. The sum of the difference between the potential Va and the ground potential GND and the threshold value of the transistor 117 is less than or equal to the difference between the potential VDD and the ground potential GND.

  Next, at time T3, the control signal S1 is set to low level. Then, the transistor 112 is turned off. Therefore, the potential Vbout is held at the node ND.

Then a control signal _{P SW} to the low level at time T4. By setting the control signal _PSW to a low level, the supply of power to the buffer circuit 111 is stopped. At this time, since the control signal S1 is at the low level, the potential Vbout is continuously held at the node ND.

  A potential corresponding to the node ND is output from the sample hold circuit 101 and input to the input terminal 241. The above is an example of the operation of the sample hold circuit 101 in FIG.

  FIG. 2B is a timing chart illustrating an example of the operation of the sample hold circuit 101 illustrated in FIG. A hatched portion 231 in the figure represents a state in which previous data is held.

First time the control signal P _SW to the high level at T1, that supply of power to the buffer circuit 111 is started, the potential Vbout a potential that potential Vin is amplified is output from the buffer circuit 111. Then, the control signal S4 is set to the high level. Then, since the transistor 117 is turned on, the potential of the node ND rises to the potential Va that is the potential of the input terminal a.

  Next, at time T2, the control signal S4 is set to low level. Then, the transistor 117 is turned off. Then, the control signal S1 is set to the high level, and the control signal S5 is set to the low level. Then, the transistor 112 is turned on. In addition, a charge corresponding to the potential difference between the two electrodes included in the capacitor 116 is accumulated in the capacitor 116. Here, at time T2, a signal obtained by inverting the logic of the control signal S1 is input to the control signal S5. At this time, for example, the potential difference of the potential of the control signal S5 with respect to the potential of the node ND is different in polarity from the potential difference of the potential of the control signal S1 with respect to the potential of the node ND. A potential difference between Vbout and the potential Vin is applied between the source and the drain of the transistor 112, and a current corresponding to the potential difference flows. Then, the potential of the node ND rises to the potential Vbout.

  Next, at time T3, the control signal S1 is set to low level, and the control signal S5 is set to high level. Then, the transistor 112 is turned off. Therefore, the potential Vbout is held at the node ND. Here, when the transistor 112 is turned off, the potential of the node ND may vary. At this time, since the sample-and-hold circuit 101 includes the capacitor 116, variation in the potential of the node ND may be suppressed.

Then a control signal _{P SW} to the low level at time T4. By setting the control signal _PSW to a low level, the supply of power to the buffer circuit 111 is stopped. At this time, since the control signal S1 is at the low level, the potential Vbout is continuously held at the node ND.

  A potential corresponding to the node ND is output from the sample hold circuit 101 and input to the input terminal 241. The above is an example of the operation of the sample hold circuit 101 in FIG.

  Here, as in the example illustrated in FIG. 3, the inverter 120 can be connected to a wiring that supplies the control signal S <b> 1, and an inverted signal of the control signal S <b> 1 can be applied to one electrode of the capacitor 116. With the configuration shown in FIG. 3, the control signal S5 is unnecessary, and the circuit can be simplified.

  As in the example illustrated in FIG. 4, the circuit 102 preferably includes a transistor 119. One of the source and the drain of the transistor 112 is preferably electrically connected to the gate of the transistor 119. In FIG. 4A, the potential output from the sample and hold circuit 101 is held at the gate of the transistor 119. As illustrated in FIG. 4B, the semiconductor device 100 may include a capacitor between the sample and hold circuit 101 and the transistor 119.

  In the semiconductor device 100, a circuit that generates a potential to be compared with the node potential ND is preferably input to the input terminal 242. An example of a circuit that generates the potential is a digital-analog conversion circuit.

  Further, as in the example illustrated in FIG. 5, the semiconductor device 100 preferably includes a successive approximation register 103 (abbreviated as SAR in the figure) and a timing controller 105 (abbreviated as T_con in the figure). The semiconductor device 100 preferably includes an oscillation circuit 106 (abbreviated as Osci. In the drawing).

  Here, the semiconductor device 100 illustrated in FIG. 5 functions as an AD converter.

  The semiconductor device 100 includes a sample hold circuit 101, a circuit 102, a successive approximation register 103, a digital / analog conversion circuit 104, a timing controller 105, and an oscillation circuit 106.

  The successive approximation register 103 has a function of holding and outputting digital data of N bits (N is a natural number of 2 or more) in accordance with a change in the analog potential DACout. N-bit, that is, 0th to (N-1) th bit digital data (abbreviated as value [N-1: 0] in the figure) is output to the outside as Vout, and is also sent to the digital-analog conversion circuit 104. Is output. The successive approximation register 103 is composed of a logic circuit including a register corresponding to each bit, and can output digital data according to the control of the control signal S2. The control signal S2 is a signal given from the timing controller 105.

  The digital-analog conversion circuit 104 has a function of generating and outputting an analog potential DACout according to digital data. The digital-analog conversion circuit 104 may be a capacitance conversion method (C-DAC) or a resistance conversion method (R-DAC). In particular, a C-DAC is preferable because a digital value can be held by using an OS transistor. Note that the structure of a C-DAC including an OS transistor will be described with a specific circuit structure in an embodiment described later.

The timing controller 105 has a function of generating and outputting control signals S1 and S2 synchronized with the clock signal CLK according to the signal S _ADC . The timing controller 105 includes a logic circuit, and can output control signals S1 and S2 according to the clock signal CLK and the signal S _ADC . As shown in FIG. 6, the timing controller 105 configured by a logic circuit can be formed integrally with the successive approximation register 103 configured by a logic circuit. The timing controller 105 may be referred to as a control circuit.

  The oscillation circuit 106 has a function of generating and outputting a clock signal CLK. The oscillation circuit 106 may be a clock signal generated by a crystal oscillator or a clock signal generated by a ring oscillator.

  The semiconductor device 100 functioning as an AD converter illustrated in FIG. 6 holds charges corresponding to the analog potential Vin acquired by a sensor circuit or the like in the sample and hold circuit 101 including the transistor 112 with extremely low off-state current. In the sample and hold circuit 101, a charge corresponding to the analog potential Vin is held at the node ND that can hold the charge by turning off the transistor 112. In one embodiment of the present invention, power supply to the buffer circuit 111 and the like included in the sample and hold circuit 101 can be stopped to reduce power consumption.

  Further, according to one embodiment of the present invention, power consumption can be reduced without suppressing the driving voltage and the frequency of the clock signal, so that the performance of the AD converter, such as resolution and sampling rate, can be prevented from being deteriorated. . Further, according to one embodiment of the present invention, analog data can be held without using a flash memory or the like, so that power consumption can be reduced without providing a dedicated high voltage generation circuit or a peripheral circuit.

  As for the sensor circuit 121, an example of an optical sensor is shown in FIG. 18, and an example of a touch sensor is shown in FIG.

  An optical sensor illustrated in FIG. 18A is provided in contact with the layer 1100 including the Si transistor and the photoelectric conversion element 66, the layer 1200 including the wiring layer, the layer 1200 including the wiring layer, and the OS transistor. And a layer 1300 including an OS transistor and a layer 1400 provided in contact with the layer 1300 and including a wiring layer. An insulating layer 1500 is formed over the photoelectric conversion element 66 formed in the layer 1100. A support substrate 1600 is provided in contact with the layer 1400. Note that the layer 1200, the layer 1300, and the layer 1400 can be omitted as illustrated in FIG.

  A light shielding layer 1510 is formed over the insulating layer 1500. Over the insulating layer 1500 and the light shielding layer 1510, an organic resin layer 1520 is formed as a planarization film. An optical conversion layer 1550 is formed on the organic resin layer 1520. A microlens array 1540 is provided on the optical conversion layer 1550, and light passing through one lens passes through the optical conversion layer 1550 directly below and irradiates the photoelectric conversion element 66. Note that the light-blocking layer 1510, the organic resin layer 1520, the optical conversion layer 1550, and / or the microlens array 1540 over the insulating layer 1500 can be omitted.

  Note that the OS transistor included in the layer 1300 may be provided in the same layer as the transistor included in the semiconductor device. In this case, since the sensor circuit and the semiconductor device can be formed using the same substrate, cost reduction and size reduction can be achieved.

  FIG. 19A is a block diagram illustrating a structure of a mutual capacitive touch sensor. FIG. 19A shows a pulse voltage output circuit 601 and a current detection circuit 602. Note that in FIG. 19A, a wiring 612 to which a pulse voltage is applied and a wiring 613 for detecting a change in current are illustrated as six wirings X1 to X6 and Y1 to Y6, respectively. FIG. 19A illustrates a capacitor 611 formed by the wiring 612 and the wiring 613 overlapping with each other.

  The pulse voltage output circuit 601 is a circuit for sequentially applying a pulse voltage to the wires X1 to X6. When a pulse voltage is applied to the wirings X1 to X6, an electric field is generated in the wirings 612 and 613 forming the capacitor 611. By utilizing the fact that the electric field generated between the electrodes changes the mutual capacitance in the capacitor 611 due to shielding or the like, it is possible to detect the proximity or contact of the detection target.

  The current detection circuit 602 is a circuit for detecting a change in current in the wirings Y1 to Y6 due to a change in mutual capacitance in the capacitor 611. In the wirings Y1 to Y6, there is no change in the current value detected when there is no proximity or contact with the detected object, but the current value is decreased when the mutual capacitance decreases due to the proximity or contact with the detected object. Detect decreasing changes. Note that current detection may be performed using an integration circuit or the like.

  Next, FIG. 19B is a timing chart of input / output waveforms in the mutual capacitive touch sensor unit shown in FIG. In FIG. 19B, it is assumed that the detection target is detected in each matrix in one frame (1F) period. In FIG. 19B, the case where the detected body is detected and the case where the detected body is not detected are shown separately. In addition, about the wiring of Y1 thru | or Y6, the waveform is shown by making the detected electric current value into a voltage value.

  A pulse voltage is sequentially applied to the wirings X1 to X6, and the waveforms in the wirings Y1 to Y6 change according to the pulse voltage. When there is no proximity or contact of the detection object, the waveforms of Y1 to Y6 change according to the change of the voltage of the wiring of X1 to X6. On the other hand, when there is proximity or contact with the detected object, the current value decreases at the location where the detected object is close or in contact, and the voltage value waveform also changes.

  In this way, by detecting the change in mutual capacitance, it is possible to detect the proximity or contact of the detected object. In addition, it is good not only as a structure of FIG. 19 (A) and (B) but another touch sensor.

  Note that a plurality of sensor circuits for supplying the analog potential Vin to the sample hold circuit 101 may be provided. In this case, when the sensor circuits 121A and 121B are provided as shown in FIG. 7, sample hold circuits 101A and 101B are provided. A selector 122 (also referred to as a multiplexer, abbreviated as MPX in the figure) is provided between the sample hold circuits 101A and 101B and the circuit 102.

  The selector 122 has a function of selecting one of the analog potentials of the sample and hold circuits 101A and 101B in accordance with the selection signal SEL and outputting the selected analog potential to the circuit 102. Since the sample hold circuits 101A and 101B have the same functions as the sample hold circuit 101 described with reference to FIGS. 1 and 2, respectively, the sample hold circuits 101A and 101B hold charges corresponding to the analog potentials Vin_A and Vin_B obtained by the sensor circuits 121A and 121B. The supply of power to the circuit can be stopped. Therefore, the power consumption can be reduced. In addition, once the analog potentials Vin_A and Vin_B are sampled by the sample hold circuits 101A and 101B, the supply of power to the sensor circuits 121A and 121B can be stopped in order to stop the supply of the analog potentials Vin_A and Vin_B. . Therefore, the power consumption of the sensor circuits 121A and 121B can be reduced.

  Note that the analog potential obtained by the sensor circuit may be constant or constantly fluctuate. When sampling a fluctuating analog potential, sampling may be performed via a correlated double sampling (CDS) circuit. The correlated double sampling circuit is used for noise removal by obtaining a relative difference between two timings.

  FIG. 8A shows an example of a correlated double sampling circuit. The correlated double sampling circuit includes a plurality of sample and hold circuits 131A to 131. As the sample hold circuits 131A to 131 shown in FIG. 8A, a circuit equivalent to the sample hold circuit 101 shown in FIG. 1A can be used. A control signal φ1 is applied to the transistors of the sample hold circuit 131A, and a control signal φ2 is applied to the transistors of the sample hold circuits 131B and 131C.

  By using an OS transistor as a transistor that is turned off by the control signals φ1 and φ2, the fluctuation of the sampled potential can be reduced to take the difference. Therefore, the accuracy of the correlated double sampling circuit can be increased. In addition, once the potential is sampled, power supply to the buffer circuits included in the sample hold circuits 131A to 131 can be stopped, so that power consumption can be reduced.

FIG. 8B shows a timing chart as an example of the operation of the correlated double sampling circuit shown in FIG. The potential V _Sensor is a varying potential obtained by the sensor circuit 121, and the potential V _NDT is an analog potential that has passed through a correlated double sampling circuit. As shown in FIG. 8B, even if the potential V _Sensor fluctuates, the voltage ΔV of the potential V _Sensor is averaged and the potential V _NDT is averaged by sampling at a constant period and taking the difference. It can be obtained as a constant analog potential. Here, in FIG. 8A, the sample hold circuit 131B is provided with a buffer circuit; however, the buffer circuit may not be provided.

  Next, FIG. 9 illustrates an example in which a circuit equivalent to the sample hold circuit 101 illustrated in FIG. 1B or the like is used as the sample hold circuit 131A to the sample hold circuit 131C. That is, each sample and hold circuit includes a second transistor and a second capacitor. In the second transistor, one of a source and a drain is connected to the node ND, and the potential Va is input to the other. In the second capacitor element, one electrode is connected to the node ND, and a control signal is input to the other electrode. Here, the control signal S41 is input to the gate of the second transistor included in the sample hold circuit 131A, and the control signal S42 is input to the second transistor included in the sample hold circuits 131B and 131C. The control signal S51 is input to the other electrode of the second capacitor of the sample hold circuit 131A, and the control signal S52 is input to the other electrode of the second capacitor of the sample hold circuits 131B and 131C. Is done.

  FIG. 10 is a timing chart for explaining the operation of the circuit shown in FIG. The control signal S52 is inputted with a signal having a phase opposite to that of the control signal φ2, and the control signal S51 is inputted with a signal having a phase opposite to that of the control signal φ1.

  First, the control signal S42 is set to the high level. Next, the control signal S42 is set to the low level, the control signal φ2 is set to the high level, the control signal S52 is set to the low level, and a charge corresponding to the potential obtained by amplifying the potential Vsensor is accumulated in the node ND of the sample hold circuit 131C. In addition, as for the potential of the node ND of the sample hold circuit 131B, charges corresponding to previously stored data are accumulated in the sample hold circuit 131A.

Next, the control signal S41 is set to the high level. Next, the control signal S41 is set to the low level, the control signal φ1 is set to the high level, the control signal S51 is set to the low level, and a charge corresponding to the potential obtained by amplifying the potential Vsensor is accumulated in the node ND of the sample hold circuit 131A. Here, the potential V _NDT is a value obtained by averaging the charge accumulated in the sample hold circuit 131B and the charge accumulated in the sample hold circuit 131A.

  Next, FIG. 11 illustrates an example of a circuit configuration of the circuit 102. A circuit 102 illustrated in FIG. 11 includes P-channel transistors 141 to 153, N-channel transistors 154 to 166, and a resistance element 167. In FIG. 6, the terminal INP corresponds to a non-inverting input terminal, and the terminal INM corresponds to an inverting input terminal.

  Next, FIG. 12A illustrates an example of a circuit configuration of the oscillation circuit 106. The oscillation circuit 106 illustrated in FIG. 12A includes a P-channel transistor 171, an inverter circuit 172, an N-channel transistor 173, and a bias voltage generation circuit 174. In FIG. 6, the terminal BIASP corresponds to a terminal that applies a positive bias voltage, and the terminal BIASP corresponds to a terminal that applies a negative bias voltage.

  FIG. 12B illustrates an example of a circuit configuration of the bias voltage generation circuit 174 illustrated in FIG. The bias voltage generation circuit 174 shown in FIG. 12B includes P-channel transistors 176 to 181, N-channel transistors 183 to 188, a resistance element 189, and capacitor elements 190 to 193.

  Next, FIG. 13A illustrates an example of a circuit configuration of the digital-analog converter circuit 104. FIG. 13A shows a 10-bit C-DAC. In FIG. 13A, the sample hold circuit 101 and the circuit 102 are shown together for explanation. A digital-analog conversion circuit 104 illustrated in FIG. 13A includes a capacitor 193, selectors 194, 195, and 196 and a transistor 197. The capacitor 193 has a capacitance value corresponding to the number of bits. An example of the capacitance value is attached to the capacitor 193 in FIG. The selectors 194 and 195 are provided corresponding to the capacitor 193. Further, although not illustrated, in FIG. 8A, the potential Va is preferably input to the sample hold circuit 101.

  FIG. 13B illustrates an example of a circuit configuration of the selectors 194, 195, and 196 illustrated in FIG. A control signal S2 is given to the terminals SEL of the selectors 195 and 196. Note that the potential selected by the selector 196 is applied to the terminals A of the selectors 194 and 195. Note that the reference potential Vref is applied to the terminal A of the selector 196. A ground potential is applied to the terminal B of the selectors 194, 195, and 196.

  FIG. 13C illustrates an example of a more specific circuit configuration of the selector illustrated in FIG. The selector shown in FIG. 13C includes an inverter circuit 198, N-channel transistors 135 and 136, and P-channel transistors 137 and 138.

  A semiconductor device 100 illustrated in FIG. 14 includes a sample and hold circuit 101, a successive approximation register 103, a digital / analog conversion circuit 104, a timing controller 105, and an oscillation circuit 106.

The configuration of the semiconductor device 100 illustrated in FIG. 14 is different from that illustrated in FIG. 5 in that the digital-analog conversion circuit 104 includes a transistor 211 and a capacitor 212 for holding digital data. A control signal S3 _{value [N-1: 0]} for controlling on or off is supplied from the timing controller 105 to the gate of the transistor 211 in correspondence with each bit. In the present embodiment, points that are different from the first embodiment will be described in detail, and descriptions of points that overlap with the first embodiment will be omitted.

The transistor 211 and the capacitor 212 hold digital data by holding the charge corresponding to the potential of the digital data in the node ND _DAC by turning off the transistor 211. The transistor 211 is a transistor having a function of extremely low current flowing between the source and the drain in the off state, like the transistor 112, and is preferably an OS transistor. Note that a circuit including a transistor 211 and a capacitor 212 that holds charges corresponding to the potential of digital data is illustrated as a circuit 20. Here, the circuit 20 may include a transistor 217 and a capacitor 216 as illustrated in FIG. One of a source and a drain of the transistor 217 is electrically connected to one of the source and the drain of the transistor 211. Further, the potential Va is preferably input to the other of the source and the drain of the transistor 217. One electrode of the capacitor 216 is electrically connected to one of a source and a drain of the transistor 211.

In the case where digital data is held in the digital-analog converter circuit 104, a transistor 211 and a capacitor 212 may be added to the selector 194 described with reference to FIGS. In addition, a transistor 217 and a capacitor 216 may be added to the selector 194. 17A and 17B each illustrate an example of a circuit diagram in which a transistor 211, a capacitor 212, a transistor 217, and a capacitor 216 are added to the selector 194. In FIG. 17 (A), (B) , the control signal _{S3 value:} as _{[N-1 0],} shows an example of giving 0 control signal _S3 bit _value of _[0] to the gate of the transistor 211.

  With the configuration in FIG. 17, power consumption can be reduced by stopping the supply of power to the sample hold circuit 101, the circuit 102, the successive approximation register 103, and the digital-analog conversion circuit 104. By holding the charge corresponding to the analog potential Vin in the sample hold circuit 101, the power supply to the buffer circuit 111 can be stopped. Further, the supply of power to the register in the successive approximation register 103 can be stopped every time the digital data in the digital-analog conversion circuit 104 is determined by each bit. Further, power supply to the circuit 102 and the digital-analog conversion circuit 104 can be stopped.

Next, in order to describe a specific operation of the semiconductor device 100, FIG. 15 shows a circuit configuration of a 2-bit AD converter in the configuration of FIG. In FIG. 15, the successive approximation register 103 shows a register 221 that holds 0-bit digital data and a register 222 that holds 1-bit digital data. Further, a control signal P _{value [0]} for controlling supply or stop of power to the register 221 and a control signal P _{value [1]} for controlling supply or stop of power to the register 222 are illustrated. Further, a control signal P ₁₁₁ for controlling supply or stop of power supply to the buffer circuit 111, a control signal P _DAC for controlling supply or stop of power supply to the digital / analog conversion circuit 104, and control of supply or stop of power supply to the circuit 102 A control signal P _Comp is shown.

  Next, the operation of the semiconductor device 100 in FIG. 15 will be described with reference to a timing chart shown in FIG. As an example, VDD is 3V, VSS is 0V, Vref is 2V, and Vbout is 1.5V. When converting an analog value of 1,5V to a 2-bit digital value, there are states corresponding to digital values of “00”, “01”, “10”, and “11”, and 0 .. The description will be made assuming that the analog values are 5V, 1.0V, 1.5V, and 2.0V. A hatched portion 231 in the figure represents a state in which previous data is held.

When the signal S _ADC is input to the timing controller 105, the timing controller starts the operation of the oscillation circuit 106 and outputs the clock signal CLK. When the signal S _ADC is input to the timing controller 105, the timing controller 105 outputs a control signal S 1 to the sample hold circuit 101. The timing controller 105 outputs a control signal S <b> 2 to the digital / analog conversion circuit 104 and the successive approximation register 103. The timing controller 105 outputs a control signal S3 _{value [1: 0]} to the digital-analog conversion circuit 104 and the successive approximation register 103.

In FIG. 16, the control signal S1 is a signal having the same waveform as the signal S _ADC , but may be a signal having a different waveform as long as the semiconductor device 100 operates normally. The sample and hold circuit 101 starts operating in response to the control signal S1. The analog potential Vin input to the sample hold circuit 101 is amplified by the buffer circuit 111 and output from the buffer circuit 111 as Vbout. Vbout is supplied to the node ND by turning on the transistor, and is held as an analog potential of 1.5 V at the node ND by turning off the transistor 112.

  In FIG. 16, the control signal S2 is a signal having the same waveform as the clock signal CLK, but may be a signal having a different waveform as long as the semiconductor device 100 operates normally. The successive approximation register 103 is reset by the control signal S2. Further, the digital-analog converter circuit 104 is reset by the control signal S1 and the control signal S2.

In FIG. 16, the control signal S3 _{value [1: 0]} is at a high level until the digital data of each bit is determined, but may be a signal having a different waveform as long as the semiconductor device 100 operates normally. After the digital data of each bit is determined by the control signal S3 _{value [1: 0]} , on / off of the transistor 211 is controlled so as to hold the digital data.

After holding the analog potential of 1.5V to node ND by the control signal S1 by turning off the transistor 112, the power supply to the buffer circuit 111 of the sample and hold circuit 101 is stopped by the control signal _{P 111.} Even when the supply of power to the buffer circuit 111 is stopped, the transistor 112 is off, so that the analog potential can be held while power consumption is reduced.

  By resetting the successive approximation register 103 with the control signal S2, the register 221 and the register 222 are initialized to “00”. The register 221 and the register 222 may be initialized to “11”.

By turning on the transistor 211 with the control signal S3 _{value [1: 0]} , digital data of each bit is supplied to the digital-analog conversion circuit 104.

  Subsequently, at the rising edge of the first cycle of the clock signal CLK, the timing controller 105 sets 1-bit digital data, which is the most significant bit, in the register 222 of the successive approximation register 103 to “1”. Further, in accordance with the control signal S 2, the digital-analog conversion circuit 104 converts the digital data “10” of the successive approximation register 103 into an analog potential DACout of 1.5 V and outputs it to the circuit 102. Then, the circuit 102 compares the analog potential Vbout held at the node ND of 1.5V with the digital / analog converted analog potential DACout of 1.5V, and if Vbout is equal to or higher than the analog potential DACout, The signal cmpout outputs a high level, and if it is less, it outputs a low level. Here, since the analog potentials of 1.5 V are compared, the signal cmpout is at a high level. The signal cmpout is input to the successive approximation register 103.

Subsequently, since the 1-bit digital data which is the upper bit is determined to be “1”, the timing controller 105 sets the control signal S3 _{value [1]} to the low level at the falling edge of the first cycle of the clock signal CLK, and turns off the transistor 211. Thus, 1-bit digital data is held in the digital-analog conversion circuit 104. Further, the control signal P _{value [1] is set} to the low level, and the supply of power to the register 222 of the successive approximation register 103 is stopped. Even when the supply of power to the register 222 is stopped, the transistor 211 is off, so that digital data can be held in the digital-analog converter circuit 104 while reducing power consumption.

  Subsequently, at the rising edge of the second cycle of the clock signal CLK, the timing controller 105 sets the 0-bit digital data, which is the least significant bit, in the register 221 of the successive approximation register 103 to “1”. Further, in accordance with the control signal S 2, the digital-analog conversion circuit 104 converts the digital data “11” of the successive approximation register 103 into an analog potential of 2.0 V and outputs it to the circuit 102. Then, the circuit 102 compares the analog potential Vbout held at the node ND of 1.5V with the digital / analog converted analog potential DACout of 2.0V, and the analog potential Vbout is equal to or higher than the analog potential DACout. If there is, the signal cmpout outputs a high level, and if it is less, it outputs a low level. Here, since the analog potential Vbout of 1.5 V and the analog potential DACout of 2.0 V are compared, the signal cmpout is at a low level. The signal cmpout is input to the successive approximation register 103.

Subsequently, since the 0-bit digital data, which is the lower bit, is determined to be “0”, the timing controller 105 sets the control signal S3 _{value [0]} to the low level at the fall of the second cycle of the clock signal CLK, and turns off the transistor 211. Thus, 0-bit digital data is held in the digital-analog conversion circuit 104. In addition, the control signal P _{value [0] is set} to a low level, and the supply of power to the register 221 of the successive approximation register 103 is stopped. Even when the supply of power to the register 221 is stopped, the transistor 211 is off, so that digital data can be held in the digital-analog converter circuit 104 while reducing power consumption.

In addition, the timing controller 105 sets the control signals P _{Comp and} P _ADC to the low level at the falling edge of the second cycle of the clock signal CLK, and the supply of power to the circuit 102 and the digital-analog conversion circuit 104 is stopped. Even when power to the circuit 102 and the digital-analog converter circuit 104 is stopped, the transistor 211 is turned off, so that digital data can be held in the digital-analog converter circuit 104 while reducing power consumption. Can do.

  Thus, the analog potential Vbout of 1.5 V is converted into 2-bit digital data “10”.

  In the structure disclosed in this embodiment mode, the potential of analog data or digital data can be held even after the supply of power is stopped using an OS transistor, so that the supply of power to each circuit is stopped and consumed. Electric power can be reduced. Further, by stopping the power supply of the entire semiconductor device functioning as an AD converter after the digital data is determined, power consumption can be reduced until the next analog potential Vbout is input.

  As described above, in the semiconductor device of this embodiment functioning as an AD converter as described above, the analog potential Vbout obtained by a sensor or the like is applied to the sample hold circuit 101 having a transistor with extremely low off-state current. Hold. In addition, the determined digital data is held in the digital-analog conversion circuit. In one embodiment of the present invention, power supply to each circuit included in a semiconductor device can be stopped to reduce power consumption.

  In addition, since the semiconductor device of this embodiment can reduce power consumption without suppressing the drive voltage and the frequency of the clock signal, the AD converter performance such as resolution and sampling rate should not be deteriorated. Can do. In addition, since the semiconductor device of this embodiment can hold analog data without using a flash memory or the like, power consumption can be reduced without providing a dedicated high voltage generation circuit or a peripheral circuit. .

(Embodiment 2)
In this embodiment, an example of a cross-sectional structure of a semiconductor device is described with reference to FIGS. In the example of this embodiment mode, an OS transistor is formed by stacking on a circuit formed by a transistor (Si transistor) using silicon or the like.

  FIG. 21 illustrates a partial cross section of the semiconductor device. The semiconductor device illustrated in FIG. 21 includes an n-type transistor and a p-type transistor using a first semiconductor material (eg, silicon) in a lower portion, and a second semiconductor material (eg, an oxide semiconductor) in an upper portion. And a capacitor and a capacitor.

  A transistor using the first semiconductor material is formed over the substrate 270. As the substrate 270, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.

  Further, as the substrate 270, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a bonded substrate A laminated film, paper containing a fibrous material, a base film, or the like may be used. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, and papers.

  Note that a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. Examples of substrates on which semiconductor elements are transferred include paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (natural fibers (silk, cotton, hemp)) , Synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrate, rubber substrate, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

  FIG. 21 shows an example in which a single crystal silicon wafer is used for the substrate 270 as an example.

The FET layer 260 is provided with a semiconductor element using the first semiconductor material, such as a Si transistor. FIG. 21 representatively shows transistors M71 to M73 as Si transistors. Wiring layers W ₁ -W ₄ are stacked on the FET layer 260. FET layer 261 is laminated on the wiring layer _{W 4.}

  The transistor M71 includes a channel formation region 272 provided in the well 271 and a low-concentration impurity region 273 and a high-concentration impurity region 274 provided so as to sandwich the channel formation region 272 (these are also simply referred to as impurity regions). A conductive region 275 provided in contact with the impurity region; a gate insulating film 276 provided over the channel formation region 272; and a gate electrode 277 provided over the gate insulating film 276. Sidewall insulating films 278 and 279 are provided on the side surfaces of the gate electrode 277. Note that a metal silicide or the like can be used for the conductive region 275. The transistor M72 may be a transistor having a polarity different from that of the transistor M71. For example, the transistor M71 may be an n-type transistor, the transistor M72 may be a p-type transistor, and the transistor M73 may be an n-type transistor.

The FET layer 261 is a layer where an OS transistor is formed, and a transistor M70 is formed. Here, the structure of the transistor M70 is similar to that of the transistor 600 illustrated in FIG. As a second gate of the transistor M70 (back gate), the conductive layer 280 is formed on the wiring layer _{W 4.} The capacitor C71 has a structure in which the source and the drain are short-circuited and used as a capacitor in the transistor M70.

Wiring layers W ₅ , W ₆ are stacked on the FET layer 261, a capacitor C 70 is stacked on the wiring layer W ₇ , and wiring layers W ₈ , W ₉ are stacked on the capacitor C 70. The capacitor C70 includes conductive layers 281 and 282. Here, the layer in which the conductive layer 281 is formed is used as a wiring layer. By providing the capacitor C70 on the FET layer 261, it is easy to increase the capacity of the capacitor C70. Further, the capacitor C70 can be provided in the FET layer 261 depending on the size of the capacitor C70. In this case, two electrodes may be formed using the same conductive layer as the source and drain electrodes of the transistor M70 and the same conductive layer as the gate electrode. Providing the capacitor C70 in the FET layer 261 can reduce the number of processes, leading to a reduction in manufacturing cost.

  The insulating layers 291 to 293 preferably include at least one layer formed of an insulator having a blocking effect against hydrogen, water, and the like. Since water, hydrogen, and the like are one of the factors that generate carriers in the oxide semiconductor, the reliability of the transistor M70 can be improved by providing a blocking layer for hydrogen, water, and the like. Examples of the insulator having a blocking effect against hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and yttria-stabilized zirconia (YSZ). ) Etc.

  The area | region where the code | symbol and hatching pattern of FIG. 21 are not given is comprised with the insulator. Examples of the insulator include aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and hafnium oxide. An insulator containing one or more materials selected from tantalum oxide and the like can be used. In the region, an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can be used. Note that in this specification, an oxynitride refers to a compound having a higher oxygen content than nitrogen, and a nitride oxide refers to a compound having a higher nitrogen content than oxygen.

  By using a single crystal semiconductor substrate as the semiconductor substrate, the transistor M71 and the transistor M72 can be operated at high speed, and the threshold value can be precisely controlled. Therefore, it is preferable to form all or part of the sample-and-hold circuit, the comparator, the successive approximation register, the analog-digital conversion circuit, the timing controller, the oscillation circuit, and the like in the semiconductor device described in the above embodiment over a single crystal semiconductor substrate. .

  Here, for example, the transistor M70, the transistor M71, the capacitor C70, and the capacitor C71 may be used as the transistor 112, the transistor 117, the capacitor 113, and the capacitor 116 illustrated in FIG.

In FIG. 21, one of the source and the drain of the transistor M70 is electrically connected to the conductive layer 281 of the capacitor C70 through the wiring layers W ₆ , W _{7 and the} like. One of the drain and the source of the transistor M70 is electrically connected to one of the source and the drain of the transistor M71 through the wiring layers W ₂ and W _{3 and the} like. The conductive layer 281 of the capacitor C70 is, via the conductive layer wiring layer _W 6, _{W 7} and the like is one electrode electrically connected to capacitor C71.

  The transistor M70 may be electrically connected to, for example, the transistor M72 or the transistor M73 included in the FET layer 260. In the example illustrated in FIG. 21, the other of the source and the drain of the transistor M70 is electrically connected to one of the source and the drain of the transistor M72 and the one of the source and the drain of the transistor M73.

Here, as in the example shown in FIG. 20, capacitor C70 may be provided between the wiring layer W ₃ and the wiring layer W _4.

  In addition, as illustrated in FIG. 20, the transistors M <b> 71 to M <b> 73 may be provided on the convex portion of the substrate 270. FIG. 22 shows an example of a cross section of the transistor M71 perpendicular to the cross section shown in FIG. Carriers flow in a wide range including the side and the upper portion of the channel formation region 272 by overlapping the conductive film 277 with the side and upper portions of the protrusions in the channel formation region 272 sandwiching the gate insulating film 276 therebetween. . Therefore, it is possible to increase the amount of carrier movement in the transistor M71 and the like while keeping the exclusive area on the substrate of the transistor M71 and the like small. As a result, the on-current of the transistor M71 and the like is increased, and the field effect mobility is increased. In the example shown in FIG. 20, the transistors M71 to M73 are isolated using a trench isolation method (STI method: Shallow Trench Isolation) or the like.

(Embodiment 3)
In this embodiment, the OS transistor described in the above embodiment is described.

<Characteristics of OS transistor>
An OS transistor can reduce off-state current by reducing an impurity concentration in an oxide semiconductor and making the oxide semiconductor intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density in the oxide semiconductor is less than 1 × 10 ¹⁷ / cm ³ , preferably less than 1 × 10 ¹⁵ / cm ³ , and more preferably 1 × It indicates less than 10 ¹³ / cm ³ . In an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than main components are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density.

  A transistor including an intrinsic or substantially intrinsic oxide semiconductor has low carrier density, and thus has less electrical characteristics with a negative threshold voltage. In addition, a transistor including the oxide semiconductor has few carrier traps in the oxide semiconductor, and thus has a small change in electrical characteristics and has high reliability. In addition, a transistor including the oxide semiconductor can have extremely low off-state current.

Note that in an OS transistor with a low off-state current, the normalized off-current per channel width of 1 μm at room temperature (about 25 ° C.) is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably ^{May be} 1 × 10 ⁻²⁴ A or less, or 1 × 10 ⁻¹⁵ A or less at 85 ° C., preferably 1 × 10 ⁻¹⁸ A or less, and more preferably 1 × 10 ⁻²¹ A or less.

<Off current>
In this specification, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise specified. Is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

  The off-state current of the transistor may depend on Vgs. Therefore, when there is Vgs at which the off-state current of the transistor is I or less, the off-state current of the transistor is sometimes I or less. The off-state current of the transistor is a value at which an off-state current when Vgs is a predetermined value, an off-current when Vgs is a value within a predetermined range, or an off-current with sufficiently reduced Vgs is obtained. Sometimes refers to off-state current.

As an example, the drain current when the threshold voltage Vth is 0.5 V and Vgs is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1 V is 1 × 10 ^−13. Assume an n-channel transistor in which the drain current is 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and the drain current is 1 × 10 ⁻²² A when Vgs is −0.8 V. . Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

  In this specification, the off-state current of a transistor having a channel width W may be expressed by a value per channel width W. Further, it may be expressed by a current value per predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be expressed as current / length (for example, A / μm).

  The off-state current of a transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device or the like including the transistor is guaranteed, or a temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature of 5 ° C. to 35 ° C.). May represent off-state current. Room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or a temperature at which the semiconductor device including the transistor is used (for example, 5 When the Vgs at which the off-state current of the transistor is equal to or lower than I is present at any one temperature of from 35 ° C. to 35 ° C., the off-state current of the transistor is sometimes equal to or lower than I.

  The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-state current has an absolute value of Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, It may represent off current at 12V, 16V, or 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented. When Vds is a predetermined value and there is Vgs where the off-state current of the transistor is I or less, the off-state current of the transistor is sometimes I or less. Here, the predetermined value is, for example, 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, This is the value of Vds that ensures the reliability of the included semiconductor device or the like, or the value of Vds used in the semiconductor device or the like that includes the transistor.

  In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

  In this specification, the term “leakage current” may be used to mean the same as off-state current.

  In this specification, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

<Composition of oxide semiconductor>
Note that an oxide semiconductor used for the semiconductor layer of the OS transistor preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. In addition to these, it is preferable to have a stabilizer that strongly binds oxygen. The stabilizer may include at least one of gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al).

  Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), and terbium (Tb). , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

  Examples of the oxide semiconductor used for the semiconductor layer of the transistor include indium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, and Zn—Mg oxide. Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also referred to as IGZO), In-Al-Zn oxide, In-Sn- Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-Zr-Zn-based oxide, In-Ti-Zn-based oxide, In-Sc-Zn-based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn -Based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based , In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er -Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga- Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide, etc. is there.

  For example, In: Ga: Zn = 1: 1: 1 or its vicinity, In: Ga: Zn = 4: 2: 3 or its vicinity, In: Ga: Zn = 5: 1: 6 or its vicinity, In: Ga : Zn = 3: 1: 2 or the vicinity thereof, In: Ga: Zn = 2: 1: 3 or an In—Ga—Zn-based oxide having an atomic ratio of the vicinity thereof or an oxide in the vicinity thereof is used. Good.

<Impurities in oxide semiconductors>
When a large amount of hydrogen is contained in the oxide semiconductor film included in the semiconductor layer, a part of the hydrogen serves as a donor and an electron serving as a carrier is generated by bonding with the oxide semiconductor. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after the oxide semiconductor film is formed, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film so that impurities are contained as little as possible. preferable.

  Note that oxygen may be reduced from the oxide semiconductor film due to dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, it is preferable to perform treatment in which oxygen is added to the oxide semiconductor film in order to fill oxygen vacancies increased by dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film.

In this manner, the oxide semiconductor film is made i-type (intrinsic) or i-type by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and filling oxygen vacancies by oxygenation treatment. An oxide semiconductor film that is substantially i-type (intrinsic) can be obtained. Note that substantially intrinsic means that the number of carriers derived from a donor in the oxide semiconductor film is extremely small (near zero), and the carrier density is 1 × 10 ¹⁷ / cm ³ or less, 1 × 10 ¹⁶ / cm ³ or less, It means 1 × 10 ¹⁵ / cm ³ or less, 1 × 10 ¹⁴ / cm ³ or less, and 1 × 10 ¹³ / cm ³ or less.

<Structure of oxide semiconductor>
The structure of the oxide semiconductor is described.

  In this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

  An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

  From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

  Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

  That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor.

[CAAC-OS]
First, the CAAC-OS will be described.

  A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS including an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even when 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 45E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 45E, a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 45E is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 45E is considered to be due to the (110) plane and the like.

  In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

  FIG. 46A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

  FIG. 46A shows a pellet which is a region where metal atoms are arranged in a layered manner. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.

FIGS. 46B and 46C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface. 46D and 46E are images obtained by performing image processing on FIGS. 46B and 46C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is obtained by performing Fast Fourier Transform (FFT) processing on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

  In FIG. 46D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

  In FIG. 46E, a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. By connecting the surrounding lattice points around the lattice points in the vicinity of the dotted line, a distorted hexagon, pentagon and / or heptagon can be formed. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

  As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as a CAA crystal (c-axis-aligned ab-plane-anchored crystal).

  The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

  Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

  In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ pieces / cm ³ , more preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × 10 ⁻⁹ pieces / cm 3. An oxide semiconductor having a carrier density of ³ or more can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

[Nc-OS]
Next, the nc-OS will be described.

  A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel to the formation surface, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 47B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 47B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

  When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

  FIG. 47D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a fine crystal oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

  Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

  Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned Nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

  The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[A-like OS]
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 48 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 48A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 48B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . 48A and 48B, it can be seen that the a-like OS has a striped bright region extending in the vertical direction from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

  Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

  As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.

  First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as an InGaZnO ₄ crystal part. Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 49 is an example in which the average size of the crystal parts (from 22 to 30 locations) of each sample was examined. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 49, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative dose of electrons related to the acquisition of the TEM image or the like. According to FIG. 49, the accumulated irradiation dose of electrons (e ⁻ ) is 4.2 × 10 ⁸ e ⁻ / nm in the crystal part (also referred to as initial nucleus) which was about 1.2 nm in the initial observation by TEM. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 49 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

  As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

  In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

  Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

  As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

  As described above, the OS transistor can realize extremely excellent off-current characteristics.

(Embodiment 4)
In this embodiment, electronic devices each including the semiconductor device described in the above embodiment are described. Examples of electronic devices include devices having wireless communication means such as computers, various portable information terminals (including mobile phones, portable game machines, sound playback devices, and the like), electronic book terminals, and wireless keyboards. In addition, a refrigerator, an air conditioner, an automobile, a washing machine, and a cooking device (such as a microwave oven) are provided with wireless communication means having the signal processing device described in the above embodiment, and are remotely operated from a computer or various portable information terminals. Is also possible.

  FIG. 23A illustrates a portable information terminal including a housing 701, a housing 702, a first display portion 703a, a second display portion 703b, and the like. At least part of the housing 701 and the housing 702 is provided with the semiconductor device described in the above embodiment. Therefore, a portable information terminal with low power consumption is realized.

  Note that the first display portion 703a is a panel having a touch input function. For example, as illustrated in the left diagram of FIG. 23A, a selection button 704 displayed on the first display portion 703a displays “touch input”. "Or" keyboard input "can be selected. Since the selection buttons can be displayed in various sizes, a wide range of people can feel ease of use. For example, when “keyboard input” is selected, the keyboard 705 is displayed on the first display portion 703a as shown in the right diagram of FIG. As a result, as in the conventional information terminal, quick character input by key input and the like are possible.

  In the portable information terminal illustrated in FIG. 23A, one of the first display portion 703a and the second display portion 703b can be removed as illustrated on the right side of FIG. . The first display portion 703b is also a panel having a touch input function, and can be further reduced in weight when carried, and can be operated with the other hand while holding the housing 702 with one hand. is there.

  FIG. 23A illustrates a function for displaying various information (still images, moving images, text images, and the like), a function for displaying a calendar, date, time, or the like on the display unit, and operating or editing information displayed on the display unit. A function, a function of controlling processing by various software (programs), and the like can be provided. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing.

  Alternatively, the portable information terminal illustrated in FIG. 23A can be configured to purchase desired book data and the like from an electronic book server and download them wirelessly. Further, the housing 702 illustrated in FIG. 23A may have an antenna, a microphone function, or a wireless function, and may be used as a mobile phone. Note that in a state where the housing 701 and the housing 702 are separated from each other, information can be exchanged via wireless communication.

  FIG. 23B illustrates an electronic book terminal mounted with electronic paper, which includes two housings, a housing 711 and a housing 712. A display portion 713 and a display portion 714 are provided in the housing 711 and the housing 712, respectively. For example, the display unit 714 may be configured by electronic paper, and the display unit 713 may be configured by a display device that has a quick response and displays a moving image, such as a liquid crystal display device or an organic light emitting display device.

  The housing 711 and the housing 712 are connected by a shaft portion 715, and can be opened and closed with the shaft portion 715 as an axis. The housing 711 includes a power switch 716, operation keys 717, speakers 718, and the like. At least one of the housing 711 and the housing 712 is provided with the semiconductor device described in the above embodiment. Therefore, an electronic book terminal with low power consumption is realized.

  In addition, by providing a secondary battery in each of the housing 711 and the housing 712, for example, as illustrated in the right diagram of FIG. For example, a communication device that can be connected to a mobile phone line and a device that conforms to a short-range wireless communication standard (for example, wireless LAN or Bluetooth) are provided in the housing 712, and a short-range wireless communication device is provided in the housing 711. It is good also as a structure to provide. In this case, data received by the housing 712 from the mobile phone line is transferred to the housing 711 according to the short-range wireless communication standard. Data input from the housing 711 is transmitted to the housing 712 according to the short-range wireless communication standard, and is transmitted from the housing 712 to the mobile phone line. That is, the housing 712 functions as a wireless modem.

  When the distance between the housing 711 and the housing 712 is long and communication is unintentionally interrupted (or is expected to be interrupted), both emit an alarm sound or a message is displayed on the display unit 713. If it is configured to display, the risk of losing these is reduced.

  In such a method of use, for example, the housing 712 is usually put in a bag, and on the other hand, the housing 711 is held in a hand or placed in a position where it can be easily taken out (for example, a pocket of clothes). Various operations can be executed with the housing 711. For example, part or all of the data can be stored in the housing 712 and transmitted to the housing 712 according to the short-range wireless communication standard as needed, so that the data can be viewed or viewed on the housing 712.

  FIG. 23C illustrates a smartphone. A housing 721 is provided with a display portion 722, a speaker 723, a microphone 724, an operation button 725, and the like. In the housing 721, the semiconductor device described in any of the above embodiments is provided. Therefore, a smartphone is realized.

  FIG. 23D illustrates a bracelet display device, which includes a housing 731, a display portion 732, and the like. In the housing 731, the semiconductor device described in any of the above embodiments is provided. Therefore, a bracelet type display device with low power consumption is realized.

(Embodiment 5)

  In this embodiment, as an example to which the semiconductor device functioning as the AD converter described in the above embodiment can be applied, a wireless sensor will be described as an example. The wireless sensor is called an RF (Radio Frequency) sensor or the like.

  Note that the wireless sensor has a function of receiving a wireless signal from the wireless communication device and transmitting data obtained by the sensor circuit to the wireless communication device. Note that the wireless communication device only needs to be a device that can transmit and receive wireless signals. Examples of the wireless communication device include an interrogator, a smart meter, a mobile phone, a personal computer, or a wireless terminal that collects data.

  The wireless sensor is preferably a passive wireless sensor that drives a received wireless signal as power. Since the passive wireless sensor does not include a secondary battery, the passive wireless sensor can be downsized and the degree of freedom of installation can be increased. In addition, you may incorporate the secondary battery which produces | generates electric power based on the received radio signal and can be charged. The semiconductor device of one embodiment of the present invention can be driven with extremely low power by using a transistor including an oxide semiconductor in a channel formation region. Since the power required for operation is low, the wireless sensor can be driven without mounting a secondary battery. Therefore, the wireless sensor of one embodiment of the present invention can be a passive wireless sensor.

  The frequency band of the radio signal may be appropriately selected based on laws and regulations, such as a 135 kHz long wave band, a 13.56 MHz short wave band, a 900 MHz UHF band, a 2.45 GHz microwave band, and the like. Can be used. The antenna structure of the wireless sensor may be selected in accordance with the frequency band of the wireless signal.

<Block diagram of wireless sensor>
FIG. 24 is a block diagram of the wireless sensor 400. Wireless sensors are roughly classified into an antenna 401 and an integrated circuit portion 402 (also referred to as an IC portion or a circuit portion).

  The antenna 401 has a function of transmitting / receiving a signal to / from a terminal such as an external interrogator using a wireless signal as an electrical signal or an electrical signal as a wireless signal. A plurality of antennas may be provided according to the frequency band of the radio signal carrying the signal. The radio signal is a modulated carrier wave. The modulation method is, for example, analog modulation or digital modulation, and any one of amplitude modulation, phase modulation, frequency modulation, and spread spectrum may be used.

  The integrated circuit portion 402 includes a circuit that operates based on a voltage generated by receiving a wireless signal and an electrical signal. The integrated circuit portion 402 includes a circuit that transmits an electric signal obtained by operating the circuit through the antenna 401.

  The integrated circuit unit 402 includes, as an example, a rectifier circuit 403, a demodulation circuit 404, a modulation circuit 405, a constant voltage circuit 406, a control circuit 407, an oscillation circuit 408, a memory circuit 409, an interface 410, an AD converter 411, and a sensor circuit 412. Have.

  The rectifier circuit 403 is a circuit having a function of rectifying and smoothing an electric signal from the antenna 401. The rectified and smoothed wireless signal becomes a voltage VIN having a constant potential. The voltage VIN is output to the constant voltage circuit 406.

  Note that the rectifier circuit 403 may include a protection circuit (limiter circuit). The protection circuit has a function of preventing each circuit of the integrated circuit portion 402 from being destroyed when an electric signal from the antenna 401 is a high voltage.

  The demodulation circuit 404 is a circuit having a function of demodulating an electric signal from the antenna 401. The demodulated signal is output to the control circuit 407.

  The modulation circuit 405 is a circuit having a function of modulating the electric signal generated by the control circuit 407. The modulated electrical signal is transmitted as a radio signal via the antenna 401 by a carrier wave.

  The constant voltage circuit 406 is a circuit having a function of generating a voltage based on the voltage VIN. The voltage VDD generated by the constant voltage circuit 406 is supplied to each circuit included in the integrated circuit portion 402. Note that the voltage generated by the constant voltage circuit 406 is not limited to one and may be plural.

  The control circuit 407 generates a signal input to each circuit included in the integrated circuit unit 402, a signal output from each circuit included in the integrated circuit unit 402, a signal for operating each circuit included in the integrated circuit unit 402, and the like. Thus, the circuit has a control function.

  The oscillation circuit 408 is a circuit having a function of generating a reference clock signal. As an example, the clock signal is supplied to the control circuit 407, the memory circuit 409, and the AD converter 411.

  The memory circuit 409 is a circuit having a function of holding data acquired by the sensor circuit 412 and converted from analog data to digital data by the AD converter 411. Since the supply of power to the wireless sensor 400 is performed at the timing when a wireless signal is received, it is intermittent. In this case, power supply to the memory circuit 409 is also intermittently performed. Therefore, the memory circuit 409 preferably includes a nonvolatile memory element that can retain data even when power is supplied intermittently. As the nonvolatile memory element, for example, a ferroelectric memory (FeRAM), a magnetoresistive memory (MRAM), a phase change memory (PRAM), a resistance change memory (ReRAM), etc. can be used in addition to a flash memory. . Alternatively, a circuit that holds data by holding electric charge using an off-state current of the OS transistor that is extremely low may be used as the memory element. By forming a memory element using an OS transistor, the memory element can be stacked with a transistor including a silicon layer.

  Note that the memory circuit 409 may hold a unique number (ID) of the wireless sensor 400. By giving the wireless sensor 400 a unique number, it is possible to communicate with a plurality of wireless sensors. For example, it is possible to read out only the wireless sensor data that matches the unique number for which data is desired. Further, the memory circuit 409 may be configured to write, read, and hold information included in a wireless signal received from an external interrogator or the like. In this case, conditions and the like according to the use environment of the wireless sensor 400 can be written, so that the application can be expanded.

  As the AD converter 411, the semiconductor device described in the above embodiment is used. The wireless sensor 400 including the AD converter 411 reduces power consumption by applying the semiconductor device described in the above embodiment to the AD converter 411 and does not deteriorate the performance of the AD converter such as resolution and sampling rate. A wireless sensor that does not require a dedicated high voltage generation circuit or peripheral circuit for holding analog data can be provided. The operation of the AD converter can control the supply or stop of power to each circuit as described in the above embodiment. Therefore, it is not necessary to continue supplying power to the AD converter over a period of receiving the radio signal. Therefore, the wireless sensor 400 can suppress the proportion of power consumed by the AD converter, increase the proportion of power consumed to transmit a signal from the wireless sensor 400 to the outside, and extend the communication distance. The convenience of 400 can be improved.

  Note that although a structure including a timing controller, an oscillation circuit, or the like is described as a circuit included in the semiconductor device in the above embodiment, a structure provided outside the AD converter 411 may be employed. For example, the oscillation circuit included in the AD converter 411 can be driven using the oscillation circuit 408 included in the integrated circuit portion 402 instead.

  Note that the AD converter 411 may include an input / output interface and a control circuit for inputting / outputting signals to / from the outside.

  The sensor circuit 412 is a circuit having a function of outputting various information such as thermal or electromagnetic information as analog data. The sensor circuit has various sensors. For example, temperature sensor, light sensor, gas sensor, flame sensor, smoke sensor, humidity sensor, pressure sensor, flow sensor, vibration sensor, touch sensor, voice sensor, magnetic sensor, radiation sensor, odor sensor, pollen sensor, acceleration sensor, tilt An angle sensor, a gyro sensor, an orientation sensor, a power sensor, or the like can be used.

  Note that the sensor circuit 412 may be provided outside the integrated circuit portion 402 as illustrated in FIG. The sensor circuit 412 can be formed separately from the integrated circuit portion 402. Therefore, the degree of freedom in designing the sensor circuit 412 can be increased, and the choices of data acquired by the sensor circuit can be expanded.

<Configuration example of memory circuit>
Here, a configuration example of the memory circuit 409 described above will be described with a plurality of specific examples. Note that the memory circuit 409 has a circuit configuration in which a memory element (also referred to as an OS memory) is formed using an OS transistor.

  FIG. 26 is a block diagram illustrating an example of the configuration of the memory circuit 409. The memory circuit 409 includes a control unit 360, a row decoder circuit 361, a row driver circuit 362, a column driver circuit 363, and a memory cell array 370.

  The control unit 360 is a control circuit of the memory circuit 409 and has a function of generating control signals for controlling the row decoder circuit 361, the row driver circuit 362, and the column driver circuit 363 in accordance with the access request of the logic unit 230. Have The row decoder circuit 361, the row driver circuit 362, and the column driver circuit 363 have a function of generating a drive signal for driving the memory cell array 370 in accordance with a control signal of the control unit 360.

  Note that in the case where multivalued data is stored in the memory cell array 370, a memory circuit 409_A including an AD converter 364 may be used as illustrated in FIG. As the AD converter 364, a flash type, a delta sigma type, a pipeline type, an integration type, or a successive approximation type may be used. In the case of the successive approximation type, it is preferable to use the semiconductor device described in the above embodiment mode. The wireless sensor 400 including the AD converter 411 reduces power consumption by applying the semiconductor device described in the above embodiment to the AD converter 411 and does not deteriorate the performance of the AD converter such as resolution and sampling rate. A wireless sensor that does not require a dedicated high voltage generation circuit or peripheral circuit for holding analog data can be provided.

  The memory cell array 370 is a circuit in which a plurality of memory cells are arranged in an array. FIG. 28 is a circuit diagram showing an example of the configuration of the memory cell array 370. FIG. 28 representatively shows four memory cells 380 of [2j-1, 2k-1]-[2j, 2k] (j and k are integers of 1 or more).

  Memory cell 380 includes transistors M70 to M72 and a capacitor C70. Here, the transistor M70 is an OS transistor and is an n-channel transistor. Transistors M71 and M72 are Si transistors and are p-channel transistors. The node FN is a data storage portion of the memory cell array 370 that holds data as electric charges, and corresponds to the gate of the transistor M72 in this example.

  Note that M71 and M72 may be n-channel transistors. An example of a circuit diagram of the memory cell array in this case is shown in FIG. When M71 and M72 are n-channel transistors, the wiring CWL connected to the capacitor C70 can be eliminated and the wiring C can be connected. A circuit diagram in this case is shown in FIG. In the memory circuit 373 illustrated in FIG. 32, the wiring CWL can be omitted; thus, the circuit area can be reduced.

  The memory cell array 370 is provided with wirings (WWL, RWL, CWL, SL, WBL, RBL) corresponding to the arrangement of the memory cells 380. Memory cell 380 is connected to these wirings in the corresponding column and row. A wiring BGL is provided as a common wiring for the memory cell array 370. The back gate of the transistor M70 of the memory cell 380 is connected to the wiring BGL.

  The wiring WWL functions as a writing word line, and the wiring RWL functions as a reading word line, and each is connected to the row driver circuit 362. The wiring CWL functions as a wiring that supplies a voltage applied to the capacitor C70.

  The wiring SL functions as a source line and is provided every two columns. The wiring WBL functions as a write bit line, and is a wiring through which memory data to be written to the memory cell 380 is supplied from the column driver circuit 363. The wiring RBL functions as a read bit line, and is a wiring through which memory data read from the memory cell 380 is output. The wiring SL, the wiring WBL, and the wiring RBL are connected to the column driver circuit 363.

  A clocked inverter CINV is connected to the output of the wiring RBL. The clocked inverter CINV is provided because the voltage level of the signal read from the wiring RBL is opposite to the high level and the low level with respect to the voltage level of the written data. In the example of FIG. 28, if the voltage of written data is low level, the voltage of RBL becomes high level, and if the voltage of written data is high level, the voltage of RBL becomes low level. The wiring OE and the wiring OEB are wirings for supplying a signal for controlling the output signal of the clocked inverter CINV. An output signal (memory data) of the clocked inverter CINV is output from the wiring DO.

  The capacitor C70 functions as a charge holding capacitor of the node FN. One terminal of the capacitor C70 is connected to the node FN, and the other terminal is connected to the wiring CWL. The wiring CWL is connected to the row driver circuit 362. Note that in the case where the charge of the node FN can be held by the inter-wire capacitance of the memory cell 380, the capacitor C70 and the wiring CWL are not necessarily provided.

  By turning on the transistor M70, a voltage corresponding to the data value (“0”, “1”) is applied to the node FN. Then, when the transistor M70 is turned off, the node FN is electrically floated and the memory cell 380 is in a data holding state. Since the transistor M70 is an OS transistor, the leakage current flowing between the source and the drain in the off state of the transistor M70 is extremely small. Therefore, the memory cell 380 can hold data without performing a refresh operation for a period of year (for example, about 10 years), and the memory cell 380 can be used as a nonvolatile memory cell. In addition, since VBG of the transistor M70 is positively shifted by applying VBG to the back gate, a voltage smaller than Vth can be more reliably applied to the gate of the transistor M70 in the data holding state. A memory cell 380 in which a holding error is suppressed can be obtained.

  Therefore, the memory circuit 409 can hold data even when the wireless sensor 400 is not receiving radio waves. Hereinafter, the operation of the memory cell array 370 (memory circuit 409) will be described in more detail with reference to FIG.

  Note that in the case of a memory circuit using an OS transistor in which off-state current is extremely low, a predetermined voltage may be continuously supplied to the transistor in a period in which information is held. For example, there is a case where a voltage that turns off the transistor completely is continuously supplied to the gate of the transistor. Alternatively, there is a case where a voltage at which the threshold voltage of the transistor shifts and the transistor is in a normally-off state is continuously supplied to the back gate of the transistor. In such a case, a voltage is supplied to the memory circuit during a period in which information is held, but little current flows, so that little power is consumed. Therefore, since power is hardly consumed, even if a predetermined voltage is supplied to the memory circuit, the memory circuit can be substantially expressed as non-volatile.

  FIG. 30 is a timing chart showing an example of the operation of the memory cell array 370 (memory circuit 409). Specifically, FIG. 30 shows signal waveforms input to the memory cell array 370, and the high level (“H”) and low level (“L”) voltages of wirings and nodes included in the memory cell array 370. It also shows. In this example, a constant voltage is applied to the wiring CWL, the wiring SL, and the wiring BGL.

  In the period Tp1, the memory circuit 409 is in a standby state. The standby state is a state where VIN is generated in the wireless sensor 400, and the memory circuit 409 is a data holding state. The wiring WWL, the wiring WBL, and the wiring RBL are at a low level, and the wiring RWL is at a high level. When “1” is written in the memory cell 380, the voltage of the FN is “H”, and when “0” is written, the voltage of the node FN is “L”.

  The period Tp2 is a writing operation period. Since the wiring WWL of the row in which data is written is “H”, the transistor M70 is turned on, and the period FN2 of the node FN is a writing operation period. Since the wiring WWL of the row in which data is written becomes “H”, the transistor M70 is turned on and the node FN is connected to the wiring WBL. When “1” is written, the wiring WBL becomes “H”, so that the node FN also becomes “H”. On the other hand, when “0” is written, since the wiring WBL is “L”, the node FN is also “L”. When the wiring WWL is set to “L” and the transistor M70 is turned off, the data writing operation is completed, and the memory cell 380 enters a standby state.

  In the period Tp3 (standby period), the transistor M70 is turned off from on, so that the voltage of the node FN decreases by the threshold voltage of the transistor M70. As described above, by applying the negative voltage VBG to the back gate, the Vth of the transistor M70 is positively shifted. Therefore, the leakage current becomes extremely small, and the node FN has a yearly period (for example, 10 years). Degree), it is possible to hold a voltage recognized as “1”.

  The period Tp4 is a read operation period. The wiring RWL of the row from which data is read becomes “L”, and the transistor M71 of that row is turned on. The wiring RWL in the other row remains “H”. When “1” is stored in the memory cell 380, the transistor M72 is in an off state, and thus the wiring RBL remains “L”. When “0” is stored, the transistor M72 is also turned on, so that the wiring RBL is connected to the wiring SL by the transistors M71 and M72, so that the voltage level becomes “H”. The signal read out to the wiring RBL is inverted in voltage level by the inverter CINV and output to the wiring DO.

  In the period Tp5, the memory circuit 409 is in a standby state, and the voltage levels of the node FN and the wiring are similar to those in the period Tp1.

  FIG. 31 shows another configuration example of the memory cell array. A memory cell array 372 illustrated in FIG. 31 is a modification of the memory cell array 370. The memory cell array 372 is different from the memory cell array 370 in that the wiring WBL and the wiring RBL are shared and configured by one wiring BL. That is, in the example of FIG. 28, two bit lines are provided for writing and reading, and in the example of FIG. 31, only one bit line is provided.

  FIG. 32 is a timing chart showing an operation example of the memory cell array 372. As shown in FIG. 32, the memory cell array 372 can also be driven in the same manner as the memory cell array 370. The wiring BL functions as both the wiring WBL and the wiring RBL. In the write operation period (T2), when “1” is written to the memory cell 380, the wiring BL is “H”, and when “0” is written, the wiring BL is “L”. Further, in the reading operation period (T4), when “1” is stored in the memory cell 380, the transistor M72 is in an off state; thus, the wiring BL remains “L”. When “0” is stored, the transistor M72 is also turned on, so that the wiring BL is connected to the wiring SL by the transistors M71 and M72, so that the voltage level becomes “H”. The signal read out to the wiring BL is inverted in logic value by the clocked inverter CINV and output to the wiring DO.

<Application examples of wireless sensors>
Next, application examples of a wireless sensor to which a semiconductor device is applied will be described with reference to FIGS.

  FIG. 33A is a schematic diagram of a wireless sensor. A wireless sensor 800 illustrated in FIG. 33A includes an antenna 801, an integrated circuit portion 802, and a sensor circuit 805.

  The antenna 801 may have any size and shape that meets the purpose within the range defined by the Radio Law. For example, a dipole antenna, a patch antenna, a loop antenna, a Yagi antenna, or the like can be used.

  The integrated circuit portion 802 includes a circuit 803 including a Si transistor and an OS transistor, and a terminal portion 804 for connecting to an antenna. The circuit 803 is formed through a pre-process for forming a Si transistor and an OS transistor. The terminal portion 804 is formed through a post process for forming a chip through a dicing process and a bonding process. The integrated circuit portion 802 is also referred to as a semiconductor package or an IC package. Note that the sensor circuit 805 is provided in the integrated circuit portion 802 or provided externally.

  The sensor circuit 805 has a function of outputting various information such as thermal or electromagnetic information as analog data. Depending on the size of the sensor circuit 805, the sensor circuit 805 may be provided outside the wireless sensor 800.

  FIG. 33B is a schematic diagram in which the wireless sensor 800 in FIG. 33A receives a wireless signal 811. The wireless sensor 800 generates power in response to a wireless signal 811 transmitted from the outside. The sensor circuit 805 that can operate by receiving power and the integrated circuit portion 802 in the wireless sensor 800 including the AD converter operate to supply and stop power to each circuit as necessary. As described in the above embodiment, the operation of the AD converter can control supply or stop of power to each circuit. Therefore, it is not necessary to continue supplying power to the AD converter over a period in which the wireless signal 811 is received. Therefore, the ratio of power consumed by the AD converter in the wireless sensor 800 can be suppressed, the ratio of power consumed to transmit a wireless signal from the wireless sensor 800 to the outside can be increased, and wireless communication such as extending the communication distance can be achieved. The convenience of the sensor 800 can be improved.

  An application mode of such a wireless sensor can be described with reference to a schematic diagram shown in FIG. For example, the wireless sensor 800 is attached to the article 821 or installed inside, and the wireless signal 811 is transmitted from the external interrogator 822. The wireless sensor 800 that has received the wireless signal 811 can acquire information such as temperature and transmit it to the interrogator 822 without touching the article 821 by the sensor. As described above, since power consumption for converting an analog potential obtained by a sensor into a digital signal in an AD converter can be suppressed, it is possible to extend use of the communication distance and improve convenience.

  Another application form of the wireless sensor can be described with reference to a schematic diagram shown in FIG. For example, the wireless sensor 800 is embedded in the tunnel wall surface, and the wireless signal 811 is transmitted from the outside. The wireless sensor 800 that has received the wireless signal 811 can acquire and transmit information on the tunnel wall surface by the sensor. As described above, since power consumption for converting an analog potential obtained by a sensor into a digital signal in an AD converter can be suppressed, it is possible to extend use of the communication distance and improve convenience. Therefore, information in the tunnel wall surface can be obtained without direct contact.

  Another application form of the wireless sensor can be described with reference to a schematic diagram shown in FIG. For example, the wireless sensor 800 is embedded in the wall surface of a bridge column, and a wireless signal 811 is transmitted from the outside. The wireless sensor 800 that has received the wireless signal 811 can acquire and transmit information in the bridge column by the sensor. As described above, since power consumption for converting an analog potential obtained by a sensor into a digital signal in an AD converter can be suppressed, it is possible to extend use of the communication distance and improve convenience. Therefore, information in the bridge column can be acquired without direct contact.

  Another application form of the wireless sensor can be described with reference to a schematic diagram shown in FIG. For example, the wireless sensor 800 is attached to the human body using an adhesive pad or the like, and the wireless signal 811 is transmitted from the interrogator 822. The wireless sensor 800 that has received the wireless signal 811 can acquire information such as biological information by transmitting a signal to the electrode 831 or the like attached to the human body via the wiring 832 and transmit the signal. The acquired information can be confirmed on the display unit 833 of the interrogator 822. As described above, since power consumption for converting an analog potential obtained by a sensor into a digital signal in an AD converter can be suppressed, it is possible to extend use of the communication distance and improve convenience. Therefore, it is possible to acquire the biological information of the human body without directly contacting it.

(Embodiment 6)
In this embodiment, structural examples of the OS transistors described in the above embodiments are described.

<Structure Example 1 of Transistor>
37A to 37D are a top view and a cross-sectional view of the transistor 600. FIG. 37A is a top view, and a cross section in the direction of dashed-dotted line Y1-Y2 in FIG. 37A corresponds to FIG. 37B, and is in the direction of dashed-dotted line X1-X2 in FIG. A cross section corresponds to FIG. 37C, and a cross section in the direction of dashed-dotted line X3-X4 in FIG. 37A corresponds to FIG. Note that in FIGS. 37A to 37D, some elements are enlarged, reduced, or omitted for clarity of illustration. The direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line X1-X2 may be referred to as a channel width direction.

  Note that the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed , The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width is, for example, that a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed. The length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of a channel region formed on a semiconductor side surface of a semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

  By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

  Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW : Surrounded Channel Width) ”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

  Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

  The transistor 600 includes a substrate 640, an insulating film 651 over the substrate 640, a conductive film 674 formed over the insulating film 651, an insulating film 656 formed over the insulating film 651 and the conductive film 674, and an insulating film 656. An insulating film 652 formed over the insulating film 652, a stack of the first semiconductor 661 and the second semiconductor 662 formed in that order, a conductive film 671 and a conductive film 672 in contact with the top surface of the semiconductor 662; , A semiconductor 663, a semiconductor 662, a conductive film 671, a third semiconductor 663 in contact with the conductive film 672, an insulating film 653 and a conductive film 673 over the semiconductor 663, an insulating film 654 over the conductive film 673 and the insulating film 653, An insulating film 655 is provided over the insulating film 654. Note that the first semiconductor 661, the second semiconductor 662, and the third semiconductor 663 are collectively referred to as a semiconductor 660.

  The conductive film 671 functions as a source electrode of the transistor 600. The conductive film 672 functions as a drain electrode of the transistor 600.

  The conductive film 673 functions as the first gate electrode of the transistor 600.

  The insulating film 653 functions as a first gate insulating film of the transistor 600.

  The conductive film 674 functions as the second gate electrode of the transistor 600.

  The insulating film 656 and the insulating film 652 function as a second gate insulating film of the transistor 600.

  The conductive film 673 and the conductive film 674 may be supplied with the same potential or different potentials. Further, the conductive film 674 can be omitted depending on circumstances.

  As shown in FIG. 37C, a side surface of the semiconductor 662 is surrounded by a conductive film 673. With the above structure, the semiconductor 662 can be electrically surrounded by the electric field of the conductive film 673 (the structure of the transistor that electrically surrounds the semiconductor by the electric field of the conductive film (gate electrode) is increased to the surrounded channel (s). -Channel) structure). Therefore, a channel may be formed in the entire semiconductor 662 (bulk). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current during conduction (on-current) can be increased. Further, the s-channel structure can provide a transistor that can operate at high frequency.

  The s-channel structure can be said to be a structure suitable for a semiconductor device that requires a miniaturized transistor such as an LSI (Large Scale Integration) because a high on-state current can be obtained. Since a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor has a region in which a channel length is preferably greater than or equal to 1 nm and less than or equal to 500 nm, more preferably greater than or equal to 3 nm and less than or equal to 200 nm, further preferably greater than or equal to 5 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than 60 nm, and even more preferably greater than or equal to 10 nm and less than 30 nm. . For example, the transistor has a region where the channel width is preferably greater than or equal to 10 nm and less than 10 μm, more preferably greater than or equal to 10 nm and less than 1 μm, further preferably greater than or equal to 10 nm and less than 500 nm, further preferably greater than or equal to 10 nm and less than 200 nm, and even more preferably greater than or equal to 10 nm and less than 100 nm. .

  The s-channel structure can be said to be a structure suitable for a transistor that requires high-frequency operation because a high on-state current can be obtained. The semiconductor device including the transistor can be a semiconductor device that can operate at high frequency.

  The insulating film 651 has a function of electrically separating the substrate 640 and the conductive film 674.

  The insulating film 652 preferably contains an oxide. In particular, an oxide material from which part of oxygen is released by heating is preferably included. It is preferable to use an oxide containing oxygen in excess of that in the stoichiometric composition. Part of oxygen is released by heating from the oxide film containing oxygen in excess of the stoichiometric composition. Oxygen released from the insulating film 652 is supplied to the semiconductor 660 which is an oxide semiconductor, so that oxygen vacancies in the oxide semiconductor can be reduced. As a result, variation in electrical characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than that in the stoichiometric composition is converted into oxygen atoms at a surface temperature of 100 ° C. or more and 700 ° C. or less by, for example, TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has an oxygen desorption amount of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The substrate temperature during the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  The insulating film 656 has a function of preventing oxygen contained in the insulating film 652 from being combined with a metal contained in the conductive film 674 and reducing oxygen contained in the insulating film 652.

  The insulating film 654 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. By providing the insulating film 654, diffusion of oxygen from the semiconductor 660 to the outside and entry of hydrogen, water, and the like into the semiconductor 660 from the outside can be prevented.

  Next, semiconductors applicable to the semiconductor 661, the semiconductor 662, the semiconductor 663, and the like are described.

The transistor 600 preferably has a low current (off-state current) flowing between the source and the drain in the non-conduction state. Here, the low off-state current means that at room temperature, the voltage between the source and the drain is 10 V, and the standardized off-current per channel width of 1 μm is 10 × 10 ⁻²¹ A or less. As such a transistor with low off-state current, a transistor including an oxide semiconductor as a semiconductor can be given.

  The semiconductor 662 is an oxide semiconductor containing indium (In), for example. For example, when the semiconductor 662 contains indium, the carrier mobility (electron mobility) increases. The semiconductor 662 preferably contains the element M. The element M is preferably aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), or the like. Other elements applicable to the element M include boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo ), Lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), and the like. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 662 preferably contains zinc (Zn). An oxide semiconductor may be easily crystallized when it contains zinc.

  Note that the semiconductor 662 is not limited to the oxide semiconductor containing indium. The semiconductor 662 may be, for example, an oxide semiconductor containing zinc, an oxide semiconductor containing zinc, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide.

  For the semiconductor 662, for example, an oxide with a wide energy gap is used. The energy gap of the semiconductor 662 is, for example, not less than 2.5 eV and not more than 4.2 eV, preferably not less than 2.8 eV and not more than 3.8 eV, more preferably not less than 3 eV and not more than 3.5 eV.

  The semiconductor 662 is preferably a CAAC-OS film described later.

  For example, the semiconductor 661 and the semiconductor 663 are oxide semiconductors including one or more elements other than oxygen included in the semiconductor 662 or two or more elements. Since the semiconductor 661 and the semiconductor 663 are composed of one or more elements other than oxygen constituting the semiconductor 662 or two or more elements, an interface state at the interface between the semiconductor 661 and the semiconductor 662 and the interface between the semiconductor 662 and the semiconductor 663 is used. The position is difficult to form.

  Note that when the semiconductor 661 is an In-M-Zn oxide and the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is less than 25 atomic%. , M is higher than 75 atomic%. In the case where the semiconductor 661 is formed by a sputtering method, a sputtering target that satisfies the above composition is preferably used. For example, In: M: Zn = 1: 3: 2 is preferable.

  In the case where the semiconductor 662 is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably higher than 25 atomic%, M is lower than 75 atomic%, and more preferably In is higher than 34 atomic%. High, and M is less than 66 atomic%. In the case where the semiconductor 662 is formed by a sputtering method, a sputtering target that satisfies the above composition is preferably used. For example, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1 is preferable. In particular, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as a sputtering target, the atomic ratio of the semiconductor 662 to be formed is In: Ga: Zn = 4: 2: 3. May be near.

  In the case where the semiconductor 663 is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably, In is less than 25 atomic%. , M is higher than 75 atomic%. Note that the semiconductor 663 may be formed using the same type of oxide as the semiconductor 661. Note that the semiconductor 661 and / or the semiconductor 663 may not contain indium in some cases. For example, the semiconductor 661 and / or the semiconductor 663 may be gallium oxide.

  Next, functions and effects of the semiconductor 660 formed by stacking the semiconductor 661, the semiconductor 662, and the semiconductor 663 will be described with reference to an energy band structure diagram in FIG. FIG. 38A is an enlarged view of the channel portion of the transistor 600 illustrated in FIG. 37B, and FIG. 38B is an energy band of the portion indicated by the chain line A1-A2 in FIG. The structure is shown. FIG. 38B illustrates an energy band structure of a channel formation region of the transistor 600.

  In FIG. 38B, Ec652, Ec661, Ec662, Ec663, and Ec653 indicate the energy at the lower end of the conduction band of the insulating film 652, the semiconductor 661, the semiconductor 662, the semiconductor 663, and the insulating film 653, respectively.

  Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also referred to as “electron affinity”) is defined as the energy gap based on the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Subtracted value. The energy gap can be measured using a spectroscopic ellipsometer. The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus.

  Since the insulating film 652 and the insulating film 653 are insulators, Ec653 and Ec652 are closer to the vacuum level (having a lower electron affinity) than Ec661, Ec662, and Ec663.

  As the semiconductor 662, an oxide having an electron affinity higher than those of the semiconductor 661 and the semiconductor 663 is used. For example, as the semiconductor 662, an oxide having an electron affinity greater than or equal to 0.07 eV and less than or equal to 1.3 eV, preferably greater than or equal to 0.1 eV and less than or equal to 0.7 eV, more preferably greater than or equal to 0.15 eV and less than or equal to 0.4 eV, compared with the semiconductors 661 and 663 Is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

  Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor 663 preferably includes indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

  At this time, when a gate voltage is applied, a channel is formed in the semiconductor 662 having high electron affinity among the semiconductors 661, 662, and 663.

  Here, in some cases, there is a mixed region of the semiconductor 661 and the semiconductor 662 between the semiconductor 661 and the semiconductor 662. Further, in some cases, there is a mixed region of the semiconductor 662 and the semiconductor 663 between the semiconductor 662 and the semiconductor 663. In the mixed region, the interface state density is low. Therefore, the stack of the semiconductor 661, the semiconductor 662, and the semiconductor 663 has a band structure in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface.

  At this time, electrons move mainly in the semiconductor 662, not in the semiconductor 661 and the semiconductor 663. As described above, when the interface state density at the interface between the semiconductor 661 and the semiconductor 662 and the interface state density at the interface between the semiconductor 662 and the semiconductor 663 are lowered, movement of electrons in the semiconductor 662 is hindered. Therefore, the on-state current of the transistor can be increased.

  The on-state current of the transistor can be increased as the factor that hinders the movement of electrons is reduced. For example, when there is no factor that hinders the movement of electrons, it is estimated that electrons move efficiently. Electron movement is inhibited, for example, even when the physical unevenness of the channel formation region is large.

  In order to increase the on-state current of the transistor, for example, the root mean square (RMS) roughness of the upper surface or the lower surface of the semiconductor 662 (formation surface, here, the semiconductor 661) in a range of 1 μm × 1 μm is set. The thickness may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The maximum height difference (also referred to as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope system SPA-500 manufactured by SII Nano Technology.

  Alternatively, for example, even when the density of defect states in a region where a channel is formed is high, the movement of electrons is inhibited.

For example, in the case where the semiconductor 662 has oxygen vacancies (also referred to as V 2 _O ), donor levels may be formed when hydrogen enters oxygen vacancy sites. The following may be referred to a state that has entered the hydrogen to oxygen vacancies in the site as V _{O H.} Since V _O H scatters electrons, it causes a reduction in the on-state current of the transistor. Note that oxygen deficient sites are more stable when oxygen enters than when hydrogen enters. Therefore, the on-state current of the transistor can be increased by reducing oxygen vacancies in the semiconductor 662 in some cases.

For example, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) at a certain depth of the semiconductor 662 or in a certain region of the semiconductor 662 is 1 × 10 ¹⁶ atoms / cm ³ or more. 2 × 10 ²⁰ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less.

  In order to reduce oxygen vacancies in the semiconductor 662, for example, there is a method in which excess oxygen contained in the insulating film 652 is moved to the semiconductor 662 through the semiconductor 661. In this case, the semiconductor 661 is preferably a layer having oxygen permeability (a layer through which oxygen passes or permeates).

  Note that in the case where the transistor has an s-channel structure, a channel is formed in the entire semiconductor 662. Accordingly, the thicker the semiconductor 662, the larger the channel region. That is, the thicker the semiconductor 662, the higher the on-state current of the transistor.

  In order to increase the on-state current of the transistor, the thickness of the semiconductor 663 is preferably as small as possible. The semiconductor 663 may have a region of, for example, less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less. On the other hand, the semiconductor 663 has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 662 where a channel is formed. Therefore, the semiconductor 663 preferably has a certain thickness. The semiconductor 663 may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more, for example. The semiconductor 663 preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulating film 652 and the like.

  In order to increase reliability, the semiconductor 661 is preferably thick and the semiconductor 663 is preferably thin. The semiconductor 661 may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and more preferably 60 nm or more. By increasing the thickness of the semiconductor 661, the distance from the interface between the adjacent insulator and the semiconductor 661 to the semiconductor 662 where a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the semiconductor 661 may have a region with a thickness of 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less, for example.

For example, between the semiconductor 662 and the semiconductor 661, for example, in SIMS analysis, 1 × 10 ¹⁶ atoms / cm ³ or more, preferably less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁶ atoms / cm ³ or more, The region has a silicon concentration of less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and less than 2 × 10 ¹⁸ atoms / cm ³ . Further, between SIMS 662 and 663, in SIMS, 1 × 10 ¹⁶ atoms / cm ³ or more, less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ^The region has a silicon concentration of less than ¹⁸ atoms / cm ³ , more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and less than 2 × 10 ¹⁸ atoms / cm ³ .

In addition, in order to reduce the hydrogen concentration of the semiconductor 662, it is preferable to reduce the hydrogen concentration of the semiconductor 661 and the semiconductor 663. The semiconductor 661 and the semiconductor 663 have a SIMS of 1 × 10 ¹⁶ atoms / cm ³ or more, 2 × 10 ²⁰ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more, preferably 5 × 10 ¹⁹ atoms / cm ^3. Or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ¹⁸ atoms / cm ³ or less hydrogen concentration Has a region to be In order to reduce the nitrogen concentration of the semiconductor 662, it is preferable to reduce the nitrogen concentrations of the semiconductor 661 and the semiconductor 663. The semiconductor 661 and the semiconductor 663 have a SIMS of 1 × 10 ¹⁶ atoms / cm ³ or more and less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ¹⁸ atoms / cm ³ in SIMS. Or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ¹⁷ atoms / cm ³ or less Has a region to be

  The above three-layer structure is an example. For example, a two-layer structure without the semiconductor 661 or the semiconductor 663 may be used. Alternatively, a four-layer structure including any one of the semiconductors 661, 662, and 663 as the semiconductor 663 may be provided above or below the semiconductor 661 or above or below the semiconductor 663. Alternatively, the n-layer structure includes any one of the semiconductors 661, the semiconductor 662, and the semiconductor exemplified as the semiconductor 663 in any two or more positions over the semiconductor 661, the semiconductor 661, the semiconductor 663, and the semiconductor 663. (N is an integer of 5 or more).

  As the substrate 640, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

  Further, a flexible substrate may be used as the substrate 640. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate 640 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 640. Further, the substrate 640 may have elasticity. Further, the substrate 640 may have a property of returning to its original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The thickness of the substrate 640 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate 640 is thinned, the semiconductor device can be reduced in weight. Further, by making the substrate 640 thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate 640 due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate 640 which is a flexible substrate, for example, metal, alloy, resin, glass, or fiber thereof can be used. The substrate 640 which is a flexible substrate is preferable because the deformation due to the environment is suppressed as the linear expansion coefficient is lower. As the substrate 640 which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less is used. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE). In particular, since aramid has a low coefficient of linear expansion, it is suitable for the substrate 640 that is a flexible substrate.

  As a material used for the insulating film 651a and the insulating film 651b, a material containing silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide is preferably used. Alternatively, a metal oxide such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used. Note that in this specification, an oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and a nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  Alternatively, the insulating film 651a and the insulating film 651b may be formed using silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen, nitrous oxide, or the like. Good.

  The insulating film 651a and the insulating film 651b include a sputtering method, a CVD (Chemical Vapor Deposition) method (including a thermal CVD method, a MOCVD (Metal Organic CVD) method, a PECVD (Plasma Enhanced CVD) method, and the like), MBE (Molecular Beam). Alternatively, a film may be formed by a method, an ALD (Atomic Layer Deposition) method, a PLD (Pulsed Laser Deposition) method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  In the case where a semiconductor substrate is used as the substrate 640, the insulating film 651a may be formed using a thermal oxide film.

  The conductive film 674 includes copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), Made of low resistance material such as chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) It is preferable to form a single layer or a stacked layer of a conductive film containing a single substance, an alloy, or a compound containing these as a main component. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Moreover, it is preferable to form with low resistance conductive materials, such as aluminum and copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide has a function of suppressing Cu diffusion.

  The conductive film 674 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like.

  It is preferable that the surface of the insulating film 651b be planarized by a CMP (Chemical Mechanical Polishing) method. Further, a planarization film may be used as the insulating film 651b. In that case, the planarization is not necessarily performed by the CMP method or the like. For example, an atmospheric pressure CVD method or a coating method can be used to form the planarizing film. Examples of the film that can be formed using the atmospheric pressure CVD method include BPSG (Boron Phosphorus Silicate Glass). Moreover, as a film | membrane which can be formed using the apply | coating method, HSQ (hydrogen silsesquioxane) etc. are mentioned, for example.

  Hereinafter, the insulating film 651a and the insulating film 651b are collectively referred to as an insulating film 651.

  The insulating film 656 and the insulating film 652 may be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like.

  The insulating film 656 preferably has a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. As the insulating film 656, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film may be provided instead of the nitride insulating film. Examples of the oxide insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

  The insulating film 652 preferably contains an oxide that can supply oxygen to the semiconductor 660. For example, the insulating film 652 is preferably formed using a material containing silicon oxide or silicon oxynitride. Alternatively, a metal oxide such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used.

  In order to make the insulating film 652 contain excessive oxygen, for example, the insulating film 652 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 652 after film formation to form a region containing excess oxygen, or both means may be combined.

  For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 652 that has been formed, so that a region containing excess oxygen is formed. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  Alternatively, after the insulating film 652 is formed, planarization treatment using a CMP method or the like may be performed in order to improve planarity of the upper surface.

  The semiconductor 661 and the semiconductor 662 are preferably formed successively without being exposed to the air. The semiconductor 661 and the semiconductor 662 may be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, a PLD method, an ALD method, or the like.

  For materials that can be used for the semiconductor 661 and the semiconductor 662, the description of the semiconductor 661 and the semiconductor 662 in FIGS.

  Note that in the case where an In—Ga—Zn oxide layer is formed by a MOCVD method as the semiconductor 661 and the semiconductor 662, trimethylindium, trimethylgallium, dimethylzinc, or the like may be used as a source gas. The combination of the source gases is not limited, and triethylindium or the like may be used instead of trimethylindium. Further, triethylgallium or the like may be used instead of trimethylgallium. Further, diethyl zinc or the like may be used instead of dimethyl zinc.

  Here, oxygen may be introduced into the semiconductor 661 after the semiconductor 661 is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the semiconductor 661 after film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  Heat treatment is preferably performed after the semiconductor 661 and the semiconductor 662 are formed. The heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. The atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after the semiconductor film is formed, or may be performed after the semiconductor film is processed to form the island-shaped semiconductor 661 and the semiconductor 662. By the heat treatment, oxygen is supplied from the insulating film 652 and the oxide film to the semiconductor, so that oxygen vacancies in the semiconductor can be reduced.

  The semiconductor 663, the insulating film 653, and the conductive film 673 may be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, a PLD method, an ALD method, or the like. In particular, a CVD method, preferably a plasma CVD method, is preferable because coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  The semiconductor 663 and the insulating film 653 may be etched after the conductive film 673 is formed. Etching may be performed using a resist mask, for example. Alternatively, the insulating film 653 and the semiconductor 663 may be etched using the formed conductive film 673 as a mask.

  Further, oxygen may be introduced into the semiconductor 663 after the semiconductor 663 is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the semiconductor 663 after film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  For materials that can be used for the semiconductor 663, the description of the semiconductor 663 in FIGS.

  The insulating film 653 is formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more insulating films can be used. The insulating film 653 may be a stack of the above materials. Note that the insulating film 653 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity.

  An example of a stacked structure of the insulating film 653 will be described. The insulating film 653 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

  Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Accordingly, the thickness of the insulating film 653 can be increased as compared with the case where silicon oxide is used, and thus leakage current due to tunneling current can be reduced. That is, a transistor with a small off-state current can be realized.

  The insulating film 654 preferably has a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. As the insulating film 654, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride. The insulating film 654 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  The aluminum oxide film is preferable for application to the insulating film 654 because the aluminum oxide film has a high blocking effect of preventing both the hydrogen and moisture impurities and oxygen from permeating through the film. In addition, oxygen contained in the aluminum oxide film can be diffused into the semiconductor 660.

  Heat treatment is preferably performed after the insulating film 654 is formed. Through this heat treatment, oxygen can be supplied from the insulating film 652 and the like to the semiconductor 660, so that oxygen vacancies in the semiconductor 660 can be reduced. At this time, oxygen released from the insulating film 652 is blocked by the insulating film 656 and the insulating film 654, so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the semiconductor 660 can be increased, and oxygen vacancies in the semiconductor 660 can be effectively reduced.

  The insulating film 655 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, a CVD method, preferably a plasma CVD method, is preferable because coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred. In the case where an organic insulating material such as an organic resin is used for the insulating film 655, a coating method such as a spin coating method may be used. Further, after the insulating film 655 is formed, planarization treatment is preferably performed on the top surface thereof.

  The insulating film 655 includes aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and hafnium oxide. An insulator containing one or more selected from tantalum oxide and the like can be used. The insulating film 655 can be formed using an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin. The insulating film 655 may be a stack of the above materials.

<Example 2 of transistor configuration>
In the transistor 600 illustrated in FIG. 36, after the insulating film 655 is provided over the insulating film 652 and the semiconductor 662, an opening is provided in the insulating film 655, and the semiconductor 663, the insulating film 653, and the conductive film are embedded to fill the opening. An example of forming 673 is shown. In FIG. 36, the insulating film 654 is in contact with the top surfaces of the insulating film 655 and the conductive film 673. Further, when the opening is provided in the insulating film 655, the conductive film 671 and the conductive film 672 may be formed by removing part of the conductive film to be the conductive film 671 and the conductive film 672.

<Configuration Example 3 of Transistor>
In the transistor 600 illustrated in FIGS. 37A and 37B, the semiconductor 663 and the insulating film 653 may be etched at the same time when the conductive film 673 is formed by etching. An example is shown in FIG.

  FIG. 39 shows the case where the semiconductor 663 and the insulating film 653 exist only under the conductive film 673 in FIG.

<Configuration Example 4 of Transistor>
In the transistor 600 illustrated in FIG. 37, the conductive film 671 and the conductive film 672 may be in contact with the side surface of the semiconductor 661 and the side surface of the semiconductor 662. An example is shown in FIG.

  FIG. 40 illustrates the case where the conductive film 671 and the conductive film 672 are in contact with the side surface of the semiconductor 661 and the side surface of the semiconductor 662 in FIG.

<Structure Example 5 of Transistor>
In the transistor 600 illustrated in FIGS. 37A and 37B, the conductive film 671 may have a stacked structure of a conductive film 671a and a conductive film 671b. Alternatively, the conductive film 672 may have a stacked structure of a conductive film 672a and a conductive film 672b. An example is shown in FIG.

  FIG. 41 illustrates the case where the conductive film 671 has a stacked structure of conductive films 671a and 671b and the conductive film 672 has a stacked structure of conductive films 672a and 672b in FIG.

  As the conductive film 671b and the conductive film 672b, for example, a transparent conductor, an oxide semiconductor, a nitride semiconductor, or an oxynitride semiconductor may be used. Examples of the conductive film 671b and the conductive film 672b include a film containing indium, tin and oxygen, a film containing indium and zinc, a film containing indium, tungsten and zinc, a film containing tin and zinc, and a film containing zinc and gallium. A film containing zinc and aluminum, a film containing zinc and fluorine, a film containing zinc and boron, a film containing tin and antimony, a film containing tin and fluorine, or a film containing titanium and niobium may be used. Alternatively, these films may contain hydrogen, carbon, nitrogen, silicon, germanium, or argon.

  The conductive films 671b and 672b may have a property of transmitting visible light. Alternatively, the conductive film 671b and the conductive film 672b may have a property of not transmitting visible light, ultraviolet light, infrared light, or X-rays by reflection or absorption. By having such a property, a change in electrical characteristics of the transistor due to stray light may be suppressed in some cases.

  The conductive films 671b and 672b may preferably be formed using a layer that does not form a Schottky barrier with the semiconductor 662 or the like. Thus, the on-state characteristics of the transistor can be improved.

  As the conductive film 671a and the conductive film 672a, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, A conductor including one or more of silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy film or a compound film, and includes a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, titanium and nitrogen. A conductor or the like may be used.

  Note that there may be a case where it is preferable that the conductive films 671b and 672b be higher resistance than the conductive films 671a and 672a. In some cases, the conductive film 671b and the conductive film 672b each preferably have a lower resistance than the channel of the transistor. For example, the resistivity of the conductive films 671b and 672b may be 0.1 Ωcm to 100 Ωcm, 0.5 Ωcm to 50 Ωcm, or 1 Ωcm to 10 Ωcm. By setting the resistivity of the conductive films 671b and 672b in the above range, electric field concentration at the boundary between the channel and the drain can be reduced. Therefore, variation in electrical characteristics of the transistor can be reduced. In addition, the punch-through current due to the electric field generated from the drain can be reduced. Therefore, saturation characteristics can be improved even in a transistor with a short channel length. Note that in a circuit configuration in which the source and the drain are not interchanged, it may be preferable to dispose only one of the conductive films 671b and 672b (for example, the drain side).

<Structure Example 6 of Transistor>
42A and 42B are a top view and a cross-sectional view of the transistor 680, respectively. FIG. 42A is a top view, and a cross section in the direction of dashed-dotted line AB in FIG. 42A corresponds to FIG. Note that in FIGS. 42A and 42B, some elements are illustrated in an enlarged, reduced, or omitted manner for clarity. In addition, the direction of the alternate long and short dash line AB may be referred to as a channel length direction.

  A transistor 680 illustrated in FIG. 42B includes a conductive film 689 functioning as a first gate, a conductive film 688 functioning as a second gate, a semiconductor 682, a conductive film 683 functioning as a source and a drain, and a conductive film. A film 684, an insulating film 681, an insulating film 685, an insulating film 686, and an insulating film 687 are included.

  The conductive film 689 is provided over the insulating surface. The conductive film 689 and the semiconductor 682 overlap with each other with the insulating film 681 interposed therebetween. The conductive film 688 and the semiconductor 682 overlap with each other with the insulating film 685, the insulating film 686, and the insulating film 687 interposed therebetween. The conductive films 683 and 684 are connected to the semiconductor 682.

  For details of the conductive films 689 and 688, the description of the conductive films 673 and 674 illustrated in FIGS.

  The conductive films 689 and 688 may be supplied with different potentials or can be supplied with the same potential at the same time. In the transistor 680, the conductive film 688 functioning as the second gate electrode is provided, so that the threshold value can be stabilized. Note that the conductive film 688 may be omitted depending on circumstances.

  For the details of the semiconductor 682, the description of the semiconductor 662 illustrated in FIG. Further, the semiconductor 682 may be a single layer or a stacked layer of a plurality of semiconductor layers.

  For the details of the conductive films 683 and 684, the description of the conductive films 671 and 672 illustrated in FIGS.

  For the details of the insulating film 681, the description of the insulating film 653 illustrated in FIGS.

  Note that FIG. 42B illustrates the case where the insulating films 685 to 687 are sequentially stacked over the semiconductor 682, the conductive film 683, and the conductive film 684; The insulating film provided over the films 683 and 684 may be a single layer or a stack of a plurality of insulating films.

  In the case where an oxide semiconductor is used for the semiconductor 682, the insulating film 686 is an insulating film that contains oxygen in excess of the stoichiometric composition and has a function of supplying part of the oxygen to the semiconductor 682 by heating. It is desirable. However, in the case where the insulating film 686 is directly provided over the semiconductor 682 and the semiconductor 682 is damaged when the insulating film 686 is formed, the insulating film 685 is formed of the semiconductor 682 and the insulating film 686 as illustrated in FIG. It is good to provide in between. The insulating film 685 is desirably an insulating film that has less damage to the semiconductor 682 during the formation than the insulating film 686 and has a function of transmitting oxygen. Note that the insulating film 685 is not necessarily provided as long as the insulating film 686 can be directly formed over the semiconductor 682 while suppressing damage to the semiconductor 682.

  For example, the insulating film 686 and the insulating film 685 are preferably formed using a material containing silicon oxide or silicon oxynitride. Alternatively, a metal oxide such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used.

  The insulating film 687 desirably has a blocking effect for preventing diffusion of oxygen, hydrogen, and water. Alternatively, the insulating film 687 desirably has a blocking effect that prevents diffusion of hydrogen and water.

  The insulating film exhibits a higher blocking effect as it is denser and denser, and as it is chemically stable with fewer dangling bonds. Examples of the insulating film that exhibits a blocking effect to prevent diffusion of oxygen, hydrogen, and water include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride. Can be formed. For example, silicon nitride, silicon nitride oxide, or the like can be used as the insulating film exhibiting a blocking effect for preventing diffusion of hydrogen and water.

  In the case where the insulating film 687 has a blocking effect for preventing diffusion of water, hydrogen, and the like, it is possible to prevent the resin in the panel and impurities such as water and hydrogen existing outside the panel from entering the semiconductor 682. In the case where an oxide semiconductor is used for the semiconductor 682, part of water or hydrogen that has entered the oxide semiconductor becomes an electron donor (donor); therefore, the insulating film 687 having the above-described blocking effect is used, whereby the threshold value of the transistor 680 is obtained. The voltage can be prevented from shifting due to the generation of donors.

  In the case where an oxide semiconductor is used for the semiconductor 682, the insulating film 687 has a blocking effect for preventing diffusion of oxygen, so that oxygen from the oxide semiconductor can be prevented from diffusing to the outside. Accordingly, oxygen vacancies serving as donors in the oxide semiconductor are reduced, so that the threshold voltage of the transistor 680 can be prevented from being shifted due to generation of donors.

(Embodiment 7)
In this embodiment, a semiconductor device having a display portion which is one embodiment of the present invention will be described with reference to FIGS.

  The semiconductor device 5 described in this embodiment has a function of displaying data acquired by a sensor on a display portion in combination with the semiconductor device 100 described in the above embodiment.

  FIG. 43A is a circuit block diagram of the semiconductor device 5 according to one embodiment of the present invention.

  The semiconductor device 5 includes an antenna 50, an RF device 60, a power control circuit 55, a display unit 61, and a battery 59. The RF device 60 includes a power supply circuit 51, an analog circuit 52, a memory 53, and a logic circuit 54.

  The antenna 50 has a function of transmitting / receiving a signal to / from an external device such as a reader using the radio signal RF as an electrical signal or the electrical signal as a radio signal RF. A plurality of antennas 50 may be provided according to the frequency band of the radio signal RF. The radio signal RF is a modulated carrier wave. The modulation method is, for example, analog modulation or digital modulation, and any one of amplitude modulation, phase modulation, frequency modulation, and spread spectrum may be used.

  The frequency band of the radio signal RF may be appropriately selected based on laws and regulations. For example, a long wave band of 135 kHz band, a short wave band of 13.56 MHz band, a UHF band of 900 MHz band, a microwave band of 2.45 GHz band, etc. Can be used. The structure of the antenna 50 may be selected according to the frequency band of the radio signal RF.

  The power supply circuit 51 is a circuit having a function of generating a voltage based on the radio signal RF. The voltage generated by the power supply circuit 51 is given to each circuit included in the semiconductor device 5. Note that the voltage generated by the power supply circuit 51 is not limited to one and may be plural.

  The analog circuit 52 has a function of modulating or demodulating the radio signal RF.

  The logic circuit 54 has a function of executing a command included in the radio signal RF. For example, according to a command, it has the function to control the light emission state of the display part 61. FIG.

  Various types of display devices can be used for the display unit 61. For example, EL elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light in response to current), electrons Emitting element, liquid crystal element, electronic ink, electrophoretic element, display element using MEMS, DMD, DMS, MIRASOL (registered trademark), IMOD element, shutter type MEMS display element, optical interference type MEMS display element, electrowetting And a light emitting element using a carbon nanotube, and the like.

  The memory 53 has a function of storing data displayed on the display unit 61. Note that as shown in FIG. 43B, wiring may be provided between the memory 53 and the logic circuit 54, and data stored in the memory 53 may be supplied to the display portion 61 through the logic circuit 54. .

  The memory 53 is preferably a non-volatile memory in order to prevent data loss even when power is supplied intermittently. In particular, the memory 53 is preferably a nonvolatile memory including the oxide semiconductor described in Embodiment 2. By using a non-volatile memory using an oxide semiconductor, the memory 53 can hold data at a high temperature. In addition, by using a nonvolatile memory including an oxide semiconductor, the memory 53 can write data with a low voltage. Further, by using a nonvolatile memory including an oxide semiconductor, the memory 53 can store not only digital data but also analog data.

  When the memory 53 stores only digital data, the memory 53 is, for example, a ferroelectric memory (FeRAM), a magnetoresistive memory (MRAM), a phase change memory (PRAM), a resistance change type memory in addition to a flash memory. (ReRAM) or the like can be used.

  The battery 59 may be a secondary battery or an electric double layer capacitor that can be repeatedly charged and discharged. In particular, the battery 59 is preferably charged with the power of the radio signal RF.

  The battery 59 may be a primary battery that performs only discharging.

  The power control circuit 55 has a function of controlling power supply. For example, when the intensity of the radio signal RF is strong, the power control circuit 55 has a function of charging the battery 59. Further, when the intensity of the radio signal RF is weak, the battery 59 has a function of supplementing the power of the RF device 60.

  When the semiconductor device 5 is configured as described above, the semiconductor device 5 can drive a circuit that cannot be driven only by the power of the radio signal RF, such as the display unit 61.

  Further, by configuring the semiconductor device 5 as described above, the semiconductor device 5 can operate even during a period in which the radio signal RF is not supplied. In addition, the semiconductor device 5 can display information on the display unit 61 even during a period in which the wireless signal RF is not supplied. Further, the semiconductor device 5 can efficiently charge and discharge the battery 59 and can operate for a long period of time.

  Next, an example of a display device including the semiconductor device 5 will be described with reference to FIG.

  FIG. 44 shows an external view of the display device 70. The display device 70 includes a circuit board 71, a battery 72, a solar cell 73, a display unit 74, and a support body 75.

  The circuit board 71 includes an antenna 50, an RF device 60, and a power control circuit 55.

  The solar cell 73 has a function of charging the battery 72. The display device 70 has a function of charging the battery 72 with the solar cell 73 even when no wireless signal is supplied.

  The support 75 is preferably made of a thin film material having flexibility. Since the support body 75 has flexibility, for example, the display device 70 can be stretched on a wall or the like. Further, the display device 70 can be suspended from the ceiling or the like.

  As the support body 75, for example, plastic, stainless steel still foil, tungsten foil, a flexible substrate, a laminated film, a substrate film, paper containing a fibrous material, wood, or the like may be used. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, and papers.

  The display device 70 has a function of displaying image information supplied from the outside on the display unit 74 by a wireless signal. Therefore, the display device 70 is. It is possible to easily update the image information.

  For example, when the display device 70 is used as a street poster, the display device 70 receives a radio signal emitted from a mobile terminal possessed by a passerby such as a smartphone, and displays an advertisement that matches the preference of the person. The display unit 74 has a function of displaying.

(Additional notes regarding the description of this specification etc.)
The above embodiment and description of each component in the embodiment will be added below.
<Supplementary Note on One Aspect of the Invention described in Embodiment>

  The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In addition, in the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined as appropriate.

  Note that the content described in one embodiment (may be a part of content) is different from the content described in the embodiment (may be a part of content) and / or one or more other contents. Application, combination, replacement, or the like can be performed on the contents described in the embodiment (may be part of the contents).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part thereof) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

  Further, although one embodiment of the present invention has been described in each embodiment, one embodiment of the present invention is not limited thereto. For example, in Embodiment Mode 1 as an embodiment of the present invention, an example in which the analog potential is held in the sample hold circuit 101 using the transistor 112 and the power supply of the buffer circuit 111 or the like is stopped has been described. One embodiment is not limited to this. A structure in which an analog potential is held in the sample-and-hold circuit 101 and the power source of the buffer circuit 111 or the like is stopped without using the transistor 112, for example, according to circumstances, may be an embodiment of the present invention. Alternatively, a configuration in which the power source of the buffer circuit 111 or the like is not stopped may be used as one embodiment of the present application depending on the situation.

<Additional notes regarding the description explaining the drawings>

  In this specification and the like, terms indicating arrangement such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. The positional relationship between the components appropriately changes depending on the direction in which each component is drawn. Therefore, the phrase indicating the arrangement is not limited to the description described in the specification, and can be appropriately rephrased depending on the situation.

  Further, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below, and is in direct contact with each other. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

  Further, in the present specification and the like, in the block diagram, the constituent elements are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved over a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

  In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

  In the drawings, some components may be omitted from the top view (also referred to as a plan view or a layout view) or a perspective view in order to clarify the drawing.

<Additional notes on paraphrased descriptions>

  In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground potential (ground potential), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  Note that in this specification and the like, a structure in which electric charge is held is illustrated with a circuit structure including one OS transistor and one capacitor, but this embodiment is not limited thereto. A circuit configuration including two or more transistors and two or more capacitor elements can hold charges, and a separate wiring may be further formed to have various circuit configurations.

<Notes on the definition of words>
In the following, the definition of the phrase that was desired to be mentioned in the above embodiment will be described.
<< About the switch >>
In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

  Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.

  Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state where the source and the drain of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source and drain of the transistor can be regarded as being electrically cut off. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

  An example of a mechanical switch is a switch using MEMS (micro electro mechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

<< About channel length >>
In this specification and the like, the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate overlap with each other, or a channel is formed. This is the distance between the source and drain in the region.

  Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

<< About channel width >>
In this specification and the like, the channel width refers to, for example, a source in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed And the length of the part where the drain faces.

  Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

  By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

  Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW : Surrounded Channel Width) ”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

  Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

<< About connection >>
In this specification and the like, “A and B are connected” includes not only those in which A and B are directly connected but also those that are electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

  Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

  For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined.

  Alternatively, as another expression method, for example, “a source (or a first terminal or the like of a transistor) is electrically connected to X through at least a first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path includes a transistor source (or first terminal or the like) and a transistor drain (or second terminal or the like) through the transistor. The first connection path is a path through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path. The third connection path is connected and does not have the second connection path, and the third connection path is a path through Z2. " Or, “the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least a first connection path, and the first connection path is a second connection path. The second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is at least connected to Z2 by the third connection path. , Y, and the third connection path does not have the second connection path. Or “the source of the transistor (or the first terminal or the like) is electrically connected to X through Z1 by at least a first electrical path, and the first electrical path is a second electrical path Does not have an electrical path, and the second electrical path is an electrical path from the source (or first terminal or the like) of the transistor to the drain (or second terminal or the like) of the transistor; The drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path is a fourth electrical path. The fourth electrical path is an electrical path from the drain (or second terminal or the like) of the transistor to the source (or first terminal or the like) of the transistor. can do. Using the same expression method as those examples, by defining the connection path in the circuit configuration, the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are distinguished. The technical scope can be determined.

  In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

C70 capacitance C71 capacitance M70 transistor M71 transistor M72 transistor M73 transistor 5 semiconductor device 10 circuit 20 circuit 50 antenna 51 power supply circuit 52 analog circuit 53 memory 54 logic circuit 55 power control circuit 59 battery 60 RF device 66 photoelectric conversion element 61 display unit 70 display Device 71 Circuit board 72 Battery 73 Solar cell 74 Display unit 75 Support device 100 Semiconductor device 101 Sample hold circuit 101A Sample hold circuit 101B Sample hold circuit 102 Circuit 103 Successive comparison register 104 Digital analog conversion circuit 105 Timing controller 106 Oscillation circuit 111 Buffer circuit 112 Transistor 113 Capacitor 116 Capacitor 117 Transistor 119 Transistor 120 Inverter 21 sensor circuit 121A sensor circuit 121B sensor circuit 122 selector 131 sample hold circuit 131A sample hold circuit 131B sample hold circuit 131C sample hold circuit 135 transistor 136 transistor 137 transistor 141 transistor 153 transistor 154 transistor 166 transistor 167 resistance element 171 transistor 172 inverter circuit 173 Transistor 174 Bias voltage generation circuit 176 Transistor 181 Transistor 183 Transistor 188 Transistor 189 Resistance element 190 Capacitance element 193 Capacitance element 194 Selector 195 Selector 196 Selector 197 Transistor 198 Inverter circuit 211 Transistor 212 Capacitance element 216 Capacitance element 217 Transistor 221 Register 222 Register 230 Logic portion 231 Shaded portion 241 Input terminal 242 Input terminal 251 Output terminal 260 FET layer 261 FET layer 270 Substrate 271 Well 272 Channel formation region 273 Low concentration impurity region 274 High concentration impurity region 275 Conductive region 276 Gate Insulating film 277 Gate electrode 278 Side wall insulating film 279 Side wall insulating film 280 Conductive layer 281 Conductive layer 282 Conductive layer 291 Insulating layer 293 Insulating layer 360 Control unit 361 Row decoder circuit 362 Row driver circuit 363 Column driver circuit 364 AD converter 370 Memory cell array 372 Memory cell array 373 Memory circuit 380 Memory cell 400 Wireless sensor 401 Antenna 402 Integrated circuit unit 403 Current circuit 404 Demodulation circuit 405 Modulation circuit 406 Constant voltage circuit 407 Control circuit 408 Oscillation circuit 409 Memory circuit 409_A Memory circuit 410 Interface 411 AD converter 412 Sensor circuit 600 Transistor 601 Pulse voltage output circuit 602 Current detection circuit 611 Capacitance 612 Wiring 613 Wiring 640 Substrate 651 insulating film 651a insulating film 651b insulating film 652 insulating film 653 insulating film 654 insulating film 655 insulating film 656 insulating film 660 semiconductor 661 semiconductor 662 semiconductor 663 semiconductor 671 conductive film 671a conductive film 671b conductive film 672 conductive film 672a conductive film 672b conductive Film 673 conductive film 674 conductive film 680 transistor 681 insulating film 682 semiconductor 683 conductive film 684 conductive film 685 insulating film 686 insulating film 687 insulating film 688 conductive Film 689 Conductive film 701 Case 702 Case 703a Display portion 703b Display portion 704 Selection button 705 Keyboard 711 Case 712 Case 713 Display portion 714 Display portion 715 Shaft portion 716 Power switch 717 Operation key 718 Speaker 721 Case 722 Display portion 723 Speaker 724 Microphone 725 Operation button 731 Case 732 Display unit 800 Wireless sensor 801 Antenna 802 Integrated circuit unit 803 Circuit 804 Terminal unit 805 Sensor circuit 832 Wiring 833 Display unit 1100 Layer 1200 Layer 1300 Layer 1400 Layer 1500 Insulating layer 1510 Light shielding layer 1520 Organic resin layer 1540 Microlens array 1550 Optical conversion layer 1600 Support substrate

Claims (15)

A sample-and-hold circuit and a first circuit;
The first circuit includes an amplifier;
The sample and hold circuit includes a buffer circuit, a first transistor, a second transistor, a first capacitor element, and a second capacitor element,
The channel length of the first transistor is 1 nm or more and 500 nm or less,
The first transistor includes an oxide semiconductor;
The gate capacitance of the first transistor is 0.1 μF · cm ⁻² or more and 1 μF · cm ⁻² or less,
The capacitance of the second capacitive element is not less than 0.3 times and not more than 0.7 times the gate capacitance of the first transistor,
One of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor,
One of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor,
One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
The first transistor has a function of holding electric charge in one of a source and a drain of the first transistor by being turned off,
The buffer circuit is a semiconductor device having a function of stopping supply of a power supply voltage after holding the charge in one of a source and a drain of the first transistor. A sample-and-hold circuit and a first circuit;
The first circuit has a comparator;
The sample and hold circuit includes a buffer circuit, a first transistor, a second transistor, a first capacitor element, and a second capacitor element,
The channel length of the first transistor is 1 nm or more and 500 nm or less,
The first transistor includes an oxide semiconductor;
The gate capacitance of the first transistor is 0.1 μF · cm ⁻² or more and 1 μF · cm ⁻² or less,
The capacitance of the second capacitive element is not less than 0.3 times and not more than 0.7 times the gate capacitance of the first transistor,
One of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor,
One of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor,
One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
The first transistor has a function of holding electric charge in one of a source and a drain of the first transistor by being turned off,
The buffer circuit is a semiconductor device having a function of stopping supply of a power supply voltage after holding the charge in one of a source and a drain of the first transistor. In claim 1 or claim 2,
The first circuit includes a third transistor;
One of the source and the drain of the first transistor is a semiconductor device electrically connected to the gate of the third transistor. In any one of Claim 1 thru | or 3,
The output from the buffer circuit is input to the other of the source and the drain of the first transistor,
A semiconductor device in which a signal corresponding to the charge held in one of a source and a drain of the first transistor is input to the first circuit. In any one of Claims 1 thru | or 4,
It has a digital / analog conversion circuit,
A semiconductor device to which the digital-analog converter circuit is connected to the first circuit. In claim 5,
A semiconductor device having a successive approximation register and a timing controller. A buffer circuit, a first transistor, a second transistor, and a capacitor;
The channel length of the first transistor is 1 nm or more and 500 nm or less,
The first transistor includes an oxide semiconductor;
One of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor,
One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
A first potential is applied to the other of the source and the drain of the second transistor;
The second transistor is turned on to give a first charge corresponding to the first potential to one of the source and drain of the first transistor, and then turned off to turn on the first charge. Has the function of holding
A second potential is applied to the other of the source and the drain of the first transistor;
The first transistor is turned on to give a second charge corresponding to a second potential to one of the source or drain of the first transistor, and then turned off to give the second charge. Has the function to hold,
The buffer circuit is a semiconductor device having a function of stopping supply of power supply voltage after holding the second charge. A buffer circuit, a first transistor, a second transistor, a capacitor, and a second capacitor;
The channel length of the first transistor is 1 nm or more and 500 nm or less,
The first transistor includes an oxide semiconductor;
The capacitance of the second capacitive element is not less than 0.3 times and not more than 0.7 times the gate capacitance of the first transistor,
One of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor,
One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
One of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor,
A first potential is applied to the other of the source and the drain of the second transistor;
The second transistor is turned on to give a first charge corresponding to the first potential to one of the source and drain of the first transistor, and then turned off to turn on the first charge. Has the function of holding
A second potential is applied to the other of the source and the drain of the first transistor;
Turning on the first transistor by applying a third potential to the gate of the first transistor;
A fourth potential is applied to the other electrode of the second capacitor;
A second charge corresponding to a second potential is applied to one of a source and a drain of the first transistor;
The first transistor has a function of holding the second charge by being turned off,
The buffer circuit is a semiconductor device having a function of stopping supply of power supply voltage after holding the second charge. In claim 7 or claim 8,
A semiconductor device in which a difference between the first potential and the second potential is greater than 0.1V and less than 4V. In any one of Claims 7 to 9,
The potential difference of the third potential with respect to the second potential is:
A semiconductor device having a polarity different from that of the fourth potential with respect to the second potential. In any one of Claims 7 to 10,
A semiconductor device in which a gate capacitance of the first transistor is 0.1 μF · cm ^{−2 to} 1 μF · cm ⁻² . In any one of Claims 7 to 11,
The output from the buffer circuit is input to the other of the source and the drain of the first transistor,
A semiconductor device in which a signal corresponding to the charge held in one of a source and a drain of the first transistor is input to the first circuit. In any one of Claims 7 to 12,
A semiconductor device having a digital-analog conversion circuit. In claim 13,
A semiconductor device having a successive approximation register and a timing controller. A semiconductor device according to any one of claims 1 to 14,
And an electronic device.