JP2009282923A - Semiconductor storage device and nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device and a nonvolatile memory for effectively allocating the number of bits used for parity among a plurality of pages to perform error correction of high correction ability to a page where a bit error occurrence ratio is high. <P>SOLUTION: The semiconductor storage device 300 includes a memory controller 100 and a nonvolatile memory 200. The nonvolatile memory comprises a plurality of pages and stores data and their parity. The memory controller has a function to add the parity to data input by host equipment and store them in the nonvolatile memory when writing data to the nonvolatile memory and, when reading the data, read the data and their parity from the nonvolatile memory to detect an error part and perform data error correction. The memory controller allocates the number of bits of all the parities available on the prescribed number of pages among the plurality of pages storable to the nonvolatile memory to each page in accordance with error occurrence ratio on each page. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device and a nonvolatile memory including a nonvolatile memory and a memory controller.

  The demand for NAND flash memories is increasing year by year due to the use of memory cards and the like. As the application expands, a memory card that operates at a higher capacity and at a higher speed is required. In order to meet the demand, a NAND flash memory using a finer process has been developed.

  In the NAND flash memory, operations at the time of data writing and reading are controlled by a memory controller. A memory controller having an ECC circuit adds parity to data input from the host device when data is written and stores it in the NAND flash memory, and stores data from the NAND flash memory together with the parity when data is read. Read, detect error location (address, etc.) and correct data error.

  The data stored in the storage area of the NAND flash memory is composed of a plurality of blocks (erase units), and the data in each block is composed of a predetermined number (for example, 128) pages. The unit for writing / reading data to / from the NAND flash memory is data for one page (page data) or data obtained by adding parity to data obtained by equally dividing data for one page into several.

  The data length and the number of parity bits input to the ECC circuit depend on the number of bits in one page of the NAND flash memory. The number of bits per page is defined by the sum of the data length and the parity length added to the data length that can be set in the NAND flash memory. In the NAND flash memory, conventionally, the number of parity bits added to data having a constant data length is constant (fixed), so that any page data (or its divided data) has a parity of 1 If the maximum number of parity bits that can be stored in the page storage area is added, if the bit error occurrence rate varies from page to page, the error correction capability may be excessive or insufficient depending on the page. That is, depending on the page, the number of parity bits may be too much or too little. In particular, if an evaluation test is performed for each page in a single NAND flash memory and the number of parities is determined according to the evaluation value with the worst (high) error rate, excessive parity will be generated on pages where errors are unlikely to occur. It will be attached.

As a prior art, there is a memory controller that corrects an error in read data for a multi-level cell memory using an ECC code (see, for example, Patent Document 1).
JP 2003-67260 A

  In view of the above problems, the present invention effectively allocates the number of bits used for parity among a plurality of pages in a non-volatile memory having a different bit error occurrence rate for each page, thereby enabling a page having a high bit error occurrence rate. An object of the present invention is to provide a semiconductor memory device and a nonvolatile memory that can perform error correction with higher correction capability.

  According to one aspect of the present invention, the nonvolatile memory is composed of a plurality of pages and stores data and the parity thereof, and when writing data to the nonvolatile memory, the parity is added to the page data and the nonvolatile memory is added. A memory controller having a function of reading page data and its parity from the nonvolatile memory, detecting an error location, and correcting the error of the data, The memory controller allocates, to each page, the number of all parity bits that can be used in a predetermined number of pages that can be stored in the nonvolatile memory according to the error occurrence rate of each page. A semiconductor memory device is provided.

  According to another aspect of the present invention, a memory area includes a plurality of data areas that can store page data of the same length, and a plurality of parities that are connected to each of the plurality of data areas and have the same length. And a predetermined number of parity areas in the plurality of parity areas corresponding to the predetermined number of data areas in the plurality of data areas capable of storing data. There is provided a non-volatile memory characterized in that all usable parity areas are allocated for each page according to the error occurrence rate of each page.

  According to the present invention, in a non-volatile memory having a different bit error rate for each page, by effectively allocating the number of bits used for parity among a plurality of pages, a page with a higher bit error rate is more It is possible to provide a nonvolatile semiconductor memory device and a nonvolatile memory that can perform error correction with high correction capability.

Embodiments of the invention will be described with reference to the drawings.
FIG. 11 shows the configuration of data stored in units of pages in the storage area of the NAND flash memory in the semiconductor memory device according to the related art of the present invention. The NAND flash memory has an area for storing data for 128 pages of page numbers 0 to 127, for example. One page of data is composed of, for example, two ECC correction units (this unit is also a unit for writing and reading), and each correction unit is composed of data and its parity (shown by diagonal lines). Yes.

  When data is read from the NAND flash memory, a set of data and parity of the ECC correction unit is read from the NAND flash memory and input to the ECC circuit under the control of the memory controller, and error detection and correction are performed. Is called.

  In this example, the data length and the number of parity bits (the ECC correction unit is constituted by the data length and the parity length) input from the NAND flash memory to the ECC circuit are the same for all pages. Therefore, assuming that there are two ECC correction units (referred to as two frames) in one page and the number of parity bits that can be used in one page is n bits, the number of parity bits input to the ECC circuit in all pages is n / 2. A bit.

  Since the number of parity bits with respect to the data length is constant (fixed), when the maximum number of parity bits that can fit on one page is set, if the bit error occurrence rate varies from page to page, the error correction capability is excessive depending on the page. The problem of becoming missing or missing arises.

  Therefore, in the embodiment of the present invention, in the NAND flash memory in which the bit error occurrence rate is different for each page, the number of parity bits is allocated among a plurality of pages, and the number of parity bits used for each page is set to the bit number. By assigning more to pages with a high error rate and assigning less to pages with a low bit error rate, the limited number of parity bits can be used more effectively and pages with a high bit error rate On the other hand, error correction with higher correction capability can be performed.

[First Embodiment]
FIG. 1 is a block diagram of a semiconductor memory device according to the first embodiment of the present invention.
In FIG. 1, a semiconductor memory device 300 includes a memory controller 100 and a NAND flash memory 200 that is a nonvolatile memory.

  The NAND flash memory 200 is composed of a plurality of pages, and stores the data and its parity in a unit of correction. The correction unit is the same as the writing unit or the reading unit, and may be one page, one half page, or one quarter page.

The memory controller 100 includes an SRAM buffer 101 and an ECC circuit 102.
The SRAM buffer 101 temporarily holds data from the host device 400, and writes data to the NAND flash memory 200 when the data has a predetermined length (for example, correction unit), and temporarily holds data read from the NAND flash memory 200. In order to output the data to the host device 400 after performing error correction on data of a predetermined length (for example, correction unit).

  Before writing to the NAND flash memory 200, the ECC circuit 102 adds parity necessary for correcting the data to the data of a predetermined length held in the SRAM buffer 101, and then writes the data to the NAND flash memory 200. . When reading data from the NAND flash memory 200, the data is temporarily stored in the SRAM buffer 101 and simultaneously input to the ECC circuit 102. The ECC circuit 102 detects the error location of the data using the parity of the fetched data. Then, the data in the SRAM buffer 101 (the same as the data fetched into the ECC circuit 102) is corrected.

  When the data to the SRAM buffer 101 is less than the predetermined length when writing data, the data for the shortage of the NAND flash memory 200 is written to the SRAM buffer 101 and sent to the ECC circuit 102. The ECC circuit 102 adds parity to the NAND flash memory 200 for writing.

  Therefore, the SRAM buffer 101 and the ECC circuit 102 in the memory controller 100 add the parity to the data input from the host device 400 and store it in the NAND flash memory 200 when writing data to the NAND flash memory 200. When reading data from the NAND flash memory 200, it has a function of reading data and its parity from the NAND flash memory 200, detecting an error location, and correcting the error of the data.

  Here, an example in which the host device 400 and the semiconductor storage device 300 are configured separately is shown, but the semiconductor storage device 300 may be incorporated in the host device 400.

  The ECC circuit 102 in the memory controller 100 calculates the number of bits of all the parity that can be used in a predetermined number of consecutive pages among a plurality of pages that can be stored in the NAND flash memory 200 when data is written. Is assigned to each page (a page at this time corresponds to one correction unit) according to the size of the error occurrence rate. Alternatively, the ECC circuit 102 in the memory controller 100 determines the parity added for each of a plurality of correction units constituting each page of the plurality of pages stored in the NAND flash memory 200 according to the error occurrence rate of each page. May be assigned to the correction unit of each page. These will be described later.

  FIG. 2 is a diagram for explaining the operation at the time of reading in FIG. Data read from the NAND flash memory 200 is simultaneously input to the SRAM buffer 101 and the ECC circuit 102 at time t1 and taken in. The ECC circuit 102 starts calculation of error correction of the data taken in at time t2 after the data fetching is finished. In this calculation, the parity of the correction unit data is used to analyze where the data is broken. Then, the ECC circuit 102 receives the data in the SRAM buffer 101 based on the analysis result at the time t3 when the error analysis calculation is completed (since this data is the same as the data fetched into the ECC circuit 102, the error location is also The same is true) and the error correction is completed at time t4.

FIG. 3 is a diagram for explaining a block area (hereinafter simply referred to as a block) that is an erase unit and a page area (hereinafter simply referred to as a page) that is a correction unit (same as a write unit or a read unit) in the NAND flash memory 200. is there.
The memory area of the NAND flash memory 200 is composed of a plurality of blocks as shown in FIG. Each block is composed of a plurality of pages as shown in FIG. In the NAND flash memory 200, data can be erased in blocks of erase units, but cannot be erased in pages of correction units constituting the blocks.

  One block is composed of a data area of 128 pages (= 256 kbytes) of a predetermined number of pages, for example, a page of 2 kbytes for one page. Provided. This extra area stores parity data for performing error correction on data of a certain length of each page of all pages constituting the data area, and stores control data for memory control. Can be used. In this embodiment, the remainder area is called a parity area as shown in FIG. 3C, and a case where it is used only for storing a parity bit (parity length Zbyte) will be described.

  FIG. 4 shows the configuration of the correction unit. The correction unit is composed of data and its parity. The data is, for example, 2 kbytes, 1 kbyte (= 1024 bytes), or 512 bytes. As shown in FIG. 3 (C), if the data portion of one page is 2 kbytes, the data portion of the correction unit is 2 kbytes, 1 kbyte, and 512 bytes, respectively. It corresponds. At present, a data portion of one page is 8 kbytes.

FIG. 5 shows the number of bits of data that can be corrected by the size of the parity added to the data. For example, 10-byte parity is required to correct 8 bits.
FIG. 6 is a diagram illustrating an example of a state in which the number of parity bits used between two pages is allocated in the storage area of the nonvolatile memory in the semiconductor storage device of the first embodiment.

  Conventionally, the number of bits used for parity in all pages is uniform. In other words, assuming that the number of parity bits that can be used in one page is n bits, when there are two correction units in one page, the number of parity correction units input to the ECC circuit 102 in all pages is n / 2 bits. It becomes.

  When allocating the number of bits to be used for parity between two consecutive pages, if the parity bit number n / 2 to s of the even page of the two consecutive odd / even pages is used as the parity of the odd page, the odd page The number of parity is n / 2 + s, and the correction capability can be increased compared to the conventional error correction using n / 2 bits. Accordingly, the number of parity bits of the even page is reduced to n / 2−s. Moreover, of course, the number of parity bits between two consecutive odd / even pages is constant without changing with the number of parity bits n bits that can be used in one page. Therefore, the example of FIG. 6 is useful when the error rate of odd pages is high.

  In the example of FIG. 6, the odd-numbered page is configured to increase the parity bit number as an error-prone page between the even-numbered page and the odd-numbered page. You may comprise so that it may increase.

FIG. 7 is a diagram for explaining the operation in the ECC circuit when the number of bits used for parity is allocated between two consecutive odd / even pages in FIG. 6 at the time of writing.
With respect to the correction unit data a or b in the even page in the ECC circuit 102 of FIG. 1, when the data a or b is input to the ECC circuit 102 as shown in FIG. Are added with a parity of n / 2−s bits. As for the correction unit data c or d in the odd page, when the data c or d is input to the ECC circuit 102 as shown in FIG. 7B, the ECC circuit 102 determines the number of bits for the data. Output with n / 2 + s parity added.

Next, description will be given of an example of writing and reading operations with respect to the NAND flash memory 200 for page 0 and page 1 as two consecutive odd / even pages.
At the time of writing, for example, 1 kbytes of raw data (data before parity is added) a and b are sequentially held in the SRAM buffer 101 as correction unit data corresponding to page 0 from the host device 400, and then the data a , B are sequentially fetched into the ECC circuit 102, and the ECC circuit 102 holds the data a, b with the parity numbers n / 2-s sequentially added thereto. Next, the correction units of data c and d corresponding to page 1 are also sequentially held in the SRAM buffer 101 in the same manner, and then the data c and d are sequentially taken into the ECC circuit 102 and then stored in the ECC circuit 102. The data c and d are held with the parity number n / 2 + s sequentially added thereto. The data held in the ECC circuit 102 is converted into a part of the page 0 area (part indicated by hatching) in the part of the page 0 area as shown in pages 0 and 1 of FIG. After the rearrangement is performed so that it is incorporated, half of the page length is sequentially written in the storage area of the NAND flash memory 200, and then half of the page length is sequentially written for page 1 as well. The rearrangement operation can also be performed in the SRAM buffer 101.

  At the time of reading, the NAND flash memory 200 sequentially reads the page 0, which is the same as FIG. 6 by half the page length, and then sequentially reads the page 1 by half the page length, and then page 0. And the number of parity bits between page 1 are rearranged to obtain the ECC correction units of page 0 and page 1 shown on the right side of FIG. 6, and the data of these correction units are also written in the SRAM buffer 101. As shown, data error (error) is detected for each correction unit in the ECC circuit 102, and the same error portion of the data held in the SRAM buffer 101 is corrected.

  FIG. 8 shows a storage area of a NAND flash memory, in which (A) the page length of each page is divided into four correction units between two consecutive odd / even pages, and (B) the page length of each page is 2 When divided into correction units, (C) When the page length of each page is not divided and is used as the correction unit, the number of parity bits between the upper and lower correction units between the two pages in each case Three examples are shown in which a large number is assigned to odd pages 2m + 1 and a small number is assigned to even pages 2m. 8A to 8C, m is an integer of 0 or more. Of course, a configuration in which a larger number of parity bits are allocated to the even page 2m and a smaller number is allocated to the odd page 2m + 1 is also possible.

  In FIG. 8A, when the page length is represented by X, the data length is represented by y1, the parity length is represented by z1, and a character variable, X = (y1 + z1) × 4. If the data length in one page is 2 kbytes, for example, the data length y1 is 512 bytes. In FIG. 8B, when the page length is represented by X, the data length is represented by y2, the parity length is represented by z2 and a character variable, the relationship is X = (y2 + z2) × 2. If the data length in one page is 2 kbytes, the data length y2 is 1 kbyte. In FIG. 8C, when the page length is represented by X, the data length is represented by y3, the parity length is represented by z3, and a character variable, the relationship is X = y3 + z3. If the data length in one page is 2 kbytes, the data length y3 is 2 kbytes.

  According to the first embodiment, a bit error occurrence rate is obtained by allocating a parity area of a storage area composed of two of a plurality of pages of a NAND flash memory which is a nonvolatile memory in accordance with a bit error occurrence rate. It is possible to allocate a larger number of bits to parity for a page with a high bit rate and to allocate a smaller number to a page with a low bit error occurrence rate, and to more effectively use a limited number of parity bits.

[Second Embodiment]
The configuration of the semiconductor memory device according to the second embodiment of the present invention is the same as that shown in FIG.
FIG. 9 is a diagram illustrating an example of a state in which the number of bits used for parity is allocated among three pages in the storage area of the nonvolatile memory in the semiconductor storage device of the second embodiment. In the following description, the number of parity bits that can be used in one page is n bits.

  When allocating the number of bits to be used for parity between three consecutive pages, the number of parity bits n / 2 to s bits of page 3m (m is an integer of 0 or more) of the three consecutive pages, pages 3m + 1 to t When bits are used as the parity of page 3m + 2, the parity of page 3m + 2 is n / 2 + s + t bits, and the correction capability can be increased compared to the conventional error correction using n / 2 bits. Accordingly, the number of parity bits of page 3m is n / 2−s, and the number of parity bits of page 3m + 1 is n / 2−t. In addition, the number of parity bits that can be used between three consecutive pages is three times the number of parity bits n that can be used in one page, and the total number of parity bits remains unchanged. Therefore, the example of FIG. 9 is useful when the error occurrence rate of the page 3m + 2 is high.

  In the example of FIG. 9, the third page 2 of the three pages 0, 1, and 2 is configured to increase the number of parity bits as the page where the error is most likely to occur. It is also possible to configure the first or second page as the page where errors are most likely to occur so that the number of parity bits is increased most.

FIG. 10 is a diagram for explaining the operation in the ECC circuit when the number of bits used for parity is allocated between three consecutive pages in FIG. 9 at the time of writing.
With respect to the correction unit data a or b in the page 3m in the ECC circuit 102 of FIG. 1, when the data a or b is input to the ECC circuit 102 as shown in FIG. Are added with a parity of n / 2−s bits. As for the correction unit data c or d in the page 3m + 1, when the data c or d is input to the ECC circuit 102 as shown in FIG. 10B, the ECC circuit 102 determines the number of bits for the data. Output with n / 2-t parity added. Further, for the correction unit data e or f in the page 3m + 2, when the data e or f is input to the ECC circuit 102 as shown in FIG. 10C, the ECC circuit 102 determines the number of bits for the data. Output with parity of n / 2 + s + t added.

Next, an operation example of writing and reading with respect to the NAND flash memory 200 for page 0, page 1, and page 2 as three consecutive pages will be described.
At the time of writing, for example, 1 kbytes of raw data (data before parity is added) a and b are sequentially held in the SRAM buffer 101 as correction unit data corresponding to page 0 from the host device 400, and then the data a , B are sequentially fetched into the ECC circuit 102, and the ECC circuit 102 holds the data a, b with the parity numbers n / 2-s sequentially added thereto. Next, the correction units of data c and d corresponding to page 1 are also sequentially held in the SRAM buffer 101 in the same manner, and then the data c and d are sequentially taken into the ECC circuit 102 and then stored in the ECC circuit 102. The data c and d are held in a state where the parity number n / 2-t is sequentially added. Further, the correction unit data e and f corresponding to page 2 are also sequentially stored in the SRAM buffer 101 in the same manner, and then the data e and f are sequentially taken into the ECC circuit 102 and the ECC circuit 102 receives the data. Each of e and f is held with the parity number n / 2 + s + t sequentially added. The data held in the ECC circuit 102 is converted into a part of the parity bit number of page 2 (part shown by hatching) in part of the area of page 0 as shown in pages 0, 1 and 2 in FIG. ) And a part of the page 1 area in which part of the parity bit number of page 2 (part indicated by hatching) is incorporated, and then stored in the NAND flash memory 200 Half of the page length is sequentially written in the area for page 0, then half of the page length is sequentially written for page 1, and half of the page length is sequentially written for page 2 as well. The rearrangement operation can also be performed in the SRAM buffer 101.

  At the time of reading, the NAND flash memory 200 sequentially reads the page 0 in the same manner as in FIG. 9 by half of the page length, and then sequentially reads the page 1 by half of the page length. After half of the page length is read sequentially, the number of parity bits is rearranged between pages 0, 1 and 2 to obtain ECC correction units for pages 0, 1 and 2 shown on the right side of FIG. The correction unit data is also written to the SRAM buffer 101, and as shown in FIG. 2, an error in the data is detected for each correction unit within the ECC circuit 102, and the data held in the SRAM buffer 101 is detected. The same error part will be corrected.

  According to the second embodiment, a bit error rate is obtained by allocating a parity area of a storage area composed of three pages among a plurality of pages of a NAND flash memory which is a nonvolatile memory according to the bit error rate. It is possible to allocate a larger number of bits to parity for a page with a high bit rate and to allocate a smaller number to a page with a low bit error occurrence rate, and to more effectively use a limited number of parity bits.

  In the embodiment described above, as shown in FIGS. 6 and 9, the parity area of the storage area consisting of a plurality of continuous pages (for example, 2 pages and 3 pages) is allocated according to the bit error occurrence rate. However, the present invention is not limited to this, and can be applied to the case of allocating the parity area of the storage area composed of a plurality of pages that exist without being consecutively arranged according to the bit error occurrence rate. Can do.

1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating an operation at the time of reading in FIG. 1. The figure explaining the block area | region which is an erasing unit and the page area | region which is a correction unit in NAND flash memory. The figure which shows the structure of a correction unit. The figure which shows the bit number of the data which can be corrected with the size of the parity added to data. FIG. 3 is a diagram for explaining an example of a state in which the number of bits used for parity is allocated between pages in the storage area of the nonvolatile memory in the semiconductor storage device of the first embodiment. FIG. 7 is a diagram for explaining the operation in the ECC circuit when the number of bits used for parity is allocated between two consecutive odd / even pages in FIG. 6 during writing. FIG. 6 is a diagram showing three examples in the case where a fixed page length of each page is divided into a plurality of correction units between two consecutive odd / even pages in the storage area of the NAND flash memory according to the first embodiment. The figure explaining an example of the state which allocated the bit number used for a parity between three pages in the storage area of the non-volatile memory in the semiconductor memory device of the 2nd Embodiment of this invention. FIG. 10 is a diagram for explaining the operation in the ECC circuit when the number of bits used for parity is allocated between three consecutive pages in FIG. 9 during writing. The figure which shows the structure of the data memorize | stored per page in the storage area of the NAND type flash memory in the semiconductor memory device of the related technology of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Memory controller 101 ... SRAM buffer 102 ... ECC circuit (error correction circuit)
200 ... NAND flash memory (nonvolatile memory)
300 ... Semiconductor memory device 400 ... Host equipment

Claims (4)

A non-volatile memory composed of a plurality of pages and storing data and its parity;
When writing data to the non-volatile memory, parity is added to page data and stored in the non-volatile memory, and when reading data, page data and its parity are read from the non-volatile memory, and the error location is A memory controller having a function of detecting and correcting data errors;
The memory controller sets the number of bits of all parity that can be used in a predetermined number of pages out of a plurality of pages that can be stored in the nonvolatile memory for each page according to the error occurrence rate of each page. A semiconductor memory device characterized by being allocated to The page data is composed of a plurality of correction unit data,
The memory controller is configured to calculate each parity added to each of a plurality of correction units constituting each page of the predetermined number of pages stored in the nonvolatile memory according to an error occurrence rate of each page. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is assigned to each other. A non-volatile configuration in which a memory area includes a plurality of data areas that can store page data of the same length and a plurality of parity areas that are connected to each of the plurality of data areas and have the same length. Memory,
Corresponding to a predetermined number of data areas of the plurality of data areas that can store data, all parity areas that can be used in the predetermined number of parity areas of the plurality of parity areas are set to error occurrence rates of each page. A non-volatile memory characterized by being allocated to each page according to the size of the memory. The page data is composed of a plurality of correction unit data,
Each parity area added to each of a plurality of correction units constituting each page corresponding to a predetermined number of data areas among the plurality of data areas is used as a correction unit for each page according to the error occurrence rate of each page. The nonvolatile memory according to claim 3, wherein the nonvolatile memory is allocated.

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