JP2009252895A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a CMOSFET having a threshold voltage appropriate for PMOS and NMOS, using a gate insulating film of high dielectric constant. <P>SOLUTION: Without using a lantern oxide film with delinquency as a cap film, an insulating film containing lantern is formed on a silicon oxide film 104 before an insulating film 111 containing hafnium is formed, to protect the insulating film 111 containing hafnium. Further, an SiGe layer 108 is epitaxial-grown in a PMOS region having been damaged by etching. Thus a structure having such threshold voltage as appropriate for PMOS and NMOS is formed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a complementary metal oxide semiconductor field effect transistor (CMOSFET) using a high dielectric constant gate insulating film and a method for manufacturing the same.

  Along with the recent miniaturization of large-scale integrated circuits, the CMOSFET transistor is also required to have a thin gate insulating film. For the next-generation gate insulating film, use a metal oxide film, metal silicate film, or a nitride film with a higher dielectric constant than silicon oxide film or silicon oxynitride film, which is called high dielectric constant gate insulating film. Thus, a proposal has been made to reduce the electrical film thickness while suppressing the leakage current by increasing the physical film thickness.

In particular, as a high dielectric constant gate insulating film, a hafnium oxide film (HfO ₂ film), a hafnium silicate film (HfSiO film), or a hafnium oxynitride film (HfON film) in which nitrogen is mixed therein to improve heat resistance In addition, the use of a hafnium silicate nitride film (HfSiON film) has been actively studied.

  In addition, with the miniaturization, the conventional transistor using polycrystalline silicon as the gate electrode material has a problem that the capacitance on the inversion side is reduced due to depletion of the gate electrode, and metal is used instead of polycrystalline silicon. Proposals for use in electrodes have been made. The metal in this case refers to a metal, a metal nitride, a metal silicide, or the like.

  When using metal for the gate electrode, in addition to the merit that the threshold voltage can be controlled by using the metal with the optimum work function, depletion of the electrode is less likely to occur compared to the gate electrode of polycrystalline silicon. There is also an advantage that a large inversion capacity can be secured.

  However, in order to obtain a CMOSFET having a high driving force, it is necessary to lower the threshold voltage. The NMOS (N Channel Metal Oxide Semiconductor) is about 4.0 eV, and the PMOS (P Channel Metal Oxide Semiconductor) is about 5.1 eV. It is desirable to select a gate electrode material having an effective work function.

  Further, when the source / drain is formed after the gate electrode is formed, a thermal process of 1000 ° C. or higher is required for the activation. Gate electrode materials that can withstand this thermal process and are formed on a high dielectric constant gate insulating film containing hafnium and have a high effective work function include a tungsten nitride film (WN film) and a molybdenum nitride film (MoN film). However, the effective work function is close to 4.0 eV so far, and no heat-resistant material has been found.

In recent years, as a method for obtaining an effective work function around 4.0 eV, a method of capping a lanthanum oxide film (La ₂ O ₃ ) on a hafnium oxide film has been proposed (Non-patent Document 1).

  When manufacturing a CMOSFET using the proposed lanthanum oxide film as a cap film, (1) an interface layer of a silicon oxide film is formed on the N-type and P-type regions of the silicon substrate, and hafnium oxide is formed on the interface layer. After sequentially laminating a film and a lanthanum oxide film, (2) a resist is formed in the P-type region by a lithography process, and the lanthanum oxide film in the N-type region is removed using this resist as a mask. After removing the resist, (4) a tungsten nitride electrode material is formed on the lanthanum oxide film in the P-type region and the hafnium oxide film in the N-type region, and (5) silicon is formed on the tungsten nitride film in the N-type region. After forming the nitride film, the tungsten nitride film in the P-type region is removed using this silicon nitride film as a mask, and then (6) the silicon nitride film is removed, and (7) After stacking the barrel carbide film, and a polycrystalline silicon film or the like, so that the gate processing.

  However, in the step of forming the resist of the above (2), when misalignment or the like occurs, the photolithography process is repeated again after removing the resist, so that the time for which the lanthanum oxide film is exposed to the atmosphere becomes longer. Degradation of the film quality occurs when the lanthanum oxide film is exposed to a solvent. Further, in the step (6) of removing the silicon nitride film formed as a mask, the lanthanum oxide film is exposed to the Wet treatment solution, resulting in deterioration of the film quality or loss of the lanthanum oxide film.

  In the step (2) of removing the resist, by using an oxygen ashing method without using a solvent, the lanthanum oxide film can be prevented from being exposed to the solvent, but it is an interface layer during the oxygen ashing. There has been a problem that the thickness of the silicon oxide film increases and the transistor characteristics deteriorate.

As described above, due to the deterioration of the lanthanum oxide film quality, there is a concern about a change in threshold voltage in the NMOS region, and it is required to prevent the deterioration of the lanthanum oxide film. Also in the PMOS region, since the effective work function of the material is not sufficient, it is required to further reduce the threshold voltage.
V. Narayanan et al., 2006 Symposium On VLSI Technology Digest of Technical Papers, pp.224

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a CMOSFET having a work function suitable for PMOS and NMOS using a high dielectric constant gate insulating film and a method for manufacturing the same. .

  In order to achieve the above object, a semiconductor device according to one embodiment of the present invention includes a semiconductor substrate having P-type and N-type regions that are isolated from each other, and a silicon oxide film or silicon oxynitride formed over the P-type region. A first insulating film made of a film, a second insulating film that does not contain hafnium formed on the first insulating film but contains lanthanum, and hafnium and lanthanum formed on the second insulating film. A third insulating film containing, a first gate insulating film having a laminated structure having a fourth insulating film containing hafnium without containing lanthanum formed on the third insulating film, and the N-type region A silicon germanium layer formed thereon, a fifth insulating film made of a silicon oxide film or a silicon oxynitride film formed on the silicon germanium layer, and lanthanum formed on the fifth insulating film. And a second gate insulating film having a laminated structure having a sixth insulating film containing hafnium, and a gate electrode formed on each of the first and second gate insulating films. To do.

  According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a P-type and an N-type region that are insulated and separated by an element isolation region on a main surface of a semiconductor substrate; A step of forming a first insulating film made of a silicon oxide film or a silicon oxynitride film, a step of sequentially laminating a lanthanum oxide film and a hafnium insulating film containing hafnium on the first insulating film, and the N Sequentially removing the hafnium insulating film, the lanthanum oxide film and the first insulating film on the mold region to expose the N-type region; and the lanthanum element of the lanthanum oxide film on the P-type region and the Forming a third insulating film containing hafnium and lanthanum by reacting the hafnium element of the hafnium insulating film; and forming a silicon germanium layer on the exposed N-type region. A step of forming a fifth insulating film made of a silicon oxide film or a silicon oxynitride film on the silicon germanium layer; and a step of containing hafnium on the third insulating film and the fifth insulating film. Forming a fourth insulating film, and forming a second insulating film not containing hafnium but containing lanthanum between the first insulating film and the third insulating film on the P-type region. A step of forming a gate electrode material on the fourth insulating film; and processing the gate electrode material and the first to fifth insulating films to form the first to fifth layers on the P-type region. A first gate insulating film having a fourth insulating film and a gate electrode is formed on the first gate insulating film, the fifth insulating film on the N-type region, and the fourth gate A second layered structure having a sixth insulating film by processing of the other insulating film And a step of forming a gate electrode on the second insulating film.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a P-type and an N-type region that are insulated and separated by an element isolation region on a main surface of a semiconductor substrate; Forming a first insulating film made of a silicon oxide film or a silicon oxynitride film, forming a third insulating film containing hafnium and lanthanum on the first insulating film, and the N-type Sequentially removing the third insulating film and the first insulating film on the region to expose the N-type region; and the first insulating film and the third insulating film in the P-type region Forming a second insulating film containing lanthanum without containing hafnium, and forming a silicon germanium layer on the exposed N-type region, and then forming a silicon oxide film on the silicon germanium layer Or a silicon oxynitride film Forming a fifth insulating film; forming a fourth insulating film containing hafnium on the third insulating film and the fifth insulating film; and forming a gate on the fourth insulating film. Forming a first electrode material; and processing the first gate electrode material and the first to fifth insulating films to form a first laminated structure having the first to fourth insulating films on the P-type region. Forming a gate electrode on the gate insulating film and the first gate insulating film, and forming the fifth insulating film on the N-type region and a sixth insulating film obtained by processing the fourth insulating film; And a step of forming a gate electrode on the second insulating film.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which has CMOSFET which uses a high dielectric constant gate insulating film and has a work function suitable for PMOS and NMOS, and its manufacturing method can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 and 2 are cross-sectional views showing a manufacturing process of a semiconductor device having a CMOSFET according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, a PMOSFET formation region (hereinafter simply referred to as a PMOS region) partitioned by an element isolation 101 on a main surface of a single crystal silicon substrate (hereinafter simply referred to as a silicon substrate) 100. ) And a P-type diffusion region 103 which is an NMOSFET formation region (hereinafter simply referred to as an NMOS region). A silicon oxide film 104 as a first insulating film is formed on the silicon substrate 100 by using a thermal oxidation method or a radical oxidation method. The first insulating film may be a silicon oxynitride film in addition to the silicon oxide film. A lanthanum oxide film 105 and a hafnium oxide film 106 are sequentially stacked on the silicon oxide film 104 by using a CVD method or the like. Here, since the lanthanum oxide film 105 is hygroscopic and deteriorates when exposed to the atmosphere for a long time, the hafnium oxide film 106 is formed after the lanthanum oxide film 105 is formed and released to the atmosphere. It is desirable that the time be within 30 minutes, preferably within 30 minutes. Furthermore, it is desirable that the lanthanum oxide film 105 and the hafnium oxide film 106 be formed continuously without breaking the vacuum.

  Next, as shown in FIG. 1B, a resist 107 is formed on the NMOS region by photolithography or the like. In this case, even if rework occurs, since the lanthanum oxide film 105 is covered with the hafnium oxide film 106, the film quality of the lanthanum oxide film 105 does not deteriorate.

  Thereafter, as shown in FIG. 1C, the hafnium oxide film 106, the lanthanum oxide film 105, and the silicon oxide film 104 in the PMOS region are sequentially formed by using reactive resist etching and dilute HF / diluted HCl aqueous solution using the resist 107 as a mask. Then, the main surface of the silicon substrate 100 in the PMOS region is exposed.

  Subsequently, as shown in FIG. 1D, the resist 107 is removed with a solvent. At this time, since the lanthanum oxide film 105 is covered with the hafnium oxide film 106, the resist 107 can be removed with a solvent without using an asher, and an increase in the thickness of the silicon oxide film 104 as an interface layer is prevented. can do.

  Next, as shown in FIG. 1E, for example, heat treatment is performed at 1000 ° C. for 5 to 10 seconds in a nitrogen atmosphere. By this heat treatment, the lanthanum oxide film 105 and the hafnium oxide film 106 in the NMOS region diffuse into the lanthanum element and hafnium to form a hafnium lanthanum oxide film 109 serving as a third insulating film. Here, about 0.1 to 1.0% of oxygen may be contained in the nitrogen atmosphere. The hafnium lanthanum oxide film 109 may be formed by performing rapid heating in a very short time by spike annealing.

  Next, a silicon germanium (SiGe) layer 108 is epitaxially grown on the silicon substrate 102 in the PMOS region. This is for recovering the damage of the silicon substrate 100 that is received when the hafnium oxide film 106, the lanthanum oxide film 105, and the silicon oxide film 104 in the PMOS region are removed by reactive ion etching. Further, by growing the SiGe layer 108 in the PMOS region, the apparent effective work function can be increased as compared with the case where a silicon substrate is used, and a threshold voltage more suitable for the PMOSFET can be obtained. When the SiGe layer 108 is grown, for example, an impurity such as boron may be doped to adjust the threshold voltage of the PMOSFET.

  Next, as shown in FIG. 2A, a silicon oxide film 110 which is a fifth insulating film is formed on the SiGe layer 108 in the PMOS region by using, for example, a thermal oxidation method, a radical oxidation method, an ALD method, or the like. Form. Similarly to the first insulating film, the fifth insulating film may be a silicon oxynitride film in addition to the silicon oxide film. When the fifth insulating film is formed by oxidizing the SiGe layer 108, there is a possibility that a germanium element is contained in the fifth insulating film. However, since the germanium element contained is small and does not affect the device characteristics, the fifth insulating film may contain germanium element. After the silicon oxide film 110 is formed, a hafnium silicate film is formed on the hafnium lanthanum oxide film 109 in the NMOS region and the silicon oxide film 110 in the PMOS region by using a CVD method or the like.

After the hafnium silicate film is formed, for example, nitrogen is mixed into the hafnium silicate film by performing plasma nitridation at room temperature to 450 ° C. for 30 to 180 seconds. Further, a heat treatment at 1000 to 1050 ° C. is performed to form a hafnium silicate nitride film 111 that is a fourth insulating film. In addition, a lanthanum silicic oxide film (LaSiO _x ) 112 as a second insulating film is formed between the hafnium lanthanum oxide film 109 and the silicon oxide film 104 in the NMOS region by the heating process at this time.

  Thereafter, as shown in FIG. 2B, a tungsten nitride film 113 as a gate electrode material is formed on the hafnium silicate nitride film 111 by using a CVD method or the like, and further, a silicon nitride film 114 is formed on the tungsten nitride film 113. Then, a mask of the silicon nitride film 114 is formed in the PMOS region by a photolithography method or the like.

  Subsequently, as shown in FIG. 2C, the tungsten nitride film 113 in the NMOS region is removed with a hydrogen peroxide solution or the like using the mask of the silicon nitride film 114. Further, the mask of the silicon nitride film 114 is removed with heated phosphoric acid.

  Next, as shown in FIG. 2D, a tantalum carbide film 115 as a gate electrode material is formed on the tungsten nitride film 113 in the PMOS region and the hafnium silicate nitride film 111 in the NMOS region by using a CVD method or the like. Further, a polycrystalline silicon film 116 and a silicon nitride film 117 are sequentially stacked on the tantalum carbide film 115.

  Next, as shown in FIG. 2E, after arsenic, phosphorus, or the like is ion-implanted into the polycrystalline silicon film 116, a gate electrode and a reactive ion etching method, a Wet treatment method are used. The gate insulating film is patterned.

  In the present embodiment, the gate insulating film of the NMOSFET has a laminated structure of the hafnium silicate nitride film 111 / hafnium lanthanum oxide film 109 / lanthanum silicate oxide film 112 / silicon oxide film 104 from the gate electrode side, and the gate insulating film of the PMOSFET is Then, a stacked structure of hafnium silicate nitride film 111 / silicon oxide film 110 is formed.

  In other words, the gate insulating film of the NMOSFET has a silicon oxide film that is the first insulating film / the second insulating film that does not contain the hafnium element but contains the lanthanum element / hafnium element and lanthanum element from the silicon substrate 100 side. The third insulating film contained / the fourth insulating film containing hafnium without containing the lanthanum element, and the gate insulating film of the PMOSFET is the silicon oxide which is the fifth insulating film from the silicon substrate 100 side. The structure is a sixth insulating film containing no film / lanthanum element and containing hafnium.

  The gate electrode of the NMOSFET has a stacked structure of the polycrystalline silicon film 116 and the tantalum carbide film 115, and the gate electrode of the PMOSFET has a stacked structure of the polycrystalline silicon film 116, the tantalum carbide film 115, and the tungsten nitride film 113. Become.

  In the present embodiment, the formed film itself is very thin, the interface between the films is unclear, and the constituent elements of each film diffuse to each other in the interface region. It is considered that hafnium is present in the insulating film and a small amount of lanthanum is present in the fourth insulating film. Such permeation of elements due to diffusion occurs structurally, and the permeation elements are not considered to be contained elements.

  According to the above-described embodiment, the following effects can be obtained. That is, by forming the hafnium oxide film 106 on the lanthanum oxide film 105, it is possible to prevent the lanthanum oxide film 105 from being exposed to the air or a solvent, and to prevent film quality deterioration of the lanthanum oxide film 105. Also, since the lanthanum element is not diffused from the cap layer but a film containing only the amount of lanthanum element necessary for threshold reduction is formed on the silicon substrate 100, the threshold voltage can be adjusted accurately. Can do. Further, by growing the SiGe layer 108 in the PMOS region damaged by the etching process, both the NMOSFET and the PMOSFET can be formed with a low threshold voltage.

  In the conventional manufacturing method, an insulating film containing lanthanum is used as a cap layer, and the threshold voltage is adjusted by diffusing it to the vicinity of the silicon oxide film. Therefore, lanthanum element is contained in all layers of the gate insulating film. In addition, it was difficult to adjust the amount of lanthanum element.

  Further, since the relative dielectric constant of the lanthanum silicic oxide film 112 is higher than that of the silicon oxide film 104, the electrical gate insulating film of the NMOSFET can be made thin. If the film thickness of the silicon oxide film 110 that is the interface layer of the PMOSFET and the film thickness of the silicon oxide film 104 that is the interface layer of the NMOSFET are selected to an optimum film thickness ratio, the electrical gate insulating film of the NMOSFET and PMOSFET It becomes possible to make the thickness the same.

  Furthermore, if the NMOSFET and the PMOSFET have the same insulating layer structure, the leakage current of the PMOSFET is lower than that of the NMOSFET, so that the thickness of the electrical gate insulating film of the PMOSFET is made thinner than the thickness of the electrical gate insulating film of the NMOSFET. As a result, the leakage current is the same between the NMOSFET and the PMOSFET, and the driving power of the PMOSFET can be improved as compared with the prior art. The specific thickness of the gate insulating film can be adjusted according to the requirements of a desired device.

  In this embodiment, the hafnium oxide film 106 is formed after the lanthanum oxide film 105 is formed. However, in order to protect the lanthanum oxide film 105, the hafnium oxide film 106 needs to be a continuous film. The film thickness of the hafnium oxide film 106 is desirably 0.3 nm or more.

  In addition, since the lanthanum oxide film 105 is used to control the threshold value, the film thickness can be adjusted in accordance with device requirements. For example, when a low threshold voltage is required, the lanthanum oxide film 105 may be formed thick. In the case of a device that does not require a very low threshold voltage, an island-like state may be used instead of a film. In the state of metal lanthanum.

  In addition, in this embodiment, the hafnium silicate nitride film 111 is used for the gate insulating film portion in contact with the gate electrode, but the hafnium oxynitride film, zirconium oxide film, zirconium oxynitride film, hafnium silicate film, hafnium oxide film A film, a zirconium silicate film, a zirconium silicate nitride film, a hafnium zirconium oxynitride film, a hafnium zirconium oxynitride film, a hafnium zirconium silicate film, a hafnium zirconium silicate nitride film, or the like may be used.

  In the present embodiment, the lanthanum oxide film 105 and the hafnium oxide film 106 in the NMOS region are reacted to form the hafnium lanthanum oxide film 109, so that the heating process is performed in the process shown in FIG. When the layer 108 is epitaxially grown, the natural oxide film on the surface of the Si substrate is removed by heat treatment at 700 ° C. or higher. During this high-temperature heat treatment, the lanthanum oxide film 105 and the hafnium oxide film 106 in the NMOS region diffuse to each other and the hafnium lanthanum oxide film 109 is formed.

  Furthermore, in the present embodiment, the lanthanum silicic oxide film 112 is formed during the nitriding step of the hafnium silicate nitride film 111. However, in the case of a material that is not nitrided, for example, by heating at 1000 ° C. for 5 to 10 seconds, A lanthanum silicon oxide film 112 may be formed.

(Second Embodiment)
FIG. 3 and FIG. 4 are cross-sectional views showing manufacturing steps of a semiconductor device having a CMOSFET according to the second embodiment of the present invention.

  First, as shown in FIG. 3A, an N-type diffusion region 202 that is a PMOS region and a P-type diffusion region 203 that is an NMOS region defined by the element isolation 201 are formed on the main surface of the silicon substrate 200. . A silicon oxide film 204 as a first insulating film is formed on the silicon substrate 200 by using a thermal oxidation method or a radical oxidation method. The first insulating film may be a silicon oxynitride film in addition to the silicon oxide film. On the silicon oxide film 204, a hafnium lanthanum oxide film 205, which is a third insulating film, is formed by CVD or the like.

  Next, as shown in FIG. 3B, a resist 206 is formed on the NMOS region by photolithography or the like. Thereafter, as shown in FIG. 3C, using the resist 206 as a mask, the hafnium lanthanum oxide film 205 and the silicon oxide film 204 in the PMOS region are removed by reactive ion etching and etching using dilute HF aqueous solution. The main surface of the silicon substrate 200 is exposed.

  Subsequently, as shown in FIG. 3D, the resist 206 is removed with a solvent. At this time, an increase in the thickness of the silicon oxide film 204 can be prevented by removing the resist 206 with a solvent without using an oxygen asher. Next, as shown in FIG. 3E, for example, by performing heat treatment at 1000 ° C. for 5 to 10 seconds, lanthanum that is a second insulating film between the hafnium lanthanum oxide film 205 and the silicon oxide film 204 is performed. A silicon oxide film 207 is formed.

  Thereafter, the SiGe layer 208 is epitaxially grown on the silicon substrate in the PMOS region. This is for recovering the damage of the silicon substrate 200 received when the hafnium lanthanum oxide film 205 and the silicon oxide film 204 in the PMOS region are removed by reactive ion etching. Further, by growing the SiGe layer 208 in the PMOS region, the apparent effective work function can be increased and the threshold voltage can be decreased as compared with the case where a silicon substrate is used. When the SiGe layer 208 is grown, for example, an impurity such as boron may be doped to adjust the threshold voltage of the PMOSFET.

  Next, as shown in FIG. 4A, a silicon oxide film 209 as a fifth insulating film is formed on the SiGe layer 208 in the PMOS region by, for example, thermal oxidation, radical oxidation, ALD, or the like. . Similarly to the first insulating film, the fifth insulating film may be a silicon oxynitride film in addition to the silicon oxide film. When the fifth insulating film is formed by oxidizing the SiGe layer 108, there is a possibility that a germanium element is contained in the fifth insulating film. However, since the germanium element contained is small and does not affect the device characteristics, the fifth insulating film may contain germanium element. Subsequently, a hafnium oxide film 210 as a fourth insulating film is formed on the hafnium lanthanum oxide film 205 in the NMOS region and the silicon oxide film 209 in the PMOS region.

  Thereafter, as shown in FIG. 4B, a tungsten nitride film 211 as a gate electrode material is formed on the hafnium oxide film 210 by using a CVD method or the like, and a silicon nitride film 212 is further formed on the tungsten nitride film 211. Then, a mask of the silicon nitride film 212 is formed in the PMOS region by photolithography.

  Subsequently, as shown in FIG. 4C, the tungsten nitride film 211 in the NMOS region is removed with a hydrogen peroxide solution or the like using the mask of the silicon nitride film 212. Further, the silicon nitride film 212 is removed with heated phosphoric acid.

  Next, as shown in FIG. 4D, a tantalum carbide film 213 as a gate electrode material is further formed on the tungsten nitride film 211 in the PMOS region and the hafnium lanthanum oxide film 205 in the NMOS region by using the CVD method or the like, and further the tantalum. A polycrystalline silicon film 214 and a silicon nitride film 215 are sequentially stacked on the carbonized film 213.

  Next, as shown in FIG. 4E, after arsenic, phosphorus, or the like is ion-implanted into the polycrystalline silicon film 214, the gate electrode and the reactive ion etching method, the wet treatment method are used. The gate insulating film is patterned.

  In the present embodiment, the gate insulating film of the NMOSFET has a laminated structure of hafnium oxide film 210 / hafnium lanthanum oxide film 205 / lanthanum silicic oxide film 207 / silicon oxide film 204 from the gate electrode side, and the gate insulating film of the PMOSFET is A laminated structure of hafnium oxide film 210 / silicon oxide film 209 is formed.

  That is, the gate insulating film in the NMOS region is from the silicon substrate 200 side, the first insulating film of the silicon oxide film / second insulating film containing no lanthanum containing hafnium / the third insulating film containing hafnium and lanthanum. The structure is a fourth insulating film containing no insulating film / lanthanum and containing hafnium, and the gate insulating film of the PMOSFET contains the silicon oxide film / lanthanum element as the fifth insulating film from the silicon substrate 200 side. Instead, the structure is a sixth insulating film containing hafnium.

  The gate electrode of the NMOSFET has a laminated structure of the polycrystalline silicon film 214 and the tantalum carbide film 213, and the gate electrode of the PMOSFET has a laminated structure of the polycrystalline silicon film 214, the tantalum carbide film 213, and the tungsten nitride film 211. Become.

  In the present embodiment, the formed film itself is very thin, the interface between the films is unclear, and the constituent elements of each film diffuse to each other in the interface region. It is considered that hafnium is present in the insulating film and a small amount of lanthanum is present in the fourth insulating film. Such permeation of elements due to diffusion occurs structurally, and the permeation elements are not considered to be contained elements.

  According to the manufacturing method of the above-described embodiment, the following effects can be obtained. That is, by forming the hafnium lanthanum oxide film 205 directly on the silicon oxide film 204, deterioration of the film quality can be avoided as compared with the case where the lanthanum oxide film is formed. Although there is a process in which the lanthanum element is exposed on the outermost surface during the manufacturing process in the present embodiment, the hafnium lanthanum oxide film has less hygroscopicity compared to the lanthanum oxide film, and therefore, in a normal process including rework etc. Degradation of the hafnium lanthanum oxide film quality can be avoided sufficiently in the required processing time. In addition, since the hafnium lanthanum oxide film 205 is directly formed on the silicon oxide film 204 in this embodiment, the number of steps can be reduced as compared with the first embodiment.

  Further, since the lanthanum element is not diffused from the cap layer but a film containing only the amount of lanthanum element necessary for threshold reduction is formed on the silicon substrate 200, the threshold voltage can be adjusted accurately. Can do. Further, by growing the SiGe layer 208 in the PMOS region damaged by the etching process, a transistor having a low threshold voltage can be formed for both the NMOSFET and the PMOSFET.

  In addition, since the relative dielectric constant of the hafnium lanthanum oxide film 205 is higher than that of the silicon oxide film 204, the film thickness of the silicon oxide film 208 that is the interface layer of the PMOSFET is larger than the film thickness of the silicon oxide film 204 that is the interface layer of the NMOSFET. When an optimum film thickness ratio is selected by increasing the thickness, the thickness of the electrical gate insulating film can be made the same between the NMOSFET and the PMOSFET.

  Furthermore, if the NMOSFET and the PMOSFET have the same insulating layer structure, the leakage current of the PMOSFET is lower than that of the NMOSFET, so that the thickness of the electrical gate insulating film of the PMOSFET is made thinner than the thickness of the electrical gate insulating film of the NMOSFET. As a result, the leakage current is the same between the NMOSFET and the PMOSFET, and the driving power of the PMOSFET can be improved as compared with the prior art. The specific thickness of the gate insulating film can be adjusted according to the requirements of a desired device.

  Further, in this embodiment, the hafnium oxide film 210 is used for the gate insulating film portion in contact with the gate electrode. A silicon oxide film, a zirconium silicate nitride film, a hafnium zirconium oxide film, a hafnium zirconium oxynitride film, a hafnium zirconium silicate film, a hafnium zirconium silicate nitride film, or the like may be used.

  In this embodiment, since the lanthanum silicic oxide film 207 is formed between the hafnium lanthanum oxide film 205 and the silicon oxide film 204 in the NMOS region, the heating process is performed in the process shown in FIG. When the layer 208 is epitaxially grown, the hafnium lanthanum oxide film 205 and the silicon oxide film 204 in the NMOS region react with each other to form the lanthanum silicic oxide film 207, and may be omitted.

(Third embodiment)
A method for manufacturing a semiconductor device having a CMOSFET according to the third embodiment of the present invention will be described. The present embodiment is characterized in that the gate electrode for work function control of the NMOSFET and the gate electrode for work function control of the PMOSFET are formed of the same material in the first embodiment described above. Since the manufacturing method is the same as that of the first embodiment up to the step of forming the tungsten nitride film 113 of the first embodiment, the same reference numerals are given to the parts having the same configuration, and the description thereof is omitted.

  FIG. 5 is a sectional view showing a manufacturing process of a semiconductor device having a CMOSFET according to the third embodiment of the present invention. FIG. 5A shows a process of forming a tungsten nitride film 113 as a work function control gate electrode of each of the NMOSFET and the PMOSFET. After the tungsten nitride film 113 is formed, as shown in FIG. 5B, a polycrystalline silicon film 316 and a silicon nitride film 317 are sequentially stacked on the tungsten nitride film 113 using a CVD method or the like. Next, as shown in FIG. 5C, after arsenic, phosphorus, or the like is ion-implanted into the polycrystalline silicon film 316, a gate electrode and a reactive ion etching method, a Wet treatment method are used. The gate insulating film is patterned.

  In the present embodiment, the gate insulating film of the NMOSFET has a laminated structure of the hafnium silicate nitride film 111 / hafnium lanthanum oxide film 109 / lanthanum silicate oxide film 112 / silicon oxide film 104 from the gate electrode side, and the gate insulating film of the PMOSFET is Then, a stacked structure of hafnium silicate nitride film 111 / silicon oxide film 110 is formed.

  In other words, the gate insulating film of the NMOSFET has a silicon oxide film that is the first insulating film / the second insulating film that does not contain the hafnium element but contains the lanthanum element / hafnium element and lanthanum element from the silicon substrate 100 side. The third insulating film contained / the fourth insulating film containing hafnium without containing the lanthanum element, and the gate insulating film of the PMOSFET is the silicon oxide which is the fifth insulating film from the silicon substrate 100 side. The structure is a sixth insulating film containing no film / lanthanum element and containing hafnium.

  Further, the gate electrodes of the NMOSFET and PMOSFET both have a laminated structure of the polycrystalline silicon film 316 and the tungsten nitride film 113.

  In the present embodiment, the formed film itself is very thin, the interface between the films is unclear, and the constituent elements of each film diffuse to each other in the interface region. It is considered that hafnium is present in the insulating film and a small amount of lanthanum is present in the fourth insulating film. Such permeation of elements due to diffusion occurs structurally, and the permeation elements are not considered to be contained elements.

  In this embodiment, the tungsten nitride film is used as the work function control gate electrode of each of the NMOSFET and the PMOSFET. However, a tantalum carbide film, a titanium nitride film, or the like may be used in addition to the tungsten nitride film.

  According to the manufacturing method of the present embodiment described above, the following effects can be obtained. By forming the gate electrode for controlling the work function of the NMOSFET and the gate electrode for controlling the work function of the PMOSFET using the same material, it is not necessary to make each electrode material separately. Therefore, in addition to the effects of the first embodiment, the number of manufacturing steps can be reduced as compared with the first embodiment.

(Fourth embodiment)
A method for manufacturing a semiconductor device having a CMOSFET according to the fourth embodiment of the present invention will be described. This embodiment is characterized in that the gate electrode for work function control of the NMOSFET and the gate electrode for work function control of the PMOSFET are formed of the same material in the second embodiment described above. Further, since the manufacturing method is the same as that of the first embodiment up to the step of forming the tungsten nitride film 211 of the second embodiment, the same reference numerals are given to the parts having the same configuration, and the description is omitted.

  FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor device having a CMOSFET according to the fourth embodiment of the present invention. FIG. 6A shows a process of forming a tungsten nitride film 211 as a work function control gate electrode of each of the NMOSFET and the PMOSFET. After the formation of the tungsten nitride film 211, as shown in FIG. 6B, a polycrystalline silicon film 414 and a silicon nitride film 415 are sequentially stacked on the tungsten nitride film 211 using a CVD method or the like. Next, as shown in FIG. 6C, after arsenic, phosphorus, or the like is ion-implanted into the polycrystalline silicon film 414, a gate electrode and a reactive ion etching method, a Wet treatment method are used. The gate insulating film is patterned.

  In the present embodiment, the gate insulating film of the NMOSFET has a laminated structure of hafnium oxide film 210 / hafnium lanthanum oxide film 205 / lanthanum silicic oxide film 207 / silicon oxide film 204 from the gate electrode side, and the gate insulating film of the PMOSFET is A laminated structure of hafnium oxide film 210 / silicon oxide film 209 is formed.

  That is, the gate insulating film in the NMOS region is from the silicon substrate 200 side, the first insulating film of the silicon oxide film / second insulating film containing no lanthanum containing hafnium / the third insulating film containing hafnium and lanthanum. The structure is a fourth insulating film containing no insulating film / lanthanum and containing hafnium, and the gate insulating film of the PMOSFET contains the silicon oxide film / lanthanum element as the fifth insulating film from the silicon substrate 200 side. Instead, the structure is a sixth insulating film containing hafnium.

  Further, the gate electrodes of the NMOSFET and PMOSFET both have a laminated structure of a polycrystalline silicon film 414 and a tungsten nitride film 211.

  In the present embodiment, the formed film itself is very thin, the interface between the films is unclear, and the constituent elements of each film diffuse to each other in the interface region. It is considered that hafnium is present in the insulating film and a small amount of lanthanum is present in the fourth insulating film. Such permeation of elements due to diffusion occurs structurally, and the permeation elements are not considered to be contained elements.

  In this embodiment, the tungsten nitride film is used as the work function control gate electrode of each of the NMOSFET and the PMOSFET. However, a tantalum carbide film, a titanium nitride film, or the like may be used in addition to the tungsten nitride film.

  According to the manufacturing method of the present embodiment described above, the following effects can be obtained. By forming the gate electrode for controlling the work function of the NMOSFET and the gate electrode for controlling the work function of the PMOSFET using the same material, it is not necessary to make each electrode material separately. Therefore, in addition to the effects of the second embodiment, the number of manufacturing steps can be reduced as compared with the second embodiment.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing which showed typically a part of manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention.

Explanation of symbols

100, 200 Single crystal silicon substrate 101, 201 Element isolation 102, 202 N type diffusion region 103, 203 P type diffusion region 104, 110, 204, 209 Silicon oxide film 105 Lanthanum oxide film 106, 210 Hafnium oxide film 107, 206 Resist 108, 208 Single crystal SiGe layers 109, 205 Hafnium lanthanum oxide film 111 Hafnium silicate nitride film 112, 207 Lanthanum silicate film 113, 211 Tungsten nitride film 114, 117, 212, 215, 317, 415 Silicon nitride film 115, 213 Tantalum Carbonized film 116, 214, 316, 414 Polycrystalline silicon film

Claims (5)

A semiconductor substrate having isolated P-type and N-type regions;
A first insulating film made of a silicon oxide film or a silicon oxynitride film formed on the P-type region, and a second insulating film containing lanthanum without containing hafnium formed on the first insulating film A third insulating film containing hafnium and lanthanum formed on the second insulating film, and a fourth insulating film containing hafnium without containing lanthanum formed on the third insulating film. A first gate insulating film having a stacked structure,
A silicon germanium layer formed on the N-type region;
A fifth insulating film made of a silicon oxide film or a silicon oxynitride film formed on the silicon germanium layer, and a sixth insulating film containing hafnium without containing lanthanum formed on the fifth insulating film A second gate insulating film of a laminated structure having
A gate electrode formed on each of the first and second gate insulating films;
A semiconductor device comprising: Forming a P-type and an N-type region that are insulated and separated by an element isolation region on a main surface of the semiconductor substrate;
Forming a first insulating film made of a silicon oxide film or a silicon oxynitride film on the P-type and N-type regions;
A step of sequentially forming a lanthanum oxide film and a hafnium insulating film containing hafnium on the first insulating film;
Sequentially removing the hafnium insulating film, the lanthanum oxide film, and the first insulating film on the N-type region to expose the N-type region;
Reacting the lanthanum element of the lanthanum oxide film on the P-type region with the hafnium element of the hafnium insulating film to form a third insulating film containing hafnium and lanthanum;
Forming a silicon germanium layer on the exposed N-type region and then forming a fifth insulating film made of a silicon oxide film or a silicon oxynitride film on the silicon germanium layer;
Forming a fourth insulating film containing hafnium on the third insulating film and the fifth insulating film;
Forming a second insulating film not containing hafnium but containing lanthanum between the first insulating film and the third insulating film on the P-type region;
Forming a gate electrode material on the fourth insulating film;
Processing the gate electrode material and the first to fifth insulating films to form the first gate insulating film and the first having a laminated structure having the first to fourth insulating films on the P-type region. A second electrode having a stacked structure including a gate electrode formed on the gate insulating film, a fifth insulating film formed on the N-type region, and a sixth insulating film formed by processing the fourth insulating film. Forming a gate electrode on the gate insulating film and the second insulating film;
A method for manufacturing a semiconductor device, comprising:   3. The method of manufacturing a semiconductor device according to claim 2, wherein the second insulating film is formed by a heating process when forming the fourth insulating film. Forming a P-type and an N-type region isolated by an element isolation region on a main surface of a semiconductor substrate;
Forming a first insulating film made of a silicon oxide film or a silicon oxynitride film on the P-type and N-type regions;
Forming a third insulating film containing hafnium and lanthanum on the first insulating film;
Sequentially removing the third insulating film and the first insulating film on the N-type region to expose the N-type region;
Forming a second insulating film not containing hafnium but containing lanthanum between the first insulating film and the third insulating film in the P-type region;
Forming a silicon germanium layer on the exposed N-type region, and then forming a fifth insulating film made of a silicon oxide film or a silicon oxynitride film on the silicon germanium layer;
Forming a fourth insulating film containing hafnium on the third insulating film and the fifth insulating film;
Forming a gate electrode material on the fourth insulating film;
Processing the gate electrode material and the first to fifth insulating films to form a first gate insulating film having the first to fourth insulating films on the P-type region and the first insulating film A second gate having a laminated structure in which a gate electrode is formed on the gate insulating film, and the fifth insulating film and a sixth insulating film obtained by processing the fourth insulating film are formed on the N-type region; Forming a gate electrode on the insulating film and the second insulating film;
A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein the second insulating film is formed by heat-treating the third insulating film after forming the third insulating film.

Images