JP2007329760A - Programmable logic device, circuit information input controller, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a programmable logic device which can make a communication unit of data not to become a bottleneck for the processing performance as a whole, without having to exclusively prepare a special circuit for data transfer, and can simultaneously assure independence of design among circuits which is the same level for recording in a memory. <P>SOLUTION: When a logic circuit A and a logic circuit B continuously execute in a processing circuit unit (S1 to S5), after execution finish of the logic circuit A (Yes in S6), the processing circuit unit switches to a logic circuit T for data transfer, in order to transfer data used by any of the logic circuit A and the logic circuit B by the control of a circuit information input control unit (S7). After execution finishing of data transfer by the logic circuit T ("Yes" in S8), the processing circuit unit switches to the logic circuit B by the control of the circuit information input control unit (S9 to S10). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a programmable logic device capable of dynamically changing a program, a circuit information input control device, and a semiconductor device.

  As a method for transferring data between programs in a programmable logic device capable of dynamically changing a program, there is a technique described in Patent Document 1. According to the technique described in Patent Document 1, data is transferred via a shared memory outside the programmable logic device. More specifically, the data output by the first logic circuit is stored once in an external shared memory, and when the second logic circuit is executed, the transfer is realized by reading from the shared memory. It is. That is, when communication of data with the external memory is concentrated on the input / output part, the communication part becomes a dominant element of the performance of the entire system.

  As described above, the method of transferring data via the shared memory increases the degree of freedom in circuit design by always recording the transfer data in the memory. Therefore, independent design is possible for each logic circuit. Although optimization for each circuit is easy, the memory access speed is limited.

  Further, according to Patent Document 2 and Non-Patent Document 1, as a method for transferring internal data to internal data of a programmable logic device, the arrangement of data transferred by two logic circuits is assigned to the same memory element. In this way, when the same storage device is assigned to two logic circuits, data can be transferred by changing the logic circuit.

JP 2001-202236 A Japanese Patent No. 3674515 August 25, 2005, published by Ohm Co., Ltd. Toshinori Sueyoshi and Hideharu Amano “Reconfigurable System” p189-p208 “Chapter 7 NEC Electronics DRP”

  However, according to the techniques described in Patent Document 2 and Non-Patent Document 1, since the memory allocation is physically limited by two logic circuits, the circuit operation speed of the logic circuit for the purpose of improving communication performance. In addition, it is difficult to optimize the circuit scale and the like, and to improve the reusability of using the designed circuit as a part for other purposes.

  The present invention has been made in view of the above, and it is possible to prevent a data communication portion from becoming a bottleneck of the overall processing performance without preparing a special circuit for data transfer. An object of the present invention is to provide a programmable logic device, a circuit information input control device, and a semiconductor device capable of ensuring the same degree of design independence between circuits as is recorded in a memory.

  In order to solve the above-described problems and achieve the object, a programmable logic device according to the present invention includes a processing circuit unit capable of realizing a plurality of logic circuits by selectively providing a plurality of circuit information, and the logic circuit. A circuit information setting memory in which circuit information to be realized is set is connected to the processing circuit unit via a signal line, and in the processing circuit unit according to the circuit information set in the circuit information setting memory A circuit information input control unit that controls switching of the logic circuit, wherein the circuit information input control unit requests a change to the second logic circuit while the processing circuit unit is executing the first logic circuit. The data transfer logic circuit for transferring data used by either the first logic circuit or the second logic circuit after the processing circuit unit finishes executing the first logic circuit. The switching, after the processing circuit unit finishes execution of the data transfer by the logic circuit for the data transfer is switched to the second logic circuit.

  Further, the circuit information input control device of the present invention is connected to a processing circuit unit capable of realizing a plurality of logic circuits by selectively providing a plurality of circuit information via a signal line, and is set in a circuit information setting memory. A circuit information input control device that controls switching of each logic circuit in the processing circuit unit in accordance with the circuit information, wherein the processing circuit unit executes a second logic during execution of the first logic circuit. When receiving a change request to the circuit, the processing circuit unit transfers data used by either the first logic circuit or the second logic circuit after the execution of the first logic circuit is completed. After switching to the data transfer logic circuit, the processing circuit unit switches to the second logic circuit after completing the execution of data transfer by the data transfer logic circuit.

  A semiconductor device according to the present invention includes a programmable logic device according to any one of claims 1 to 6, a control device for controlling the programmable logic device, and each logic circuit in a processing circuit section of the programmable logic device. And a storage device for storing circuit information according to the above.

  According to the present invention, it is possible to prevent a communication part of data from becoming a bottleneck of the overall processing performance without preparing a special circuit for data transfer, and to the same extent as recording in a memory. The independence of the design between the circuits can be ensured.

  Exemplary embodiments of a programmable logic device, a circuit information input control device, and a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS.

[Programmable logic device configuration]
FIG. 1 is a block diagram showing a semiconductor device 100 including a programmable logic device 50 according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 includes a programmable logic device 50 that can dynamically change a program. Connected to the programmable logic device 50 are a host processor 10 which is a control device for controlling the programmable logic device 50 and a main memory 20 which is a storage device storing a plurality of circuit information and data used for processing. Has been. The circuit information of the logic circuit stored in the main memory 20 is prepared in advance by the user, and an identifier uniquely determined by the user is assigned to each logic circuit.

  As shown in FIG. 1, the programmable logic device 50 is configured by connecting a processing circuit unit 51 and a circuit information input control unit (circuit information input control device) 52 by a circuit information input signal line 53.

  First, the processing circuit unit 51 constituting the programmable logic device 50 will be described. FIG. 2 is a circuit diagram exemplarily showing the configuration of the processing circuit unit 51. As shown in FIG. 2, the processing circuit unit 51 includes a logic block (LB) 51L such as a look-up table, a switch block (SB) 51S for configuring a data path, and data used for processing inside the logic circuit. And a memory (MEM) 51M for storing. The logic block (LB) 51L, the switch block (SB) 51S, and the memory (MEM) 51M are connected by a circuit information input signal line 53. In FIG. 2, the square not shown has basically the same structure as the switch block (SB) 51S. However, in FIG. 2, what is indicated as SB is different in terms of the number of input / output ports.

  FIG. 3 is a schematic diagram exemplarily showing the configuration of the logic block 51L. As shown in FIG. 3, the logic block 51L includes a memory 51LM that stores the contents of the truth table, and a selector 51LS that outputs the contents of the memory 51LM using an input signal as a selector signal. Realize.

  Note that the configuration of the logic block 51L shown in FIG. 3 is an example, and the logic block 51L can be an arithmetic device that can perform arithmetic operations and logical operations and has a memory that stores information defining processing. Is not specified. For example, an ALU (Arithmetic and Logic Unit) having a processor and an instruction memory may be used. Also, it is not necessary to process arbitrary logic.

  FIG. 4 is a schematic diagram exemplarily showing the configuration of the switch block 51S. As shown in FIG. 4, the switch block 51S includes switches 51SS arranged in a grid and a memory 51SM for controlling ON / OFF of the switch 51SS.

  Note that the configuration of the switch block 51S shown in FIG. 4 is an example, and the switch block 51S only needs to have a memory for storing route information and means for communicating with a plurality of sets at the same time.

  That is, in the processing circuit unit 51 of the programmable logic device 50, circuit information is expressed via the circuit information input signal line 53 from the outside with respect to the memory 51LM of the logic block 51L and the memory 51SM of the switch block 51S as described above. By inputting the data, a logic circuit defined by the user is realized.

  Next, the circuit information input control unit 52 will be described. The circuit information input control unit 52 controls switching of logic circuits executed by the processing circuit unit 51. Here, FIG. 5 is a block diagram showing a configuration of the circuit information input control unit 52. As shown in FIG. 5, the circuit information input control unit 52 includes a memory 52Ma that stores an identifier of a currently executed logic circuit, a memory 52Mb that stores an identifier of a logic circuit to be executed next, a memory 52Ma, and a memory 52Mb. The table 52T for obtaining the identifier of the transfer logic circuit from the identifier stored in the configuration, the configuration memory 54, which is a circuit information setting memory in which circuit information of the logic circuit is set, and the state of the circuit information input control unit 52 And a controller 52P for controlling the transition.

  With the configuration described above, the circuit information input control unit 52 is configured to store circuit information of the logic circuit from the main memory 20 to the configuration memory 54 in accordance with a signal such as a control command transmitted from the host processor 10 or an identifier of the logic circuit to be changed. Initialization processing such as transfer and transfer of table information from the main memory 20 to the table 52T is performed. The circuit information input control unit 52 also performs logic circuit change processing such as transfer of circuit information of the logic circuit from the configuration memory 54 to the processing circuit unit 51 and control of switching of the logic circuit executed by the processing circuit unit 51. .

  When the logic circuit is changed, circuit information output from the configuration memory 54 is written to the memory 51LM of the logic block 51L and the memory 51SM of the switch block 51S via the circuit information input signal line 53.

[Processing with programmable logic devices]
Next, as an example of processing in the programmable logic device 50, a case where the following program is processed will be described.

for (int i = 0; i <1000; i ++) {
// Process in logic circuit A z = x + y;
a = IN + b;
b = IN >>z;
}
for (int i = 0; i <1000; i ++) {
// Process with logic circuit B
OUT = a + b;
c = IN <<a;
d = IN + c;
}

  When the above program is executed by the processing circuit unit 51 of the programmable logic device 50, for example, the logic circuit A is processed by the logic circuit shown in FIG. 6, and the logic circuit B is processed by the logic circuit shown in FIG. To do. In the logic circuit A shown in FIG. 6 and the logic circuit B shown in FIG. 7, the variables a and b in the program are respectively assigned to physically different memories 51M.

  In the programmable logic device 50 according to the present embodiment, for the purpose of efficiently performing processing in such a case, as shown in FIG. A logic circuit T for data transfer, which is a third logic circuit, is executed between the logic circuits B, which are circuits.

  FIG. 9 is a circuit diagram showing the logic circuit T. As shown in FIG. 9, the logic circuit T transfers data used by both the logic circuit A and the logic circuit B. Here, the logic circuit T transfers only the variables a and b, and does not transfer x, y, and z. In addition, since only transfer is performed, a logic circuit can be realized without using the logic block 51L.

  FIG. 10 is a time chart when the above program is executed. As shown in FIG. 10, the logic circuit A and the logic circuit B each execute 1000 cycles, but the logic circuit T completes the processing in one cycle because it only transfers the variables a and b.

[Method of changing logic circuit by circuit information input controller]
In changing the logic circuit A from the currently executed logic circuit A to the logic circuit B, the circuit information input control unit 52 first determines the logic circuit A that is currently processing, and the logic circuit B requested by the host processor 10. The circuit information of the logic circuit T that performs data transfer between them is written into the processing circuit unit 51 and the logic circuit T is executed. Subsequently, the circuit information of the logic circuit B is written into the processing circuit unit 51, and after the processing of the logic circuit T is completed, the logic circuit B is executed. For identifying the end of the logic circuit T, the number of processing cycles may be designated from the outside, or a control signal for informing the end of processing may be provided.

  FIG. 11 is a flowchart showing the flow of the logic circuit changing process in the programmable logic device 50. In the following, the procedure for changing the logic circuit is shown in accordance with the flowchart of FIG. It is assumed that circuit information of a logic circuit that is requested to be changed by the host processor 10 is stored in the configuration memory 54 in advance. In other words, before making a logic circuit change request, circuit information is written in the configuration memory 54 in advance.

  As shown in FIG. 11, when the circuit information input control unit 52 of the programmable logic device 50 receives the REQ signal for changing the logic circuit of the programmable logic device 50 transmitted from the host processor 10, the logic circuit can be changed. If so, an ACK signal is transmitted to the host processor 10 to start changing the logic circuit (step S1). If the logic circuit cannot be changed, it waits until it can be changed. Upon receiving the ACK signal from the circuit information input control unit 52, the host processor 10 transmits the changed logic circuit identifier B to the circuit information input control unit 52.

  Upon receiving the changed logic circuit identifier B (step S2), the circuit information input control unit 52 receives the currently executed logic circuit identifier A and the changed logic circuit identifier B as inputs, and performs circuit information input control. By retrieving the table 52T in the unit 52, the identifier T of the logic circuit for data transfer is obtained (step S3). However, if there is no currently executing logic circuit immediately after resetting, a logic circuit for data transfer is not necessary.

  FIG. 12 is a schematic diagram showing the structure of the table 52T. As shown in FIG. 12, the table 52T has a structure in which the identifier of the logic circuit currently being executed, the identifier of the logic circuit after the change, and the identifier of the logic circuit for data transfer are associated with each other.

  When the circuit information input control unit 52 obtains the identifier T of the logic circuit for data transfer, the circuit information input control unit 52 reads the circuit information of the logic circuit T from the configuration memory 54, The circuit information of the logic circuit T is transferred by writing to the logic block 51L and the switch block 51S (step S4).

  Subsequently, the circuit information input control unit 52 reads the circuit information of the logic circuit B from the configuration memory 54, and applies the logic block 51 </ b> L and the switch block 51 </ b> S inside the processing circuit unit 51 via the circuit information input signal line 53. The circuit information of the logic circuit B is transferred (step S5).

  Next, when the processing of the currently executed logic circuit A is completed (Yes in step S6), execution of the processing of the logic circuit T is started (step S7).

  When the process of the logic circuit T is completed (Yes in step S8), it is determined whether or not the transfer of the circuit information of the logic circuit B is completed (step S9).

  When it is determined that the transfer of the circuit information of the logic circuit B is completed (Yes in step S9), the execution of the process of the logic circuit B is started (step S10), and an ACK signal is transmitted to the host processor 10.

  When the host processor 10 receives the ACK signal, the logic circuit change of the programmable logic device 50 is completed (step S11).

  As described above, according to the present embodiment, when the first logic circuit (logic circuit A) and the second logic circuit (logic circuit B) are successively executed in the processing circuit unit 51, the processing circuit unit 51 is used. After the execution of the first logic circuit (logic circuit A) is completed, both the first logic circuit (logic circuit A) and the second logic circuit (logic circuit B) are used under the control of the circuit information input control unit 52. Circuit information input control after the processing circuit unit 51 finishes executing data transfer by the data transfer logic circuit (logic circuit T). By switching to the second logic circuit (logic circuit B) under the control of the unit 52, the data communication portion does not become a bottleneck in the overall processing performance without preparing a special circuit for data transfer. You It is possible, it is possible to secure the design of independence between circuits of the same degree as to record in the memory.

  Here, a first modification of the programmable logic device 50 will be described. FIG. 13 is a schematic diagram showing a logic block 51L of the programmable logic device 50 of the first modification. As shown in FIG. 13, the first modification of the logic block 51L includes a selector 61 and a memory 62 on the circuit information input signal line 53 in addition to the configuration shown in FIG.

  The selector 61 selects circuit information to be input to the memory 51 LM from information transmitted on the circuit information input signal line 53 and information stored in the memory 62. The memory 62 is preliminarily input with circuit information used when executing a logic circuit for data transfer. The memory 62 may input circuit information at the time of manufacture using a ROM, or may input circuit information at the time of device activation using a RAM.

  In addition, by connecting the control signal of the selector 61 to the circuit information input signal line 63, the circuit information is less than that for programming to determine all operations, compared to the case where circuit information is input only to the switch block 51S. The logic block 51L can be used in a logic circuit for data transfer. More specifically, this is because the circuit information can be expressed with a smaller data size for information specifying the selector signal of the selector 61 than for all the information of one logic block 51L. In FIG. 13, 16 bits are required when circuit information is directly input to all the memory cells in the memory 51LM. However, in order to input circuit information stored in the memory 62 in advance, the signal information on the signal line 63 is used. Since it is sufficient to input 1-bit data for controlling the selector 61 to the register, circuit information can be reduced.

  The programmable logic device that stores the circuit information of the logic circuit for data transfer in the main memory 20 by having the memory 62 in which circuit information for realizing the logic circuit for data transfer is input in advance. Since it can be reduced from the circuit information of the entire 50, the time required for circuit information input can be reduced.

  Next, a second modification of the programmable logic device 50 will be described. FIG. 14 is a schematic diagram showing a logic block 51L of the programmable logic device 50 of the second modified example. As shown in FIG. 14, the second modification of the logic block 51L has a memory 51LM ′ in addition to the memory 51LM, and is executing a logic circuit of circuit information stored in one memory 51LM. The other memory 51LM ′ has a structure capable of inputting circuit information.

  FIG. 15 is a schematic diagram showing a switch block 51S of the programmable logic device 50 of the second modification. As shown in FIG. 15, the modified example of the switch block 51S has a memory 51SM ′ in addition to the memory 51SM, like the modified example of the logic block 51L shown in FIG. And the circuit information can be input to the other memory 51SM ′ while the logic circuit of the circuit information stored in the one memory 51SM is being executed.

  In the case of such a processing circuit unit 51 having the logic block 51L and the switch block 51S, even if information on a logic circuit to be executed next is input while a certain logic circuit is being executed, the circuit operation being executed is not affected. .

  Thereby, the processing circuit unit 51 provides a plurality of (here, two sets) memories redundantly in the logic block 51L and the switch block 51S, thereby executing the data transfer logic circuit (logic circuit T). By making it possible to input circuit information for realizing the second logic circuit (logic circuit B), the time required for circuit information input can be reduced.

  Further, since the circuit information for realizing the data transfer logic circuit (logic circuit T) is composed of only the circuit information for realizing the communication path, the time required for circuit information input can be further reduced.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

[Programmable logic device configuration]
FIG. 16 is a block diagram showing a semiconductor device 200 including the programmable logic device 150 according to the second embodiment of the present invention. As shown in FIG. 16, the semiconductor device 200 of this embodiment includes a programmable logic device 150 that can dynamically change a program. The programmable logic device 150 is connected to a host processor 10 for controlling the programmable logic device 150 and a main memory 20 in which a plurality of circuit information and data used for processing are stored.

  As shown in FIG. 16, the programmable logic device 150 is configured by connecting a processing circuit unit 151 and a circuit information input control unit 152 through two types of circuit information input signal lines 153A and 153B.

  First, the processing circuit unit 151 constituting the programmable logic device 150 will be described. FIG. 17 is a circuit diagram exemplarily showing the configuration of the processing circuit unit 151. As shown in FIG. 17, the processing circuit unit 151 includes a logic block (LB) 51L, a switch block (SB) 51S, and a memory (MEM) 51M, as in the processing circuit unit 51 of the first embodiment. It is configured. However, while one type of circuit information input signal line 53 is connected to the processing circuit unit 51 of the first embodiment, the processing circuit unit 151 is a logic that is a block used for other than data transfer. The circuit information input signal line 153A connected only to the block 51L and the circuit information input signal line 153B connected only to the switch block 51S that is a block used for data transfer are different. With this structure, the switch block 51S and the logic block 51L can be independently controlled without substantially increasing the hardware resources of the processing circuit unit 151.

  The circuit information input control unit 152 controls switching of logic circuits executed by the processing circuit unit 151. FIG. 18 is a block diagram illustrating a configuration of the circuit information input control unit 152. As illustrated in FIG. 18, the circuit information input control unit 152 includes a memory 52Ma that stores an identifier of a currently executed logic circuit, a memory 52Mb that stores an identifier of a logic circuit to be executed next, a memory 52Ma, and a memory 52Mb. The table 52T for obtaining the identifier of the logic circuit for transfer from the identifier stored in the memory, the configuration memory 154L for storing circuit information relating to the logic block 51L of the logic circuit, and the circuit information relating to the switch block 51S of the logic circuit are saved. Configuration memory 154S, and a controller 52P for controlling the state transition of the circuit information input control unit 52.

  With the above-described configuration, the circuit information input control unit 152 performs logic processing from the main memory 20 to the configuration memory 154L or the configuration memory 154S in accordance with a signal such as a control command transmitted from the host processor 10 or an identifier of the logic circuit to be changed. Initialization processing such as transfer of circuit information of the circuit and transfer of table information from the main memory 20 to the table 52T is performed. Further, the circuit information input control unit 152 transfers logic circuit information from the configuration memory 154L or the configuration memory 154S to the processing circuit unit 151 and controls logic circuit switching executed by the processing circuit unit 151. Circuit change processing is also performed.

  The output of the configuration memory 154L is connected to the circuit information input signal line 153A, and the output of the configuration memory 154S is connected to the circuit information input signal line 153B.

[Procedure for changing logic circuit]
When changing the logic circuit A from the currently executed logic circuit A to the logic circuit B, the circuit information input control unit 152 first determines the logic circuit A that is currently performing processing, the logic circuit B requested by the host processor 10, and Circuit information of the logic circuit T that performs data transfer between them is written into the processing circuit unit 151 and the logic circuit T is executed. Subsequently, the circuit information of the logic circuit B is written into the processing circuit unit 151, and after the processing of the logic circuit T is completed, the logic circuit B is executed.

  FIG. 19 is a flowchart showing the flow of logic circuit change processing in the programmable logic device 150. In the following, the procedure for changing the logic circuit is shown in accordance with the flowchart of FIG. However, as in the first embodiment, it is assumed that circuit information of a logic circuit that is requested to be changed by the host processor 10 is stored in the configuration memory 154L or the configuration memory 154S in advance.

  As illustrated in FIG. 19, when the circuit information input control unit 152 of the programmable logic device 150 receives the REQ signal for changing the logic circuit of the programmable logic device 50 transmitted from the host processor 10, the logic circuit can be changed. If so, an ACK signal is transmitted to the host processor 10 to start changing the logic circuit (step S1). If the logic circuit cannot be changed, it waits until it can be changed. When receiving the ACK signal from the circuit information input control unit 152, the host processor 10 transmits the changed logic circuit identifier B to the circuit information input control unit 152.

  When the circuit information input control unit 152 receives the identifier B of the changed logic circuit (step S2), the circuit information input control unit 152 receives the identifier A of the currently executed logic circuit and the identifier B of the changed logic circuit as inputs. By retrieving the table 52T in the unit 152, the identifier T of the data transfer logic circuit is obtained (step S3). However, if there is no currently executing logic circuit immediately after resetting, a logic circuit for data transfer is not necessary.

  When the circuit information input control unit 152 obtains the identifier T of the logic circuit for data transfer, the circuit information input control unit 152 reads the circuit information of the switch block 51S of the logic circuit T from the configuration memory 154S and processes it via the circuit information input signal line 153B. The circuit information of the logic circuit T is transferred by writing to the switch block 51S in the circuit unit 151 (step S21).

  At the same time, the circuit information input control unit 152 reads the circuit information of the logic block 51L of the logic circuit B from the configuration memory 154L, and sends the circuit information to the logic block 51L inside the processing circuit unit 151 via the circuit information input signal line 153A. The circuit information of the logic circuit B is transferred by writing (step S22).

  In addition, after transferring the circuit information of the logic circuit T in step S21, the circuit information input control unit 152 reads the circuit information of the switch block 51S of the logic circuit B from the configuration memory 154S, and passes through the circuit information input signal line 153B. Then, the circuit information of the logic circuit B is transferred by writing to the switch block 51S in the processing circuit unit 151 (step S23).

  Next, when the processing of the currently executed logic circuit A is completed (Yes in step S6), execution of the processing of the logic circuit T is started only for the switch block 53S of the processing circuit unit 151 (step S7). .

  When the process of the logic circuit T is completed (Yes in step S8), it is determined whether or not the transfer of the circuit information of the logic circuit B is completed (step S9).

  When it is determined that the transfer of the circuit information of the logic circuit B is completed (Yes in step S9), the execution of the process of the logic circuit B is started (step S10), and an ACK signal is transmitted to the host processor 10.

  When the host processor 10 receives the ACK signal, the logic circuit change of the programmable logic device 50 is completed (step S11).

  Thus, according to the present embodiment, the signal line connecting the processing circuit unit 151 and the circuit information input control unit 152 is the first signal line 153B connected only to the switch block 51S of the processing circuit unit 151. And the second signal line 153A connected only to the logic block 51L of the processing circuit unit 151, and the circuit information input control unit 152 stores a plurality of circuit information for storing circuit information. The circuit information input control unit 152 reads the circuit information of the switch block 51S of the data transfer logic circuit (logic circuit T) from the memory 154S that stores one circuit information, and the first information By writing to the switch block 51S inside the processing circuit unit 151 via the signal line 153B, a data transfer logic circuit (logic The circuit information of the circuit T) is transferred, and the circuit information of the logic block 51L of the second logic circuit (logic circuit B) is read from the memory 154L for storing other circuit information, and is transmitted via the second signal line 153A. The circuit information of the second logic circuit (logic circuit B) is transferred by writing to the logic block 51L inside the processing circuit unit 151. As a result, different control is possible for each (when the signal line 153B, which is a system for inputting only information necessary for the logic circuit T, and 153A, which is a system for inputting other information, is used as a signal. Since the configuration information of the logic circuit B can be input at 153A while the configuration information of the logic circuit T is input at the line 153B), the switch block 51S does not substantially increase the hardware resources of the processing circuit unit 151. And the logic block 51L can be controlled independently, and the processing efficiency can be improved.

It is a block diagram showing a semiconductor device provided with the programmable logic device concerning a 1st embodiment of the present invention. It is a circuit diagram which shows the composition of a processing circuit part exemplarily. It is a schematic diagram which shows the structure of a logic block exemplarily. It is a schematic diagram which shows the structure of a switch block exemplarily. It is a block diagram which shows the structure of a circuit information input control part. 2 is a circuit diagram showing a logic circuit A. FIG. 3 is a circuit diagram showing a logic circuit B. FIG. It is a schematic diagram showing a logic circuit T for data transfer. 2 is a circuit diagram showing a logic circuit T. FIG. It is a time chart at the time of running a program. It is a flowchart which shows the flow of the logic circuit change process in a programmable logic device. It is a schematic diagram which shows the structure of a table. It is a schematic diagram which shows the logic block of the programmable logic device of a 1st modification. It is a schematic diagram which shows the logic block of the programmable logic device of a 2nd modification. It is a schematic diagram which shows the switch block of the programmable logic device of a 2nd modification. It is a block diagram which shows the semiconductor device provided with the programmable logic device concerning the 2nd Embodiment of this invention. It is a circuit diagram which shows the composition of a processing circuit part exemplarily. It is a block diagram which shows the structure of a circuit information input control part. It is a flowchart which shows the flow of the logic circuit change process in a programmable logic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Control apparatus 20 Memory | storage device 50,150 Programmable logic device 51,151 Processing circuit part 52,152 Circuit information input control part, Circuit information input control apparatus 53 Signal line 62 Memory 100, 200 Semiconductor device 153B 1st signal line 153A 1st 2 signal lines 54, 154L, 154S circuit information setting memory A first logic circuit B second logic circuit T data transfer logic circuit

Claims (8)

A processing circuit unit capable of realizing a plurality of logic circuits by selectively giving a plurality of circuit information;
Circuit information setting memory in which circuit information for realizing the logic circuit is set;
A circuit information input control unit that is connected to the processing circuit unit via a signal line and controls switching of the logic circuit in the processing circuit unit in accordance with the circuit information set in the circuit information setting memory When,
With
When the processing circuit unit receives a change request to the second logic circuit while the processing circuit unit is executing the first logic circuit, the circuit information input control unit is configured such that after the processing circuit unit finishes executing the first logic circuit, , Switching to a data transfer logic circuit for transferring data used by either the first logic circuit or the second logic circuit, and the processing circuit unit executing data transfer by the data transfer logic circuit After finishing the above, switching to the second logic circuit,
A programmable logic device characterized by that. In addition to the circuit information setting memory, the processing circuit unit includes a memory in which the circuit information for realizing one or a plurality of the logic circuits usable in the data transfer logic circuit is input in advance. ,
The programmable logic device according to claim 1. The processing circuit unit inputs the circuit information for realizing the second logic circuit while executing the data transfer logic circuit by providing the logic block and the switch block with a plurality of redundant memories. Possible,
The programmable logic device according to claim 1. The circuit information for realizing the data transfer logic circuit is composed only of circuit information for realizing a communication path.
The programmable logic device according to claim 3. The signal line connecting the processing circuit unit and the circuit information input control unit is not only the first signal line connected to the block used for data transfer of the processing circuit unit and the data transfer of the processing circuit unit. A second signal line connected only to a block to be used, and a plurality of the circuit information setting memories,
The circuit information input control unit reads out circuit information of a block used for the data transfer of the data transfer logic circuit from one circuit information setting memory, and the circuit information input control unit includes an internal circuit of the processing circuit unit via the first signal line. The circuit information of the data transfer logic circuit is transferred by writing to the block used for the data transfer, and the circuit information of the block used for other than the data transfer of the second logic circuit is set to the other circuit information setting. Read circuit information of the second logic circuit by reading from the memory and writing to a block used for other than the data transfer inside the processing circuit unit via the second signal line,
The programmable logic device according to claim 1. The block used for the data transfer is a switch block of the processing circuit unit, and the block used for other than the data transfer is a logic block of the processing circuit unit.
The programmable logic device according to claim 5. The processing circuit unit is connected to a processing circuit unit capable of realizing a plurality of logic circuits by selectively providing a plurality of circuit information via a signal line, and according to the circuit information set in a circuit information setting memory. A circuit information input control device for controlling switching of each of the logic circuits in
When the processing circuit unit receives a request to change to the second logic circuit during execution of the first logic circuit, the processing circuit unit, after completing the execution of the first logic circuit, After switching to a data transfer logic circuit for transferring data to be used by either of the second logic circuits, the processing circuit unit ends execution of data transfer by the data transfer logic circuit, and then the second logic circuit Switch to the logic circuit
A circuit information input control device. A programmable logic device according to any one of claims 1 to 6;
A control device for controlling the programmable logic device;
A storage device for storing circuit information related to each logic circuit in the processing circuit unit of the programmable logic device;
A semiconductor device comprising:

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