JP2007234750A - Bonded structure, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bonded structure which makes the productivity high by uniformly depositing a plating metal for bonding chips. <P>SOLUTION: A wafer 2 having a plurality of first chips 4 each having cathodes 19a, 19b, and anodes 20a, 20b disposed near them and a wafer 3 having a plurality of second chips 5 each having cathodes 34a, 34b, are bonded to form a bonded structure. With the chips 4, 5 dipped in an electrolytic plating solution, a current is flowed between the first cathodes 19a, 34a and the anode 20a, and between the cathodes 19b, 34b and the anode 20b to form a bond 23 in bloc with a deposited plating metal to form bonded structures, respectively. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bonded structure and a manufacturing method thereof.

In general, there is known a bonded structure formed by bonding substrates such as a semiconductor chip or a glass substrate on which mounted components, wirings, and the like are formed via a plated metal.
For example, Patent Document 1 discloses a technique in which a mounting component and wiring conductors of a wiring board are joined with a plating metal deposited by an electrolytic plating process in which the wiring conductors are deposited from each other.
JP 10-229271 A

Usually, semiconductor wafers (hereinafter referred to as wafers) are bonded to each other so that a large number of mounting components and connection pads formed on the wafers are connected together to improve productivity.
However, in the case where the joint is formed by electrolytic plating as in Patent Document 1 described above, a current is passed in a state where the electrolytic plating solution is filled in the gap between the wafers held in close proximity to each other, and the plating metal is removed. It will be deposited. In this case, the current flowing through the electrolytic plating solution differs between the wafer center and the wafer outer peripheral side. That is, the current on the outer peripheral side tends to flow, and the current on the central side becomes difficult to flow. For this reason, there is a problem that the deposition rate of the plated metal varies depending on the formation position of the mounted component.

In such a case, a connection pad in which the plating metal is excessively deposited on the wafer and a connection pad in which precipitation is insufficient are generated, resulting in poor productivity. Therefore, in the case of forming the joint by electrolytic plating, in order to improve productivity, it is preferable that the difference in the deposition rate in the substrate is reduced and the plated metal is uniformly deposited in the same plating time. . However, in the past, sufficient countermeasures including Patent Document 1 have not been implemented.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a bonded structure and a method for manufacturing the same, in which plated metal for bonding is uniformly deposited and the productivity is high.

  In order to achieve the above object, the present invention provides a first substrate having a plurality of first chips each having a first cathode and an anode disposed in the vicinity of the first cathode, and a first cathode having the second cathode. An alignment step of aligning a second substrate having a plurality of second chips that are bonded to the chip to form a bonded structure with the first cathode and the second cathode facing each other at a predetermined interval. And immersing the first substrate and the second substrate in an electrolytic plating solution, energizing the first cathode and the second cathode and the anode, and depositing the metal by the deposited metal. Bonding the entire number of the first chip and the second chip on the first substrate and the second substrate in a lump. Each with a bonded structure To provide a method of manufacturing a joined structure, characterized by forming.

  ADVANTAGE OF THE INVENTION According to this invention, the plating metal which joins between board | substrates (chip | tip) can be uniformly deposited, and a joining structure with good productivity and its manufacturing method can be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing a schematic configuration of two silicon semiconductor wafers to be bonded as a first embodiment according to the bonded structure of the present invention. FIG. 2 is a diagram illustrating a configuration before joining of the mounting components illustrated in FIG. 1. FIG. 3 is a diagram showing a cross-sectional configuration of the mounted components to be joined in the AA cross section of FIG. FIG. 4 is a view for explaining a bonding formation step in the bonding portion shown in the BB cross section of FIG. FIG. 5 is a diagram illustrating a configuration example of a holding jig used when forming the joint portion. The direction parallel to the main surface (mounting component forming surface) of the silicon semiconductor wafer is defined as the XY direction, the direction orthogonal to the main surface is defined as the Z direction, and the distance between the wafers in the Z direction is referred to as the interval. . A state in which the alignment in the X-Y direction between the two silicon semiconductor wafers is satisfied and the interval is a predetermined distance is referred to as a predetermined position interval.

  In the present embodiment, a bonded structure for constituting an electrostatic drive type optical deflection apparatus will be described. The electrostatic drive type optical deflection apparatus 1 is an optical system unit for reflecting a light beam on a rotating mirror unit to deflect the light beam or irradiating a scanning light beam obtained by repeating the light beam in a short time. It is.

  FIG. 1 shows silicon semiconductor wafers (hereinafter referred to as wafers) 2 and 3 each having nine first chips 4 and second chips 5 for producing the electrostatic drive type optical deflection apparatus 1. Show. In FIG. 1, the wafers 2 and 3 are described so as to overlap with each other in line symmetry (centered with a one-dot chain line), and the alignment marks 6a and 7a and 6b and 7b on the wafers 2 and 3 coincide with each other. By superimposing in such a manner, the nine first chips 4 and the second chips 5 can be superimposed at predetermined positions described later. The number of these alignment marks may be three or more. The wafer 2 is provided with a cathode lead electrode 8 and an anode lead electrode 9 to be described later, and the wafer 3 is provided with a cathode lead electrode 10 to be described later.

  As shown in FIGS. 2 and 3, in the first chip 4, a first insulating film 14 serving as an interlayer insulating film is formed on the entire surface of the substrate body (wafer 2) 12, and on the first insulating film 14. Are formed with patterned wirings 15a and 15b. Further, in the laminated structure, the second insulating film 17 is formed and insulated in the same layer as the wirings 15a and 15b. Mirror drive electrodes 16a and 16b are respectively formed on the regions where the wirings 15a and 15b are exposed as connection electrodes in the upper layer, and their entire surfaces are individually covered with the third insulating films 21a and 21b. Yes. The wirings 15a and 15b are configured such that an external power source can be connected from a wiring (not shown) and an electrode (not shown) provided on the frame 31. In the first chip 4, the cathodes 19 a and 19 b and the anode 20 are exposed during the plating process, and electrical conduction is possible, and the other surfaces are covered with the second insulating film 17.

  In addition, wiring (not illustrated) (aluminum (Al), copper (Cu) or the like is patterned by a photolithography technique by a sputtering method or a vapor deposition method), a first insulating film 14, a second insulating film 17 (a sputtering method, a CVD method, or the like) The silicon oxide film, the silicon nitride film, and the like formed by photolithography are also appropriately formed by a semiconductor manufacturing technique.

  As shown in FIGS. 2 and 5, in the first chip 4, cathodes 19a and 19b are formed at positions sandwiching the electrodes from both sides in a direction perpendicular to the arrangement direction of the mirror drive electrodes 16a and 16b. Is done. The cathodes 19a and 19b are made of a metal thin film formed by sputtering or vapor deposition and patterned using a photolithography technique. In a plating process described later, for example, copper (Cu) is used as a plating metal by a copper sulfate plating solution. In the case of depositing copper, the material of the cathode is preferably copper. On these cathodes 19a and 19b, a bonding portion 23 is deposited by a plating process to be described later to structurally connect the wafers. A mask 22 that functions as a formation guide for plating metal deposited during the plating process is formed so as to surround the outer periphery of the cathodes 19a and 19b. The mask 22 is, for example, a thick film resist mask that is patterned using a photolithography technique.

  In the present embodiment, the anode 20 is arranged in the vicinity of the cathodes 19a and 19b. This neighborhood arrangement will be described. The proximity of the cathode and the anode means that a current capable of obtaining a desired plating deposition amount is disposed within a distance that can flow between the cathode and the anode through the electroplating solution. In FIG. 2, the arrangement of the cathode 19a and the anode 20a is in the vicinity thereof, and the same applies to the cathode 19b and the anode 20b. As shown in FIG. 2, the anode 20b disposed in the vicinity of the cathode 19b has a D1 so that the current flowing between the anode 20b and the cathode 19b is not smaller than the current flowing between the anode 20b and the cathode 19a. <D2 (D1: distance between anode 20b and cathode 19b, D2: distance between anode 20b and cathode 19a).

That is, as shown in FIG. 4, a plurality of cathodes 19-1 to 19-n (here, up to n = 4) are formed on one wafer or one chip, and d1 : Distance between cathode 19-1 and anode 20-1, d2: distance between cathode 19-2 and anode 20-1, d3: distance between cathode 19-3 and anode 20-1, d4: cathode 19-4 And the distance between the anode 20-1 and dn: the distance between the cathode 19-n and the anode 20-1, when the anode 20-1 is disposed in the vicinity of the cathode 19-1, the following distance is provided: It is preferable to have a relationship.
d1 <d2
d1 <d3
d1 <d4
・
d1 <dn
Furthermore, in this embodiment, as shown in FIG. 2, two pairs of four anodes 20 are formed so as to be close to the outer periphery of the mask 22 and to be orthogonal to each other with the cathodes 19a and 19b as the center.

  The anode 20 is a gold (Au) wire, or, for example, when copper (Cu) is deposited as a plating metal by a copper sulfate plating solution, preferably a stud bump using a copper wire or a copper plating bump formed by a plating method Formed with. For example, as the stud bump, the volume of the bump can be increased by increasing the wire diameter. In the case of a plated bump, by increasing the amount of precipitation, both the thickness and height of the bump can be increased, and the volume of the bump metal can be increased relatively easily. The bump metal of the anode 20 is dissolved together with the plating process. However, by increasing the bump volume, the anode 20 can be prevented from disappearing until the formation of the joint portion 23 is completed.

  Further, if the joining portion 23 to be formed is small, the deposition of the plating metal necessary for forming the anode 20 may be relatively small. Thus, the anode 20 may be a metal thin film formed by sputtering or vapor deposition and patterned by photolithography. Further, the anode 20 is formed of a metal thin film made of an insoluble material with respect to an electrolytic plating solution such as platinum (Pt), so that it does not dissolve during the plating process. Therefore, even when the structure is relatively small and there is no space for forming the large volume anode 20, it is possible to join by forming it with an insoluble material.

  The cathodes 19 a and 19 b are electrically connected to the cathode lead electrode 8 by wiring (not shown), and each anode 20 is electrically connected to the anode lead electrode 9 by an anode wire 30. These wirings are used at the time of plating, and may be divided when cut out in units of chips after the bonding portion forming step.

  Next, the second chip 5 is formed with a frame part 31, a mirror part 33 whose center is supported by a pair of torsion springs 32a and 32b, and cathodes 34a and 34b. These are formed on a wafer having a predetermined thickness by an etching process using a resist mask by a semiconductor manufacturing technique (for example, RIE: reactive ion etching method). The mirror 3, the torsion springs 32 a and 32 b, and the frame 31 are formed by performing an etching process on the wafer 3 to form an opening. In this configuration, these portions are made of silicon, and the mirror portion 33, the torsion springs 32a and 32b, and the frame portion 31 are electrically connected. Therefore, an external power source (not shown) can be connected to the mirror part 33 from a wiring (not shown) and an electrode (not shown) provided on the frame part 31.

  Similarly to the cathodes 19a and 19b described above, the cathodes 34a and 34b are formed with a third insulating film 36 serving as an interlayer insulating film in the lower layer, and are electrically connected to the cathode lead-out electrode 10 by wiring (not shown). The In the second chip 5, the cathodes 34 a and 34 b are exposed during the plating process, and electrical conduction is possible. The other surfaces are covered with the fourth insulating film 37. Also, a mask 38 equivalent to the mask 22 is formed so as to surround the outer periphery of the cathodes 34a and 34b.

  The first chip 4 and the second chip 5 use a camera, an infrared camera, or the like to align the wafers 2 and 3 when the alignment marks 6a and 7a and 6b and 7b shown in FIG. Due to this coincidence, the cathodes 19a, 19b and the cathodes 34a, 34b are opposed to each other, and further, as shown in FIG. 3, the opposite ends of the mirror 33 are opposed to the mirror drive electrodes 16a, 16b (see FIG. 3). (Joining position in the XY direction). Further, the wafers 2 and 3 are positioned so that the distance between them becomes a predetermined distance. The positioning is performed so that the wafers 2 and 3 are held by the holding jig 42 shown in FIG. In this embodiment, an example realized by alignment using an optical alignment mark is described. However, the present invention is not limited to this, and a method of cutting a wafer or the like may be used, or a mark by X-ray detection may be used. Various methods are conceivable.

  The holding jig 42 holds the wafers 2 and 3 respectively, and adjusts the bonding position (alignment mark alignment) in the XY direction, and the substrate position adjusting units 42a and 42a, A substrate spacing adjustment unit 42c having a micrometer function for movably connecting between 42b and adjusting the spacing in the Z direction between the wafers 2 and 3 is formed in a U-shape.

Here, the operation principle of the electrostatic drive type optical deflection apparatus 1 shown in FIG. 3 will be described.
By applying alternately between the mirror drive electrode 16a and the mirror portion 33, between the mirror drive electrode 16b and the mirror portion 33 from an external power source (not shown), and generating an electrostatic force, the torsion springs 32a and 32b are centered. The mirror unit 33 is repeatedly rotated like a seesaw. The rotating mirror unit 33 is irradiated with a light beam generated by an LED or the like, and reflected and deflected here. Furthermore, if the mirror unit 33 is repeatedly rotated in a short time, it is possible to generate a light beam to be scanned.

  Next, with reference to the manufacturing process shown in FIG. 5, a manufacturing method of the electrostatic drive type optical deflection apparatus by wafer bonding will be described.

<Alignment process>
As described above, the nine first chips 4 and the second chips 5 are formed on the wafers 2 and 3, respectively, and all the chips are collectively formed by the position adjustment using the alignment marks 6a and 7a and 6b and 7b. Then, the alignment is completed at a predetermined position interval and is held by the holding jig 42. While being held at the predetermined position interval, an external power source (not shown) is connected to the cathode lead electrodes 8 and 10 and the anode lead electrode 9 provided on the wafers 2 and 3 as shown in FIG. The It is desirable to prevent the electrolytic plating solution from adhering to the cathode lead electrodes 8, 10 and the anode lead electrode 9 when immersed in the electrolytic plating solution.

<Joint formation process>
The aligned wafers 2 and 3 are immersed in the electrolytic plating solution while being held by the holding jig 42. Thereafter, a direct current from an external power source is supplied to the cathode lead electrodes 8 and 10 and the anode lead electrode 9. The external power source has a positive electrode connected to the anode lead electrode 9 and a negative electrode connected to the cathode lead electrodes 8 and 10.

  By this external power source, a current flows between the anode 20 and the cathodes 19a and 19b through the electrolytic plating solution. As shown in FIG. 5B, the plating metal 51 is deposited from both the cathodes 19 a and 19 b while the deposition direction is guided by the mask 22. For example, a copper sulfate plating solution is used as the electrolytic plating solution. In the case of a copper sulfate plating solution, the plating process is generally performed in a plating solution having a temperature of about 25 ° C., so that it can be bonded at a relatively low temperature. For this reason, the performance of the first chip 4 and the second chip 5 may be deteriorated by heat, and even when it is not preferable to apply heat, it is possible to perform bonding that does not deteriorate the performance.

  The plated metal 51 deposited from the first chip 4 and the plated metal 51 deposited from the second chip 5 are brought into contact with each other and joined, and a joint portion 23 composed of the plated metal 51 and the cathodes 19a, 34a (and 19b, 34b) is formed. As shown in FIG. 5C, the first chip 4 and the second chip 5 are joined. At this time, since it is not necessary to apply a mechanical pressure to the first chip 4 and the second chip 5, even if there is a possibility that the performance is deteriorated when the mechanical pressure is applied to the chip, it is possible to perform the bonding without degrading the performance.

  In this process, since the anode 20 is disposed around the cathodes 19a, 19b, 34a, and 34b, even if they are bonded together in units of wafers, they flow in the electrolytic plating solution without being affected by the position of the chip on the substrate. The magnitude of the current becomes uniform. Therefore, the deposition rate of the plated metal to be deposited is substantially unified. Therefore, productivity is improved and yield is improved. Further, as shown in FIG. 2A, since the four anodes 20 are arranged symmetrically with respect to one cathode 19, the current flowing in the electrolytic plating solution is applied to each cathode 19. Flowing in a symmetric direction, the plated metal is uniformly deposited on each cathode 19. Further, since the four anodes 20 are arranged symmetrically with respect to one cathode 34, the current flowing in the electroplating solution also flows to each cathode 34 in a symmetric direction. In contrast, the plating alloy is uniformly deposited. Therefore, the reliability of joining is further improved.

<Division process>
The first substrate 2 and the second substrate 3 bonded by the bonding portion 23 are replaced with the electrostatic drive type optical deflection apparatus 1 including the first chip 4 and the second chip 5 by using a dicer using a blade, Divide into individual laser beams. In the present embodiment, nine electrostatic drive type optical deflection apparatuses 1 are provided.

  As described above, when the electrostatic drive type optical deflection apparatus 1 is manufactured, since the alignment is performed by the wafer, the alignment is performed on a large number of chips at the same time. Thus, since the number of alignment steps can be reduced, productivity can be improved and costs can be reduced.

Next, a second embodiment according to the bonded structure of the present invention will be described.
In the first embodiment described above, the bonded structure is formed by bonding two wafers together. However, the present embodiment is a bonded structure including three or more layers.

  The bonding structure shown in FIG. 7 is bonded by three wafers, that is, by three chips 61, 62, and 63. The chip 62 arranged in the center has mounting components on both main surfaces (front and back surfaces). In addition, chips 61 and 63 to be bonded to both sides are formed with mounting components, circuit elements, and wirings on opposite sides.

In these chips 61, 62, 63, cathodes 64a, 64b, 64c, 64d and an anode 65 are formed in the same manner as in the first embodiment described above. A mask 66 is provided around each cathode to guide the metal deposition direction (shape) during the plating process. Furthermore, the junction part 67 in each of the cathode 64a and the cathode 64b and the cathode 64c and the cathode 64d is formed and connected by the electrolytic plating process.
These chips 61, 62, and 63 are also held in a state of being aligned by a holding jig. As described above, when a plurality of wafers are held at the same time, the wafer disposed inside may be configured to be held at the outer peripheral edge of the wafer. The alignment can also be performed based on the alignment mark described above. In the case of a bonded structure composed of three or more chips, the bonding method of the present invention may be applied to bonding of all the chips, or the bonding method of the present invention may be used for bonding only some chips. Good.

  According to this embodiment, even a bonded structure formed by stacking three or more chips can be easily applied. Also, by aligning according to the state of the wafer, it is possible to align a large number of chips at the same time, so that the number of alignment steps can be reduced compared with the case where alignment is performed separately on chips. , Productivity can be improved and cost can be reduced.

Next, FIG. 8 shows and describes a modification of the anode.
In the first and second embodiments described above, the anode has been described as an example in which two pairs of four are provided around the cathode so as to be orthogonal to the center of the electrode around the cathode. However, the present invention is not limited to this. Is not to be done.

  FIG. 8A is suitable when the area of the cathode 19 is small and the volume of the joint 23 is small, and the two anodes 71a and 71b can cope with metal deposition. These anodes 71a and 71b are positions facing each other at equal distances through the cathode center.

  FIG. 8B is an example in which eight anodes are provided in a square shape with the cathode 19 as the center, which is suitable when the area of the cathode 19 is large and the volume of the junction 23 is large. Two pairs (four) of anodes 72a, 72b, 73a, 73b are disposed at positions that face each other at a distance L1 through the cathode center and are orthogonal to each other in pairs. The remaining two pairs (four) of anodes 74a, 74b, 75a, and 75b face each other at a distance L2 (L1 <L2) through the center of the cathode, and are orthogonal to each other, and further anodes 72a, 72b, 73a, and 73b. Are arranged at equal intervals in a matrix form with a 90 ° offset. In this example, the anodes 72a, 72b, 73a, 73b are arranged at the center of each side of the square. However, the present invention is not limited to this arrangement, and the anodes 72a, 72b, 73a, 73b are centered on the cathode 19. Can be regarded as a double circle if the circle formed by is an inner circle and the circle formed by the anodes 74a, 74b, 75a, 75b is regarded as an outer circle. Therefore, by arranging a plurality on the inner circumference and appropriately arranging them on the outer circumference while checking the arrangement balance, arrangements other than those shown in FIG. 8B are possible.

  In FIG. 8C, the three anodes 76a, 76b, and 76c are shifted by 180 ° from the cathode 19 and arranged at the apex position of the equilateral triangle. In FIG. 8D, an anode 77 formed in an annular shape around the cathode 19 is arranged.

  As described above, it is only necessary that the anode be arranged at a uniform density with respect to the cathode, and the anode is arranged so that the current density flowing through the plating solution to the cathode and each anode is uniform. If it is done, it does not have to be equidistant or equidistant. In addition, in these modified examples, the explanation was made on the assumption that the size of the anode is uniform (thickness and length). However, the current flowing through the cathode and each anode also in the thickness and length (volume) of the anode. The density is not particularly limited as long as the density is uniform. For example, since the anodes 74a, 74b, 75a, and 75b are farther from the cathode than the anodes 72a, 72b, 73a, and 73b, thick anodes may be arranged.

The present invention also includes the following gist.
(1) An anode may be formed on the second chip 5 side. In this case, the cathode may be disposed at the same position as the first chip 4 or may be different.
(2) Although nine chips are arranged on each of the first substrate 2 and the second substrate 3, the present invention is not limited to this, and there may be two or more.
(3) In FIG. 2, two joints 23 are formed in one electrostatic light deflection apparatus 1, but the present invention is not limited to this.

(4) As in this embodiment, for example, the first substrate 2 and the second substrate 3 are not divided into nine chips, and one static light deflection device 1 having nine electrostatic light deflecting devices 1 is provided. It may be used as an electro-optic deflector array. Therefore, the productivity is good, and it can be easily applied to the manufacture of an arrayed electrostatic light deflection apparatus. In addition, for example, it may be used as three electrostatic light deflecting device arrays each including three electrostatic light deflecting devices 1. Further, it is used as one electrostatic light deflector array having six electrostatic light deflectors 1 and one electrostatic light deflector array having three electrostatic light deflectors 1. Also good. Further, it may be used as one electrostatic light deflecting device array having six electrostatic light deflecting devices 1 and three electrostatic light deflecting devices 1, and the division method may be appropriately changed according to the design. May be. At the same time, an electrostatic light deflecting device having a plurality of specifications can be manufactured.

(5) A configuration in which the mask 27 used for the plating process is not formed may be used. Further, the mask 27 may be removed with an organic solvent after the plating step. The mask 27 is not limited to a thick film resist, and for example, a polyimide film may be used.

(6) Although the electrostatic drive type optical deflecting device 1 has been described as an example of the bonding structure, it is not limited to this. For example, the present invention may be applied to an electrostatically driven variable mirror or an electrostatically driven microvalve in which two or more chips are bonded.

(7) The function of the bonding portion 23 may be a configuration that not only holds the first chip 2 and the second chip 3 but also has an electrical connection between the chips and also functions as a wiring. As a result, when it is necessary to electrically connect the first chip 2 and the second chip 3, it is possible to omit a step of electrically connecting in a step such as wire bonding separately, and to provide it at a low cost. . Further, since it is not necessary to separately provide a component for electrical connection, the size can be further reduced.

(8) In the above-described embodiment, the silicon semiconductor wafer has been described as an example of the substrate having the bonding structure of the electrostatic light deflecting device, but is not limited thereto. For example, a bonding structure on a glass substrate on which circuit elements used for a liquid crystal display or the like are formed may be used. Further, a bonding structure including a glass substrate and a silicon semiconductor wafer may be used. The bonding method of the present invention can also be applied to a structure in which wirings such as a printed board and a ceramic board are hierarchically connected.

It is a figure which shows schematic structure of the semiconductor wafer to which the mounting component used as 1st Embodiment based on the joining structure of this invention was formed. It is a figure which shows the structure before joining of the mounting components shown in FIG. It is a figure which shows the cross-sectional structure of the mounting components joined in the AA cross section of FIG. It is a figure for demonstrating arrangement | positioning vicinity of a cathode and an anode. It is a figure for demonstrating the joining formation process in the junction part shown to the BB cross section of FIG. It is a figure which shows the structural example of the holding jig used at the time of formation of a junction part. It is a figure which shows the structure of the junction structure of the mounting components used as 2nd Embodiment which concerns on the junction structure of this invention. It is a figure which shows the modification of an anode.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electrostatic drive type optical deflection | deviation apparatus, 2, 3 ... Silicon semiconductor wafer, 4 ... 1st chip | tip, 5 ... 2nd chip | tip, 6a, 6b, 7a, 7b ... Alignment mark, 8, 10 ... Cathode extraction Electrode, 9 ... anode extraction electrode, 12 ... substrate body, 14 ... first insulating film, 15a, 15b ... wiring, 16a, 16b ... mirror drive electrode, 17 ... second insulating film, 19a, 19b ... cathode, 20 ... Anode, 21a, 21b ... Third insulating film, 22 ... Mask, 23 ... Joint part, 31 ... Frame part, 32a, 32b ... Torsion spring, 33 ... Mirror part.

Claims (9)

A first substrate having a plurality of first chips having a first cathode and an anode disposed in the vicinity thereof, and a second substrate having a second cathode are bonded to the first chip to form a bonded structure. An alignment step of aligning the second substrate having a plurality of second chips with the first cathode and the second cathode facing each other at a predetermined interval;
The first substrate and the second substrate are immersed in an electrolytic plating solution, and a current is passed between the first cathode and the second cathode and the anode, and the first metal is deposited by the deposited plating metal. A bonding step of bonding between the cathode and the second cathode;
A bonding structure characterized in that all the first chips and the second chips on the first substrate and the second substrate are bonded together and a bonding structure is formed on each of them. Body manufacturing method.   2. The substrate dividing step according to claim 1, further comprising a substrate dividing step of dividing each of the plurality of bonded structures manufactured by bonding the first substrate and the second substrate after the bonding step. A method for manufacturing a bonded structure.   The method for manufacturing a bonded structure according to claim 1, wherein the anode is formed by a step of forming a bump.   The method for manufacturing a joined structure according to claim 1, wherein the anode is an insoluble anode. In a bonded structure in which a first chip having a first cathode and a second chip having a second cathode are bonded to each other by plating metal deposited from the first cathode and the second cathode. ,
At least one anode is arranged in the vicinity of the cathode on the surface having the cathode of at least one of the first chip and the second chip.   The joining structure according to claim 5, wherein the anode includes a plurality of anodes, and the anodes are arranged symmetrically with respect to the cathode.   The bonded structure according to claim 5, wherein the anode is formed by a bump.   The joined structure according to claim 5, wherein the anode is made of an insoluble material.   A joint portion including the first cathode, the plated metal, and the second cathode, and joining the first chip and the second chip electrically connects the first chip and the second chip. The bonding structure according to claim 5, wherein the bonding structure has a function as a wiring connected to the wire.

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