JP2007067048A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technology for easily forming a contact without damaging a characteristic and reliability of an MIS transistor. <P>SOLUTION: A manufacturing method of a semiconductor device comprises a process (A) for forming a gate insulating film 205 on a semiconductor substrate 201, a process (B) for forming a gate electrode 206 on the gate insulating film 205, a process (C) for forming a protection film comprising at least an amorphous carbon film 210 as a surface layer on a whole face, a process (D) for forming side walls 210a formed of the protection film on side faces of the gate electrode 206 by etch back, and a process (E) for selectively removing only the amorphous carbon film (210). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a MIS (Metal Insulator Semiconductor) transistor.

  MIS transistors in recent years have an LDD (Lightly Doped Drain) structure in order to alleviate electric field concentration under the gate electrode end. A general method for manufacturing an MIS transistor having an LDD structure will be briefly described with reference to FIG.

  First, an element isolation structure 102 such as a field oxide film, a P-type well 103, and an N-type well 104 are formed in a semiconductor substrate 101. A gate insulating film 105 is formed on the semiconductor substrate 101. Next, a polysilicon film, a polycide film, or a polymetal film is formed as the gate electrode material film 106. The gate electrode 107a is formed by processing the deposited film in accordance with a desired pattern. Here, a gate mask insulating film 107 may be formed for gate processing. After that, an oxidation process is performed on the side surface of the gate electrode 107 a and the surface of the semiconductor substrate 101.

  Next, a low concentration N-type impurity diffusion layer 108 and a low concentration P-type impurity diffusion layer 109 are formed in the semiconductor substrate 101 by ion implantation. Here, the gate electrode 107a is used as a mask. Moreover, in order to suppress the short channel effect, pocket ion implantation may be performed. Next, a single layer silicon nitride film or a silicon nitride film / silicon oxide film laminated film is deposited on the entire surface by CVD. Subsequently, the deposited film is etched back by anisotropic dry etching, and a sidewall 110 is formed on the side surface of the gate electrode 107a.

  Next, a high concentration N-type impurity diffusion layer 111 and a high concentration P-type impurity diffusion layer 112 are formed in the semiconductor substrate 101 by ion implantation. Here, the sidewall 110 together with the gate electrode 107a is used as a mask. Thereafter, the high-concentration impurity diffusion layers 111 and 112 are activated by heat treatment. Next, an interlayer insulating film 113 is formed. Thereafter, a contact hole is formed by dry etching so as to penetrate the interlayer insulating film 113 and the gate insulating film 105. Then, by filling the contact hole with a conductive film, a contact 114 connected to the high concentration impurity diffusion layers 111 and 112 is formed.

  A technique related to the sidewall is disclosed in Patent Document 1. According to the technique, the sidewall is formed so that transistors having different characteristics depending on regions are obtained. Specifically, first, a first sidewall is formed in a region where a transistor having certain characteristics is formed. Then, impurity ions are implanted by utilizing the first sidewall. Thereafter, the first sidewall is removed. Next, a second sidewall different from the first sidewall is formed in a region where a transistor having another characteristic is formed.

JP 2005-64535 A

  The inventor of the present application paid attention to the following points. In order to miniaturize the MIS transistor, it is necessary to reduce the distance between the adjacent gate electrodes 107a. This means that the space between the adjacent sidewalls 110 is narrowed. When the space is narrowed, the embedding property of the interlayer insulating film 113 is deteriorated. Furthermore, when the contact hole is formed after the interlayer insulating film 113 is buried, the silicon nitride film constituting the sidewall 110 is also removed by dry etching. Thus, with the miniaturization of the MIS transistor, dry etching for forming the contact 114 becomes more difficult.

As a method for facilitating the processing of the contact 114, the above-described sidewall 110 (a single-layer silicon nitride film or a silicon nitride film / a stacked film of silicon oxide films) is wet before the interlayer insulating film 113 is deposited. It can be considered to be removed by etching. For the wet etching, hydrofluoric acid (HF), phosphoric acid (H ₃ PO ₄ ), or the like is used. However, in that case, even the insulating films such as the field oxide film (element isolation structure) 102, the gate insulating film 105, and the gate mask insulating film 107 are removed. In particular, undesirably removing a part of the gate insulating film 105 significantly reduces the characteristics and reliability of the manufactured MIS transistor.

  An object of the present invention is to provide a technique capable of easily forming a contact without impairing the characteristics and reliability of a MIS transistor.

  Another object of the present invention is to provide a technique capable of expanding a space in which a contact is formed without damaging a gate insulating film and an element isolation structure.

  Still another object of the present invention is to provide a sidewall that can be selectively removed without affecting the gate insulating film and the element isolation structure.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  The method for manufacturing a semiconductor device according to the present invention includes (A) a step of forming a gate insulating film (205) on a semiconductor substrate (201), and (B) a gate electrode (207a) formed on the gate insulating film (205). A step of forming, (C) a step of forming a protective film including at least an amorphous carbon film (210) as a surface layer, and (D) a protective film on the side surface of the gate electrode (207a) by etch back. Forming a sidewall (210a); and (E) removing the amorphous carbon film (210).

  The amorphous carbon film (210) can be removed with an infinite selectivity with respect to other constituent materials. For example, it is possible to selectively remove only the amorphous carbon film (210) by using gas plasma of oxygen alone gas. Therefore, in the step (E), at least a part of the sidewall (210a) is removed without affecting the gate insulating film (205) and the element isolation structure (202). That is, the space in which the contact (215) is formed can be expanded without damaging the gate insulating film (205) and the element isolation structure (202). Therefore, it becomes easy to embed the interlayer insulating film (213) in the expanded space, and it becomes easy to form the contact (215). As described above, according to the present invention, the contact (215) can be easily formed without impairing the characteristics and reliability of the MIS transistor.

  The high concentration impurity diffusion layers (211 and 212) as the source / drain connected to the contact (215) may be formed between the step (D) and the step (E). Specifically, after the step (D), ion implantation using the sidewall (210a) and the gate electrode (207a) as a mask is performed. As a result, high-concentration impurity diffusion layers (211 and 212) are formed in a self-aligned manner in the semiconductor substrate (201).

  The LDD region (208, 209) may be formed between the step (B) and the step (C). Specifically, after the step (B), ion implantation using the gate electrode (207a) as a mask is performed. As a result, LDD regions (208, 209) are formed in a self-aligned manner in the semiconductor substrate (201). The LDD in the active region improves the characteristics of the manufactured MIS transistor.

  The above-described protective film is, for example, a single layer amorphous carbon film (210). In that case, in the step (C), a single-layer amorphous carbon film (210) is formed as a protective film. The protective film described above may be a laminated film including a silicon nitride film (310b) and an amorphous carbon film (310). In that case, the step (C) includes (C1) a step of forming a silicon nitride film (310b) on the entire surface, and (C2) a step of forming an amorphous carbon film (210) as a surface layer. The protective film described above may be a laminated film including a silicon oxide film (310b) and an amorphous carbon film (310). In that case, the step (C) includes (C1) a step of forming a silicon oxide film (310b) on the entire surface, and (C2) a step of forming the amorphous carbon film (310) as a surface layer.

  The sidewall according to the present invention includes at least an amorphous carbon film as a surface layer, and the amorphous carbon film can be removed with an infinite selectivity with respect to other components. Therefore, it is possible to remove at least a part of the sidewall without affecting the gate insulating film and the element isolation structure. That is, the space in which the contact is formed can be expanded without damaging the gate insulating film and the element isolation structure. Therefore, it is possible to easily form a contact without impairing the characteristics and reliability of the MIS transistor. In addition, the embedding property of the interlayer insulating film is improved. Thus, according to the method for manufacturing a semiconductor device of the present invention, a highly reliable MIS transistor is provided.

  A method for manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings. In the present embodiment, as an example, a MIS transistor having an LDD structure is manufactured.

(First embodiment)
2A to 2K are cross-sectional views sequentially showing manufacturing steps according to the first embodiment of the present invention. First, as illustrated in FIG. 2A, the element isolation structure 202 is formed in the semiconductor substrate 201. The semiconductor substrate 201 is, for example, a single crystal silicon substrate into which a P-type impurity is introduced. The element isolation structure 202 is, for example, an STI (Shallow Trench Isolation) structure.

Next, as shown in FIG. 2B, a P-type well 203 and an N-type well 204 are formed in a region in the semiconductor substrate 201 surrounded by the element isolation structure 202. The P-type well 203 is formed by masking a region to be an N-type well with a photoresist and injecting a P-type impurity (for example, boron (B) or boron fluoride (BF ₂ )) by an ion implantation method. . Similarly, the N-type well 204 is formed by masking the P-type well 203 with a photoresist and injecting an N-type impurity (for example, phosphorus (P) or arsenic (As)) by ion implantation. In addition, heat treatment is performed to electrically activate the impurities introduced into the semiconductor substrate 201.

  Next, as illustrated in FIG. 2C, a gate insulating film 205 is formed on the semiconductor substrate 201. The gate insulating film 205 is a silicon oxide film formed by, for example, a thermal oxidation method or an ISSG oxidation (In-Situ Steam Generated Oxidation) method. Further, as the gate insulating film 205, a High-k film having a dielectric constant higher than that of the silicon oxide film may be used. Subsequently, a film 206 serving as a material for the gate electrode is formed on the gate insulating film 205. The gate electrode material film 206 includes a single layer polysilicon film, a stacked film of a polysilicon film and a tungsten silicide film (polycide gate film), a stacked film of a polysilicon film and a tungsten film (polymetal gate film), and the like. Can be mentioned. Subsequently, a gate mask insulating film 207 for processing a gate electrode is formed on the gate electrode material film 206 by a CVD method. Examples of the gate mask insulating film 207 include a silicon nitride film, a silicon oxide film, or a silicon nitride film / silicon oxide film laminated film. Note that the gate mask insulating film 207 may be omitted.

  Next, a resist is applied to the entire surface, and a resist mask having a desired pattern is formed by a photolithography technique. By anisotropic dry etching using the resist mask, the gate mask insulating film 207 and the gate electrode material film 206 in a region corresponding to a desired pattern are removed. When the photoresist is removed, the gate electrode 207a formed on the gate insulating film 205 is obtained as shown in FIG. 2D. Note that after the gate mask insulating film 207 is processed by anisotropic dry etching using the resist mask, the resist mask may be removed by oxygen gas plasma. In this case, by using the processed gate mask insulating film 207 as a next mask, the gate electrode material film 206 is processed by anisotropic dry etching. Even in this case, the structure shown in FIG. 2D is obtained.

Next, as shown in FIG. 2E, LDD (Lightly Doped Drain) regions 208 and 209 are formed in a self-aligned manner in the surface layer portion of the semiconductor substrate 201 by ion implantation using the gate electrode 207a as a mask. Specifically, the low-concentration N-type impurity diffusion layer 208 and the low-concentration P-type impurity diffusion layer 209 are formed in the P-type well 203 and the N-type well 204, respectively, by ion implantation. For example, phosphorus (P) or arsenic (As) is used as the N-type impurity to be ion-implanted. As the P-type impurity to be ion-implanted, for example, boron (B) or boron fluoride (BF ₂ ) is used. After ion implantation, heat treatment may be performed to electrically activate the impurities.

  Next, as shown in FIG. 2F, a single-layer amorphous carbon film 210 is formed on the entire surface. The amorphous carbon film 210 is deposited by a plasma-excited CVD method, and propylene is used as a source gas. The film thickness of the amorphous carbon film 210 is determined depending on the LDD structure required for the characteristics of the MIS transistor and the size of the sidewall.

Next, the amorphous carbon film 210 is etched back by anisotropic dry etching. As a result, as shown in FIG. 2G, a sidewall 210a is formed on the side surface of the gate electrode 207a. For the anisotropic dry etching for the amorphous carbon 210, for example, a mixed gas of O ₂ / Ar is used. The formed sidewall 210 a is composed of a single-layer amorphous carbon film 210, and the surface layer is also the amorphous carbon film 210.

Next, as shown in FIG. 2H, source / drain diffusion layers 211 and 212 are formed in a self-aligned manner on the surface layer portion of the semiconductor substrate 201 by ion implantation using the gate electrode 207a and the sidewall 210a as a mask. . Specifically, a high-concentration N-type impurity diffusion layer 211 and a high-concentration P-type impurity diffusion layer 212 are formed in the P-type well 203 and the N-type well 204, respectively, by ion implantation. For example, phosphorus (P) or arsenic (As) is used as the N-type impurity to be ion-implanted. As the P-type impurity ions are implanted, for example, boron (B) or boron fluoride (BF ₂₎ is used. The impurity concentration in each of the high concentration impurity diffusion layers 211 and 212 is relatively higher than the impurity concentration in the low concentration impurity diffusion layers 208 and 209 described above.

  Next, as shown in FIG. 2I, the sidewall 210a made of the amorphous carbon film 210 is entirely removed. This step is performed so that only the amorphous carbon film 210 is removed. That is, the amorphous carbon film 210 is removed with an infinite selection ratio with respect to other constituent materials. In order to selectively remove only the amorphous carbon film 210, for example, gas plasma of oxygen alone gas may be used. Thus, according to the present embodiment, only the amorphous carbon film 210 is removed without affecting the gate insulating film 205 and the element isolation structure 202. Since the sidewall 210a is composed of a single-layer amorphous carbon film 210, the sidewall 210a is entirely removed in the present embodiment. Therefore, the space where the contact is formed later is expanded by the side wall 210a. Note that after the amorphous carbon film 210 is removed, heat treatment may be performed to electrically activate the high-concentration impurity diffusion layers 211 and 212.

  Next, as shown in FIG. 2J, after a thin silicon nitride film 214 is formed on the entire surface, an interlayer insulating film 213 is formed. The interlayer insulating film 213 is a silicon oxide film and is deposited by, for example, a CVD method. A CMP (Chemical Mechanical Polishing) method is used to planarize the surface of the interlayer insulating film 213. As described above, the space in which the contact is formed is expanded without damaging the gate insulating film 205 and the element isolation structure 202. Therefore, it becomes easy to embed the interlayer insulating film 213 in the space, that is, the “embeddability” of the interlayer insulating film 213 is improved. The thin silicon nitride film 214 is preferably formed so as to be sufficiently thinner than the thickness of the sidewall 210a.

  Next, a contact hole is formed by dry etching so as to penetrate the interlayer insulating film 213 and the gate insulating film 205. Then, by filling the contact hole with a conductive film, a contact 215 connected to the high-concentration impurity diffusion layers 211 and 212 is formed as shown in FIG. 2K. In this way, a MIS transistor having the required LDD structure is manufactured.

  As described above, the sidewall 210a according to the present embodiment includes the amorphous carbon film 210 as a surface layer, and is removed with an infinite selection ratio with respect to other components. Therefore, it is possible to prevent the gate insulating film 205 and the element isolation structure 202 from being damaged when the sidewall 210a is removed. This prevents the characteristics and reliability of the manufactured MIS transistor from deteriorating.

  Further, since the side wall 210a is removed, a space in which the contact 215 is formed is enlarged. Therefore, the embedding property of the interlayer insulating film 213 is improved. Since the side wall 210a does not remain, the contact 215 does not come into contact with a side wall formed of a silicon nitride film, a silicon oxide film, or the like as in the prior art. Therefore, dry etching for forming the contact 215 (contact hole) is facilitated. As described above, according to this embodiment, the contact 215 can be easily formed without impairing the characteristics and reliability of the MIS transistor.

  Further, the LDD structure contributes to the improvement of the characteristics of the MIS transistor. According to the present embodiment, an MIS transistor having excellent reliability is provided.

(Second Embodiment)
The material of the sidewall is not limited to the single-layer amorphous carbon film 210 shown in the first embodiment. If a protective film including at least an amorphous carbon film as a surface layer is used, the effect of the present invention can be obtained. For example, a laminated film of a silicon nitride film and an amorphous carbon film is used. Alternatively, a laminated film of a silicon oxide film and an amorphous carbon film may be used. In any case, the amorphous carbon film is formed on the uppermost surface of the laminated film.

  A manufacturing process of the MIS transistor according to the present embodiment will be described below with reference to FIGS. 3A to 3D. The manufacturing process according to the present embodiment is the same as the manufacturing process shown in the first embodiment, and the same process as that shown in FIGS. 2A to 2E is executed first. As a result, as shown in FIG. 3A, an element isolation structure 302, a P-type well 303, an N-type well 304, and low-concentration impurity diffusion layers (LDD) 308 and 309 are formed in a semiconductor substrate 301. A gate electrode 307 a is formed on the semiconductor substrate 301 with a gate insulating film 305 interposed therebetween. The gate electrode 307 a includes a gate electrode material film 306 and a gate mask insulating film 307.

  Next, as shown in FIG. 3A, a silicon nitride film 310b or a silicon oxide film 310b is formed on the entire surface by a CVD method. In the following description, the case of the silicon nitride film 310b will be described as an example. Even in the case of the silicon oxide film 310a, the steps shown below are the same. In order to secure a space in which the contact is formed, it is desirable that the silicon nitride film 310b be formed as thin as possible. Subsequently, an amorphous carbon film 310 is formed on the silicon nitride film 310b by a CVD method. The size of the sidewall to be formed later is determined by the sum of the thickness of the silicon nitride film 310b and the thickness of the amorphous carbon film 310. Therefore, the film thickness of the amorphous carbon film 310 is determined according to the required sidewall size of the MIS transistor.

Next, etch back of the laminated film of the amorphous carbon film 310 and the silicon nitride film 310b is performed by anisotropic dry etching. As a result, as shown in FIG. 3B, sidewalls 310a are formed on the side surfaces of the gate electrode 307a. In this anisotropic dry etching, first, for example, a mixed gas of O ₂ / Ar is used to etch back the amorphous carbon film 310. When the underlying silicon nitride film 310b is exposed, the etching gas is switched to a mixed gas of, for example, CHF ₃ / CF ₄ / O ₂ / Ar. The silicon nitride film 310b is etched back by the mixed gas. The side wall 310 a formed as a result is a laminated film of the silicon nitride film 310 b and the amorphous carbon film 210, and the surface layer is the amorphous carbon film 210.

  Next, as in the first embodiment, source / drain diffusion layers 311 and 312 are formed in a self-aligned manner in the surface layer portion of the semiconductor substrate 301 by ion implantation using the gate electrode 307a and the sidewall 310a as a mask. The Specifically, the high-concentration N-type impurity diffusion layer 311 and the high-concentration P-type impurity diffusion layer 312 are formed in the P-type well 303 and the N-type well 304, respectively, by ion implantation.

  Next, only the amorphous carbon film 310 on the sidewall 310a is selectively removed. In order to selectively remove only the amorphous carbon film 310, for example, gas plasma of oxygen alone gas may be used. As a result, as shown in FIG. 3C, only the sidewall formed of the silicon nitride film 310b remains on the side surface of the gate electrode 307a. A space where a contact is formed later is expanded by the amount of the removed amorphous carbon film 310.

  Next, as in the first embodiment, after a thin silicon nitride film 314 is formed on the entire surface, an interlayer insulating film 313 is formed. Subsequently, after a contact hole is formed so as to penetrate the interlayer insulating film 313 and the gate insulating film 305, a contact 315 connected to the high-concentration impurity diffusion layers 311 and 312 is formed. In this way, as shown in FIG. 3D, the MIS transistor having the LDD structure is manufactured.

  As described above, the sidewall 310a according to the present embodiment includes the amorphous carbon film 310 as a surface layer, and is removed with an infinite selectivity with respect to other components. Accordingly, it is possible to prevent the gate insulating film 305 and the element isolation structure 302 from being damaged when the amorphous carbon film 310 is removed. This prevents the characteristics and reliability of the manufactured MIS transistor from deteriorating.

  In addition, since a part of the side wall 310a is removed, a space between the adjacent side walls 310a, that is, a space in which the contact 315 is formed is enlarged. Therefore, the embedding property of the interlayer insulating film 313 is improved, and the contact 315 can be easily formed. As described above, according to this embodiment, the contact 315 can be easily formed without impairing the characteristics and reliability of the MIS transistor. Further, the LDD structure contributes to the improvement of the characteristics of the MIS transistor. According to the present embodiment, an MIS transistor having excellent reliability is provided.

FIG. 1 is a cross-sectional view showing the structure of a conventional MIS transistor. FIG. 2A is a cross-sectional view showing a manufacturing step of the MIS transistor according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view showing a step subsequent to the step shown in FIG. 2A. FIG. 2C is a cross-sectional view showing a step subsequent to the step shown in FIG. 2B. FIG. 2D is a cross-sectional view showing a step that follows the step shown in FIG. 2C. FIG. 2E is a cross-sectional view showing a step subsequent to the step shown in FIG. 2D. FIG. 2F is a cross-sectional view showing a step subsequent to the step shown in FIG. 2E. FIG. 2G is a cross-sectional view showing a step subsequent to the step shown in FIG. 2F. FIG. 2H is a cross-sectional view showing a step subsequent to the step shown in FIG. 2G. FIG. 2I is a cross-sectional view showing a step subsequent to the step shown in FIG. 2H. FIG. 2J is a cross-sectional view showing a step subsequent to the step shown in FIG. 2I. FIG. 2K is a cross-sectional view showing a step subsequent to the step shown in FIG. 2J. FIG. 3A is a cross-sectional view showing a manufacturing step of the MIS transistor according to the second embodiment of the present invention. FIG. 3B is a cross-sectional view showing a step subsequent to the step shown in FIG. 3A. FIG. 3C is a cross-sectional view showing a step subsequent to the step shown in FIG. 3B. FIG. 3D is a cross-sectional view showing a step subsequent to the step shown in FIG. 3C.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 Element isolation structure 103 P type well 104 N type well 105 Gate insulating film 106 Gate electrode material film 107 Gate mask insulating film 107a Gate electrode 108 Low concentration N type impurity diffusion layer 109 Low concentration P type impurity diffusion layer 110 Side Wall 111 High-concentration N-type impurity diffusion layer 112 High-concentration P-type impurity diffusion layer 113 Interlayer insulating film 114 Contact 201 Semiconductor substrate
202 Element isolation structure 203 P-type well 204 N-type well 205 Gate insulating film 206 Gate electrode material film 207 Gate mask insulating film 207a Gate electrode 208 Low-concentration N-type impurity diffusion layer 209 Low-concentration P-type impurity diffusion layer 210 Amorphous carbon Film 210a Side wall 211 High-concentration N-type impurity diffusion layer 212 High-concentration P-type impurity diffusion layer 213 Interlayer insulating film 214 Silicon nitride film 215 Contact 301 Semiconductor substrate 302 Element isolation structure 303 P-type well 304 N-type well 305 Gate insulating film 306 Gate electrode material film 307 Gate mask insulating film 307a Gate electrode 308 Low concentration N-type impurity diffusion layer 309 Low concentration P-type impurity diffusion layer 310 Amorphous carbon film 310a Side wall
310b Silicon nitride film or silicon oxide film 311 High-concentration N-type impurity diffusion layer 312 High-concentration P-type impurity diffusion layer 313 Interlayer insulating film 314 Silicon nitride film 315 Contact

Claims (8)

(A) forming a gate insulating film on the semiconductor substrate;
(B) forming a gate electrode on the gate insulating film;
(C) forming a protective film including at least an amorphous carbon film as a surface layer on the entire surface;
(D) forming a sidewall made of the protective film on a side surface of the gate electrode by etch back. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
Furthermore, (E) The manufacturing method of a semiconductor device which has the process of removing only the said amorphous carbon film. A method of manufacturing a semiconductor device according to claim 2,
In the step (E), the amorphous carbon film is removed by using gas plasma of oxygen-only gas. A method of manufacturing a semiconductor device according to claim 2 or 3,
And (a) forming an impurity diffusion layer in the semiconductor substrate by ion implantation using the sidewall and the gate electrode as a mask,
The step (a) is performed between the step (D) and the step (E). A method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
And (b) forming an LDD (Lightly Doped Drain) region in the semiconductor substrate by ion implantation using the gate electrode as a mask.
The step (b) is performed between the step (B) and the step (C). A method of manufacturing a semiconductor device according to claim 1,
In the step (C), a single-layer amorphous carbon film is formed as the protective film. A method of manufacturing a semiconductor device according to claim 1,
The step (C)
(C1) forming a silicon nitride film on the entire surface;
(C2) A step of forming the amorphous carbon film as the surface layer after the step (C1). A method of manufacturing a semiconductor device according to claim 1,
The step (C)
(C1) forming a silicon oxide film on the entire surface;
(C2) A step of forming the amorphous carbon film as the surface layer after the step (C1).

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