CN210984733U - Cellular structure and semiconductor assembly using same - Google Patents
Cellular structure and semiconductor assembly using same Download PDFInfo
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- CN210984733U CN210984733U CN201922399069.7U CN201922399069U CN210984733U CN 210984733 U CN210984733 U CN 210984733U CN 201922399069 U CN201922399069 U CN 201922399069U CN 210984733 U CN210984733 U CN 210984733U
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Abstract
The cell structure comprises a semiconductor substrate, wherein a plurality of first groove units and second groove units are arranged on the semiconductor substrate, a carrier barrier region and a first electric field shielding region are respectively arranged at the bottoms of the first groove units and the second groove units, a second electric field shielding region is arranged at the periphery of the carrier barrier region and the first electric field shielding region, and a conductive material is arranged in the grooves to correspondingly form two gate regions. The source body area is arranged between the adjacent first groove units and is in contact with the first metal layer on the top of the semiconductor substrate, the upper area is arranged between the first groove unit and the second groove unit and is isolated from the second metal layer through an insulating medium, and more than one source area is arranged on the surface of the source body area, close to the side edge of at least one of the first groove unit and the second groove unit. The first semiconductor region and the second metal layer contacting the first semiconductor region are arranged at the bottom of the semiconductor substrate.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a cell structure and a semiconductor device using the same.
Background
The trench power semiconductor device has the characteristics of high integration level, high input impedance, small driving power, simple driving circuit, low on-resistance, low on-voltage, high switching speed, small switching loss and the like, and is widely applied to various power management and switching conversion. For example, a common Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of an Insulated Gate field effect Transistor (MOS) and a Bipolar Transistor (BJT), which has the above-mentioned characteristics. In order to further improve the robustness and current density of the device, a new device using deep and shallow trenches is proposed, however, the process of the power semiconductor device requires strict adjustment of the concentration and doping level of the semiconductor material at each portion to effectively control the device performance, so the process requirements are relatively severe.
If the material doping precision is wrong, the doped region under the shallow groove reaches the periphery of the deep groove through diffusion, and longitudinal diffusion is generated besides transverse diffusion, so that the risk of mutual compensation with other semiconductor regions with different conductive properties is easily generated, and the semiconductor device loses the gate control performance. Moreover, when the etching window of the trench is misaligned, the concentration of the semiconductor region on one side near the deep trench deviates from the predetermined requirement, which causes a structure matching with the deep trench to be incorrect, thereby generating a poor conduction path or generating an unexpected hole channel, and greatly increasing the conduction voltage drop of the device.
SUMMERY OF THE UTILITY MODEL
In order to solve the above-mentioned problems, an object of the present invention is to provide a cell structure and a semiconductor device using the same, in which the offset tolerance of a trench etching window is controlled by improving the cell structure.
The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.
According to the present application, a cell structure of a semiconductor device is provided, which includes: a semiconductor substrate of a first conductivity type; the semiconductor substrate comprises a semiconductor substrate, a plurality of groove units and a plurality of control units, wherein the plurality of groove units are arranged on a first side of the semiconductor substrate and comprise a first groove unit and a second groove unit, the first groove unit is arranged in a separated mode, and the second groove unit is arranged on two outer sides of the first groove unit; the first gate region is arranged in the first groove unit and is isolated from the semiconductor substrate through a first medium; the second gate region is arranged in the second groove unit and is isolated from the semiconductor substrate through a second medium; a carrier barrier region of the first conductivity type disposed adjacent to a bottom of the first trench cell; an electric field shielding region of the second conductivity type disposed adjacent to a bottom of the second trench unit; the source body region of the second conduction type is arranged at the inner side interval of the first groove unit and is provided with more than one source region of the first conduction type, the source regions are tightly attached to the first medium of the first groove unit, and the source body region and the source regions are arranged on the surface of the semiconductor substrate; an upper region disposed at an interval between the first tank unit and the second tank unit; the first metal layer is arranged on the top of the semiconductor substrate, contacts the source region and isolates the upper region and part or all of the first groove units through a third medium; a second electric field shielding region of the second conductivity type disposed outside at least one of the first electric field shielding regions at an outermost periphery; a doped region of a second conductivity type formed in the semiconductor substrate in a vertical direction contacting the second electric field shielding region and the first metal layer; a first semiconductor region disposed on a second side of the semiconductor substrate, the second side being opposite to the first side; and a second metal layer disposed in contact with the first semiconductor region.
The technical problem solved by the application can be further realized by adopting the following technical measures.
In an embodiment of the present application, the second electric field shielding region is in contact with or not in contact with the first electric field shielding region.
In an embodiment of the present application, the second electric field shielding region is located below an outer side of the first electric field shielding region.
In an embodiment of the present application, the doped region and the first metal layer are isolated from each other by the third dielectric.
In an embodiment of the present application, the upper region further includes a third dielectric layer disposed outside at least one of the second trench units and isolated from the first metal layer by the third dielectric layer.
In an embodiment of the present application, the second gate region surface is entirely in contact with the first metal layer.
In an embodiment of the application, an opening is disposed in a position of the third medium corresponding to a notch of the second slot unit, and the first metal layer contacts the second gate region through the opening.
In an embodiment of the present application, the widths of the notches of the first and second groove units are the same or different.
In an embodiment of the present application, a depth of the second groove unit is greater than or equal to the first groove unit.
In an embodiment of the present application, the number of the second groove units disposed at an outer side of the first groove unit is plural, and the bottom portions of the plural second groove units are all adjacently disposed with the electric field shielding region of the second conductivity type. The electric field shielding regions are at least adjacent to each other. The source region is also disposed in the space of the second trench unit and contacts the first metal layer.
In an embodiment of the present application, the source region is of a first conductivity type or a second conductivity type.
In an embodiment of the present application, the source region is a heavily doped region or a lightly doped region.
In an embodiment of the present application, the first conductive type is N-type, and the second conductive type is P-type.
In an embodiment of the present application, the first conductive type is a P type, and the second conductive type is an N type.
In an embodiment of the present application, the source region is an electron source region when the source region is an N-type, and the source region is a hole source region when the source region is a P-type.
In an embodiment of the present application, the first semiconductor region is of a first conductivity type or a second conductivity type.
In an embodiment of the present application, one side of the first semiconductor region is provided with a third semiconductor region having the same or different conductivity type as that of the first semiconductor region.
In an embodiment of the present application, a fourth semiconductor region having a conductivity type different from that of the first semiconductor region is disposed on a same layer side of the first semiconductor region.
In an embodiment of the present application, the upper region is a first conductivity type semiconductor, a second conductivity type semiconductor, or an insulating substance.
In an embodiment of the present application, the gate region and the cathode region are made of a conductive material, which includes polysilicon or a conductive metal material.
In an embodiment of the present application, the material of each of the aforementioned semiconductors includes a silicon (Si) material or a silicon carbide (SiC) material.
In an embodiment of the present invention, the first dielectric, the second dielectric and the third dielectric may be selectively made of an insulating material including silicon dioxide or benzocyclobutene (BCB) or Polyimide (PI), a composite layer of silicon dioxide and other materials, such as a composite layer of silicon dioxide and silicon nitride, a composite layer … of silicon dioxide and Polyimide (PI), and the like.
Another object of the present invention is to provide a semiconductor device including a cell region and a termination region, wherein the cell region includes one or more cells, and the structure of the cells includes: an N-type semiconductor substrate; the N-type semiconductor substrate comprises a plurality of N-type semiconductor substrates, a plurality of groove units and a plurality of control units, wherein the N-type semiconductor substrates are arranged on the first sides of the N-type semiconductor substrates; the polycrystalline silicon is arranged in the first groove unit and is used as a first gate region, and the polycrystalline silicon is isolated from the semiconductor substrate through a first medium; the polycrystalline silicon is arranged in the second groove unit and is used as a second gate region, and the polycrystalline silicon is isolated from the semiconductor substrate through a second medium; an N-type carrier barrier region disposed adjacent to a bottom of the first trench unit; the first P-type electric field shielding region is arranged at the bottom adjacent to the second groove unit; the P-type source body region is arranged at the inner side of the first groove unit at intervals, more than one N-type source region is arranged in the P-type source body region, the N-type source region is tightly attached to the first medium of the first groove unit, and the P-type source body region and the N-type source region are arranged on the surface of the semiconductor substrate; an upper region disposed at an interval between the first tank unit and the second tank unit; the first metal layer is arranged on the top of the semiconductor substrate, contacts the source region and isolates the upper region and part or all of the first groove units through a third medium; the second P-type electric field shielding region is arranged at the outer side of at least one of the first P-type electric field shielding regions at the outermost periphery; the P-type doped region is formed in the semiconductor substrate in the vertical direction and contacts the second P-type electric field shielding region and the first metal layer; a P-type semiconductor region disposed on a second side of the semiconductor substrate, the second side being opposite to the first side; and a second metal layer disposed in contact with the P-type semiconductor region.
The upper region is used for adjusting the diffusible range of the doped region at the bottom of the shallow groove, so that the semiconductor regions with different conductive properties can be prevented from being mutually compensated, and the grid control performance of the manufactured semiconductor device is stabilized. Secondly, through the parallel design of the shallow grooves of the first groove units, even if the etching windows of a few grooves are deviated, the concentration of the semiconductor area close to the deep groove can be adjusted, and the error of the structure matched with the deep groove is avoided, so that a poor conduction path is generated or an unexpected cavity channel is generated, and the conduction voltage drop of the device is greatly increased. Moreover, the upper region can indirectly define the width of an etching window required by the subsequent process of the source body region, which is beneficial to reducing the complexity of the arrangement of the source region. In addition, through the design of the double electric field shielding regions, most ionization donors with positive charges from the semiconductor substrate can be absorbed by ionization acceptors with negative charges in the electric field shielding regions, so that a power line reaching the source region is basically shielded, and the voltage resistance of the semiconductor device is further improved.
Drawings
FIG. 1 is a diagram of an exemplary structure of a semiconductor device using deep and shallow trench junctions;
fig. 2 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
fig. 3 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
fig. 4 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
fig. 5 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
fig. 6 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
fig. 7 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
fig. 8 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
fig. 9 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
fig. 10 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a punch-through or electric field stop cell according to an embodiment of the present disclosure;
FIG. 12 is a schematic diagram of a reverse conducting cell structure according to an embodiment of the present application;
fig. 13 is a schematic diagram of a cell structure of an electric field cut-off type combined with a reverse conducting type according to an embodiment of the present application.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. In the present application, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like are merely referring to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting.
The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.
In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.
To further illustrate the technical means and effects of the present application for achieving the intended purpose, the following detailed description is given to a cell structure and a semiconductor device using the same, with reference to the accompanying drawings and embodiments.
Fig. 1 is a diagram illustrating a structure of a semiconductor device combined by deep and shallow trenches. The device is composed of a plurality of unit cells. Fig. 1 illustrates a cross-sectional structural view of one of the cells. The structure of the unit cell comprises: an N-type semiconductor substrate 001, one side of the N-type semiconductor substrate 001 is provided with a P-type first semiconductor region 002, which serves as an anode region. The other side of the N-type semiconductor substrate 001 is provided with more than one first groove unit 700 and second groove unit 800, respectively, and the depth of the first groove unit 700 is smaller than that of the second groove unit 800. An N-type carrier barrier region 010, also called a minority carrier barrier region, having a higher doping concentration than the N-type semiconductor substrate 001 is provided at the bottom of the first trench cell 700, and a P-type electric field shielding region 101 is provided at the bottom of the second trench cell 800. The first trench unit 700 and the second trench unit 800 are disposed therein with a conductive material, which may be polysilicon or a material with conductive property. The conductive material in the first trench cell 700 serves as a first gate region 011 and the conductive material in the second trench cell 800 serves as a second gate region 111. The first gate region 011 and the second gate region 111 are isolated from the N-type semiconductor substrate 001 by the first dielectric 012 and the second dielectric 112, respectively. The side of the N-type carrier barrier region 010 contacts the second medium 112 of the second slot cell 800. The P-type source region 202 is disposed between the first trench cell 700 and the second trench cell 800, an N-type source region 303 is disposed in the P-type source region 202, and the N-type source region 303 is closely attached to the first dielectric 012 on one side of the first trench cell 700. A P-type floating semiconductor region 203 is provided outside the first trench cell 700 and the second trench cell 800. The first electrode 500 and the second electrode 502 include or are made of a metal material. The first electrode 500 is in contact with at least part of the first gate region 111, at least part of the P-type source body region 202 and at least part of the N-type source region 303, and the second electrode 502 covers the P-type first semiconductor region 002. A third medium 015 is arranged between the first gate region 011 and the first electrode 500 for isolation; a fourth dielectric 016 is disposed between the P-type floating semiconductor region 203 and the first electrode 500 for isolation. The first gate region 011 is a gate electrode of the device, and the first electrode 500 and the second electrode 502 are a cathode and an anode of the device, respectively.
In combination with the above, the first trench cell 700, the N-type carrier barrier region 010, the P-type source region 202, and the N-type source region 303 constitute one NMOS structure. The N-type source region 303 is a source region of electrons of the NMOS, the N-type carrier barrier region 010 is a drain region of electrons of the NMOS, and the first gate region 011 is a gate region of the NMOS. When the voltage V between the second electrode 502 and the first electrode 500CEGreater than zero and a voltage V between the first gate region 011 and the first electrode 500CEExceeds the threshold voltage V of the NMOSTHNAt this time, the NMOS channel is turned on, and electrons reach the P-type first semiconductor region 002 from the N-type source region 303 through the P-type source body region 202, the N-type carrier barrier region 010, and the N-type semiconductor substrate 001. On the other hand, holes pass from the P-type first semiconductor region 002 through the N-type semiconductor substrate 001 and the P-type electric field shielding region 101 to reach the N-type carrier barrier region 010. The built-in potential formed between the N-type semiconductor substrate 001 and the N-type carrier barrier region 010 hinders the flow of holes to the P-type source region 202, and the hole concentration in the N-type semiconductor substrate 001 is significantly increased near the N-type carrier barrier region 010 to form strong conductance modulation, thereby greatly increasing the current density of the device. Namely, the device has lower conduction voltage drop V than the IGBT under the same current densityON. Through reasonable design, the current of the device is reduced under the same turn-on voltage dropThe density is close to that of a Thyristor, so the device is named moscotrolled square-Thyristor, MCKT for short.
When the voltage V between the second electrode 502 and the first electrode 500CEAt a higher level, the negatively charged ionization acceptors in the partially depleted P-type electric field shielding region 101 absorb the electric lines of force generated from the positively charged ionization donors in the depleted N-type semiconductor substrate 001, so that only a few electric lines of force reach the gate region 011, and therefore the electric field around the dielectric layers at the bottoms of the first trench unit 700 and the second trench unit 800 is lower, so that a high blocking voltage can be obtained, and the service life of the dielectric layers is prolonged, thereby improving the reliability of the device. Since the P-type electric field shielding region 101 shields most of the electric lines of force from the N-type semiconductor substrate 001, the charges in the first gate region 011 become insensitive to the change of the collector potential, reflected as the gate-collector capacitance (C)GC) Is reduced.
In addition, adjusting the area ratio of the P-type floating semiconductor region 203 to the unit cell can obtain a suitable saturated collector current to obtain good short-circuit resistance. In the turn-off process of the ordinary IGBT, minority carriers are continuously injected into an anode to generate a trailing current, a large part of power loss in the turn-off process is generated by the trailing current, and the size of the trailing current is increased along with the increase of the injection efficiency of the minority carriers in the anode. Since the MCKT greatly increases the hole concentration on the N-type carrier barrier 010 side, the hole injection efficiency of the anode is allowed to be greatly reduced under the same on-state voltage drop, so that the proportion of the electron current to the total current is increased, the trailing current is reduced, and thus, smaller turn-off loss can be obtained.
Although the device shown in fig. 1 has the above advantages, the actual process requires a strict process control, so that holes can be effectively blocked, the N-type carrier barrier 010 needs to diffuse into and contact with the dielectric layer 112 of the second trench unit 800, and the concentration on the surface of the dielectric layer needs to be high, so the dosage of the N-type carrier barrier 010 is often high, and the higher dosage of the N-type carrier barrier 010 easily diffuses into and compensates for the P-type source region 202, so that the device loses the gate control capability and fails. In addition, when the trench etching window is misaligned, the concentration of the N-type carrier barrier region 010 on the surface of the dielectric layer 112 on one side is low, so that a channel is provided for holes to flow out of the device from the P-type source region 202, and the device loses the advantage of low conduction voltage drop.
Fig. 2 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. The cellular structure includes: a semiconductor substrate 001 of a first conductivity type; a plurality of groove units disposed on a first side of the semiconductor substrate 001, the groove units including a first groove unit 700 and a second groove unit 800, the first groove unit 700 being disposed at a distance from each other, the second groove unit 800 being disposed at both outer sides of the first groove unit 700; a first gate region 011 disposed in the first trench unit 700 and isolated from the semiconductor substrate 001 by a first dielectric 012; a second gate region 111 disposed in the second trench unit 800 and isolated from the semiconductor substrate 001 by a second medium 112; a carrier barrier region 010 of the first conductive type disposed adjacent to a bottom of the first trench cell 700; an electric field shielding region 101 of the second conductivity type disposed adjacent to the bottom of the second trench unit 800; a source region 202 of the second conductivity type, which is disposed at an inner interval of the first trench cell 700, wherein the source region 202 has one or more source regions 303, the source region 303 is closely attached to the first dielectric 012 of the first trench cell 700, and the source region 202 and the source region 303 are located on the surface of the semiconductor substrate 001; an upper region 203 disposed at an interval between the first tank unit 700 and the second tank unit 800; the first metal layer is arranged on the top of the semiconductor substrate 001, contacts the source region 202 and is isolated from the upper region 203 and part or all of the first gate region 011 through a third medium 015; a second electric field shielding region 201 of the second conductivity type disposed outside at least one of the first electric field shielding regions 101 at the outermost periphery; a doped region 103 of a second conductivity type formed in the semiconductor substrate 001 in a vertical direction, contacting the second electric field shielding region 201 and the first metal layer 500; and a second side of the semiconductor substrate 001 is provided with a first semiconductor region 002, the second side being an opposite side to the first side. A second metal layer is disposed at the bottom of the semiconductor device, and the second metal layer is the aforementioned second electrode 502, which is combined with the first semiconductor region 002 as an anode region. The first metal layer is the first electrode 500 as described above, which is used as a cathode region with respect to an anode region.
For the sake of understanding, the conductivity type of each semiconductor region is temporarily the same as that of fig. 1, the first conductivity type is N-type, and the second conductivity type is P-type, and the electrical characteristics are basically the same as those of the semiconductor device shown in fig. 1.
The device shown in fig. 2 differs from the device shown in fig. 1 in that the source region 202 is disposed between two first trench cells 700, and an upper region 203 is added between the first trench cell 700 and the second trench cell 800. The device operates on the same principle as the device of fig. 1, in the case of a semiconductor of the same conductivity type as fig. 1, when the voltage V between the second electrode 502 and the first electrode 500 is equal toCEGreater than zero and a voltage V between the first gate region 011 and the first electrode 500GEExceeds the threshold voltage V of an NMOS formed by the first trench cell 700, the N-type carrier barrier region 010, the P-type source body region 202 and the N-type source region 303THNAt this time, the NMOS channel is turned on, and electrons reach the P-type first semiconductor region 002 from the N-type source region 303 through the P-type source body region 202, the N-type carrier barrier region 010, and the N-type semiconductor substrate 001. On the other hand, holes pass from the P-type first semiconductor region 002 through the N-type semiconductor substrate 001 and the P-type electric field shielding region 101 to reach the N-type carrier barrier region. The built-in potential formed between the N-type semiconductor substrate 001 and the N-type carrier barrier region 010 obstructs the flow of holes to the P-type source region 202, and the added upper region 203 also obstructs the flow of holes out of the device, so that the hole concentration is significantly increased near the N-type carrier barrier region 010 and its vicinity to form strong conductance modulation, thereby greatly increasing the current density of the device. Namely, the device has lower conduction voltage drop V than the IGBT under the same current densityON. Due to the addition of the upper region 203, the N-type carrier barrier 010 does not need to diffuse to the dielectric layer 112 of the second trench unit 800 to contact therewith, nor does it need to require the N-type carrier barrier 010 to have a higher concentration near the surface of the dielectric layer, thereby enabling the provision of a higher concentration N-type carrier barrier 010So as to prevent the N-type carrier barrier region 010 from diffusing to the P-type source region 202 to compensate with it, and stabilize the gate control performance after the semiconductor device is manufactured. Second, even if the etching window of the trench (e.g., the first trench unit 700) is misaligned, a hole path is not formed between the first trench unit 700 and the second trench unit 800, thereby maintaining the predetermined low turn-on voltage drop functional properties of the semiconductor device.
In an embodiment of the present invention, the upper region 203 is used as a location for limiting generation of a hole path or an electron path, and the upper region 203 may be an N-type semiconductor region, a P-type semiconductor region, an insulating material or a conductive material according to design requirements without specific limitation as long as the requirement for blocking the hole path or the electron path is met.
In some embodiments, the third dielectric 015 is disposed on the surface of the semiconductor substrate 001 and between the second metal layer 500 and the semiconductor substrate 001, while partially covering the peripheral portion of the surface of the semiconductor region 102.
In some embodiments, under the influence of the doped region 103, the potential of the second electric field shielding region 201 is close to the potential of the cathode, the second electric field shielding region 201 and the semiconductor substrate 001 form a PN junction reverse bias, and start to be depleted, and most of the ionized donors with positive charges in the semiconductor substrate 001 are absorbed by the ionized acceptors with negative charges in the dual electric field shielding regions, so that the electric flux lines reaching the source region 202 are substantially shielded, and the voltage resistance of the semiconductor device is further improved.
In an embodiment of the present application, the upper region 203 further includes a third dielectric 016 disposed outside at least one of the second trench cells 800 and isolated from the first metal layer 500 by the third trench cell.
In an embodiment of the present application, the widths of the notches of the first and second slot units 700 and 800 are the same or different.
In an embodiment of the present application, the depth of the second slot cell 800 is greater than or equal to the depth of the first slot cell 700.
In an embodiment of the present application, an opening is disposed at a position of the third medium 015 corresponding to the notch of the second slot unit 800, and the first metal layer contacts the second gate region 111 through the opening.
In some embodiments, the surface of the second gate region 111 is entirely in contact with the first metal layer.
In some embodiments, the third dielectric 015 has a limited opening through which the first metal layer contacts a local surface of the second gate region.
In an embodiment of the present application, the source region 303 is of a first conductivity type or a second conductivity type.
In an embodiment of the present application, the source region 303 is a heavily doped region or a lightly doped region.
As shown in fig. 2, in an embodiment of the present application, the second electric field shielding region 201 contacts the first electric field shielding region 101.
Fig. 3 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. As shown in fig. 3, the second electric field shielding region 201 does not contact the first electric field shielding region 101.
Fig. 4 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. In an embodiment of the present application, the second electric field shielding region 201 is located below the outer side of the first electric field shielding region 101.
Fig. 5 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. In an embodiment of the present application, the doped region 103 and the first metal layer 500 are isolated from each other by the third dielectric 015.
Fig. 6 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. The difference from the example of fig. 2 is that the notch of the second slot cell 800 is covered by the third medium 015, and the first metal layer and the second gate region are isolated by the third medium.
In some embodiments, the conductive material in the second trench cell 800 may be designed to be opened in a certain direction to contact the first metal layer (the first electrode 500) by bypassing the third dielectric 015, or to be opened in a local area to contact the first metal layer, or to contact other grounding components.
Fig. 7 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. In an embodiment of the present application, the carrier barrier region 010 has only one, and the setting range is wide, and the first slot cell 700 simultaneously contacts the carrier barrier region 010.
Fig. 8 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. In an embodiment of the present application, the depths of the first trench unit and the second trench unit are the same or similar, and the depths of the electric field shielding region 101 and the carrier barrier region 010 disposed on the semiconductor substrate 001 are also the same or similar. The electric field shielding region 101 and the carrier barrier region 010 adjacent to each other may be selectively designed to contact each other or not.
Fig. 9 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. In an embodiment of the present invention, the second groove units 800 disposed at an outer side of the first groove unit 700 are plural, and the bottom portions of the plural second groove units are all adjacent to the electric field shielding region of the second conductivity type.
In one embodiment of the present application, the source body region 202 is further disposed in the space of the second trench unit 800 and contacts the first metal layer (the first electrode 500). when the semiconductor device operates at an extreme condition such as high voltage and large current, a large number of positive holes are injected from the P-type first semiconductor region 002 into the N-type semiconductor substrate 001 and reach the P-type electric field shielding region 101 to raise the potential of the P-type electric field shielding region 101. when the potential of the P-type electric field shielding region 101 is high to a certain extent, a PMOS formed by the P-type source body region 202, the N-type substrate 001 and the electric field shielding region 101 is turned on, a hole channel separated from an electron channel of an NMOS is formed next to the sidewall of the second trench unit 800. a large number of holes in the N-type semiconductor substrate 001 will pass through the P-type source body region 202 and finally reach the cathode-second electrode 500 of the MCKT to avoid a parasitic substrate L (which is formed by the N-type source body region, the P-type source region and the N-type field shielding region 800.
Fig. 10 is a schematic diagram of a cell structure of a semiconductor device according to an embodiment of the present application. In an embodiment of the present application, a second semiconductor region 102 of the first conductivity type having a doping concentration different from that of the substrate region 001 is disposed between the second trench cells 800, and the second semiconductor region 102 is adjacent to the source region 202. A PMOS structure is formed by the second trench cell 800, the source region 202, the second semiconductor region 102, and the electric field shielding region 101, wherein the P-type electric field shielding region 101 is a source region of holes of the PMOS, and the P-type source region 202 is a drain region of holes of the PMOS.
In an embodiment of the present application, the source region 202 is further disposed in the space of the second trench unit 800 and contacts the first metal layer 500.
In an embodiment of the present application, the source region is an electron source region when the source region is an N-type, and the source region is a hole source region when the source region is a P-type.
In an embodiment of the present application, a first semiconductor region 002 is disposed between the semiconductor substrate 001 and the second metal layer 502. As described above, the first semiconductor region 002 is of the second conductivity type; alternatively, the conductivity type of the first semiconductor region 002 is equal to that of the semiconductor substrate 001.
One side of the first semiconductor region 002 is provided with a third semiconductor region 003 having the same or different conductivity type as that of the first semiconductor region.
In an embodiment of the present application, a side edge of the same layer of the first semiconductor region 002 is provided with a fourth semiconductor region 004 having a different conductivity type from the first semiconductor region.
Fig. 11 is a schematic structural diagram of a punch-through or electric field stop cell according to an embodiment of the present application. In an embodiment of the present application, one side of the first semiconductor region 002 is provided with a third semiconductor region 003 of the first conductivity type, which serves as a field stop region, and the doping concentration of the third semiconductor region 003 is higher than that of the semiconductor substrate 001. When the highest voltage is applied between the collector and the emitter, the electric field is cut off in the field cut-off region, and the field cut-off region is not fully depleted. Thus the electricity formed in FIG. 11The field stop structure can obtain smaller thickness of the semiconductor substrate 001, thereby obtaining smaller on-state voltage drop (V)ON). Secondly, the total amount of carriers in the semiconductor substrate 001 is proportional to the thickness of the semiconductor substrate 001, so that the total amount of carriers can be reduced. At a certain current, the time required for the semiconductor device to go from the on-state to the off-state or from the off-state to the on-state is shorter, and thus a smaller switching loss is obtained.
Fig. 12 is a schematic structural diagram of a reverse conducting cell according to an embodiment of the present application. In an embodiment of the present application, a side edge of the same layer of the first semiconductor region 002 is provided with a fourth semiconductor region 004 of the first conductivity type. Both the semiconductor region 002 and the fourth semiconductor region 004 are in direct contact with the second electrode 502, forming an Anode Short (Anode Short) structure. The first conductivity type is an N-type, and the second conductivity type is a P-type. In an embodiment of the present application, when the potential of the first electrode 500 is higher than the potential of the second electrode 502, the body diode is forward biased, and a current flows from the P-type source body region 202 to the N-type fourth semiconductor region 004 through the N-type carrier barrier region 010 and the N-type semiconductor substrate 001. Due to the presence of the N-type carrier barrier region 010, the anode hole injection efficiency of the body diode is greatly reduced, thereby obtaining an extremely low charge concentration near the anode region when the body diode is turned on. Fig. 13 is a schematic diagram of a cell structure combining an electric field cut-off type and a reverse conducting type according to an embodiment of the present application, where the structure shown in the present application has the electrical characteristics described in fig. 11 and 12, and details are not repeated here.
In one embodiment of the present application, the semiconductor substrate 001 shown in fig. 1 to 10 is a Non-punch through (Non punch through), i.e., the semiconductor substrate 001 is not fully depleted when the highest voltage is applied between the collector and the emitter; FIG. 11 shows a Punch-Through (Punch Through) or Field Stop (Field Stop) cell; FIG. 12 shows a reverse conducting (Reversecduction) cell; fig. 13 is a combination of the structures of fig. 11 and 12. However, the above-described embodiments are not limited to the respective structures shown in the drawings, and a Non-Punch-Through (Non Punch Through) structure, a Punch Through (Punch Through), a Field Stop (Field Stop), an Anode Short (Anode Short) structure, or a structure equivalent to or similar to the above-described structure is applied to each of the embodiments.
In an embodiment of the present invention, the above-mentioned designs of the plurality of adjacent second trench units 800, the second electric field shielding regions and their associated structures are not limited to the above-mentioned examples, and the structures of the embodiments and examples of the present invention can also be used, but not limited to the examples in the specification, and the same, related, similar and equivalent semiconductor device structures are also applicable.
In an embodiment of the present application, the first gate region 011 and the second gate region 111 are conductive materials, which include polysilicon or metal materials with conductivity.
In an embodiment of the present application, the material of each of the aforementioned semiconductors includes a silicon (Si) material or a silicon carbide (SiC) material.
In an embodiment of the present invention, the first dielectric 012, the second dielectric 112, the third dielectric 015, and the fourth dielectric 016 may be selectively made of an insulating material including silicon dioxide, benzocyclobutene (BCB), Polyimide (PI), a composite layer of silicon dioxide and other materials, such as a composite layer of silicon dioxide and silicon nitride, a composite layer … of silicon dioxide and Polyimide (PI), and the like.
Another object of the present invention is to provide a semiconductor device including a cell region and a termination region, wherein the cell region includes one or more cells, and the structure of the cells includes: an N-type semiconductor substrate 001; a plurality of groove units arranged on a first side of the N-type semiconductor substrate 001, wherein polycrystalline silicon is arranged in the groove units, the groove units comprise a first groove unit 700 and a second groove unit 800, the first groove unit 700 is arranged in a separated manner, and the second groove unit 800 is arranged on two outer sides of the first groove unit 700; the polysilicon is arranged in the first trench unit 700 as a first gate region 011, which is isolated from the semiconductor substrate 001 by a first dielectric 012; the polysilicon is arranged in the second trench unit 800 as a second gate region 111, and is isolated from the semiconductor substrate 001 through a second medium 112; an N-type carrier barrier region 010 disposed adjacent to a bottom of the first trench cell 700; a P-type electric field shielding region 101 disposed adjacent to the bottom of the second trench unit 800; the P-type source region 202 is disposed at an inner interval of the first trench unit 700, the P-type source region 202 is provided with more than one N-type source region 303, the N-type source region 303 is tightly attached to the first medium 012 of the first trench unit 700, and the P-type source region 202 and the N-type source region 303 are located on the surface of the semiconductor substrate 001; an upper region 203 disposed at an interval between the first tank unit 700 and the second tank unit 800; a first metal layer disposed on top of the semiconductor substrate 001, the first metal layer contacting the source region 202 and isolating the upper region 203 and isolating a part or all of the first trench cell 700 through a third dielectric 015; a second P-type electric field shielding region 201 disposed outside at least one of the first P-type electric field shielding regions 101 at the outermost periphery; a P-type doped region 103 formed in the semiconductor substrate 001 in a vertical direction, contacting the second P-type electric field shielding region 201 and the first metal layer 500; a P-type semiconductor region 002 disposed on a second side of the semiconductor substrate 001, the second side being opposite to the first side; and a second metal layer 502 provided in contact with the P-type semiconductor region 002.
The upper region is used for adjusting the diffusible range of the doped region at the bottom of the shallow groove, so that the semiconductor regions with different conductive properties can be prevented from being mutually compensated, and the grid control performance of the manufactured semiconductor device is stabilized. And secondly, the upper region additionally arranged in the device blocks the cavity from flowing out of the device, so that a cavity channel generated by the deviation of the groove etching window can be avoided, the etching tolerance of the groove is increased, and the preset functional property of low conduction voltage drop of the semiconductor device is maintained. In addition, through the design of the double electric field shielding regions, most ionization donors with positive charges from the semiconductor substrate can be absorbed by ionization acceptors with negative charges in the electric field shielding regions, so that a power line reaching the source region is basically shielded, and the voltage resistance of the semiconductor device is further improved.
As previously mentioned, the first conductivity type is different from the second conductivity type, for example: the first conductive type is P type, and the second conductive type is N type; alternatively, the first conductivity type is N-type and the second conductivity type is P-type, that is, the N-type and the P-type in the above description can be interchanged, and the corresponding electron and hole can be interchanged, and the principle of the present application can still be applied after the interchange.
The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.
Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (10)
1. A cell structure of a semiconductor device, the cell structure comprising:
a semiconductor substrate of a first conductivity type;
the semiconductor substrate comprises a semiconductor substrate, a plurality of groove units and a plurality of control units, wherein the plurality of groove units are arranged on a first side of the semiconductor substrate and comprise a first groove unit and a second groove unit, the first groove unit is arranged in a separated mode, and the second groove unit is arranged on two outer sides of the first groove unit;
the first gate region is arranged in the first groove unit and is isolated from the semiconductor substrate through a first medium;
the second gate region is arranged in the second groove unit and is isolated from the semiconductor substrate through a second medium;
a carrier barrier region of the first conductivity type disposed adjacent to a bottom of the first trench cell;
a first electric field shielding region of the second conductivity type disposed adjacent to a bottom of the second trench unit;
the source body region of the second conduction type is arranged at the inner side interval of the first groove unit and is provided with more than one source region of the first conduction type, the source regions are tightly attached to the first medium of the first groove unit, and the source body region and the source regions are arranged on the surface of the semiconductor substrate;
an upper region disposed at an interval between the first tank unit and the second tank unit;
the first metal layer is arranged on the top of the semiconductor substrate, contacts the source region and isolates the upper region and part or all of the first groove units through a third medium;
a second electric field shielding region of the second conductivity type disposed outside at least one of the first electric field shielding regions at an outermost periphery;
a doped region of a second conductivity type formed in the semiconductor substrate in a vertical direction contacting the second electric field shielding region and the first metal layer;
a first semiconductor region disposed on a second side of the semiconductor substrate, the second side being opposite to the first side; and
a second metal layer disposed in contact with the first semiconductor region.
2. The cell structure of the semiconductor device of claim 1, wherein the second electric field shielding region is in contact with or not in contact with the first electric field shielding region.
3. The cell structure of the semiconductor device of claim 1, wherein the second electric field shielding region is located below an outer side of the first electric field shielding region.
4. The cell structure of the semiconductor device of claim 1, wherein the doped region and the first metal layer are isolated from each other by the third dielectric.
5. The cell structure of a semiconductor device of claim 1, wherein the upper region further comprises a third dielectric disposed outside at least one of the second trench cells and isolated from the first metal layer by the third dielectric.
6. The cell structure of the semiconductor device of claim 1, wherein the surface of the second gate region is entirely in contact with the first metal layer; or, an opening is arranged at a local position of the third medium corresponding to the notch position of the second slot unit, and the first metal layer contacts the second gate region through the opening.
7. The cell structure of the semiconductor device according to claim 1, wherein widths of the notches of the first groove unit and the second groove unit are the same or different; the depth of the second groove unit is greater than or equal to the depth of the first groove unit.
8. The cell structure of the semiconductor device according to claim 1, wherein the second trench units are disposed at an outer side of the first trench units, and the bottom portions of the second trench units are adjacent to the electric field shielding region of the second conductivity type; the electric field shielding region is at least adjacent to the electric field shielding region; and the source region is also arranged in the interval of the second groove unit and contacts the first metal layer.
9. The cell structure of the semiconductor device according to claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.
10. A semiconductor device comprising a cell region and a termination region, wherein the cell region comprises one or more cells, and wherein the structure of the cells comprises:
an N-type semiconductor substrate;
the N-type semiconductor substrate comprises a plurality of N-type semiconductor substrates, a plurality of groove units and a plurality of control units, wherein the N-type semiconductor substrates are arranged on the first sides of the N-type semiconductor substrates;
the polycrystalline silicon is arranged in the first groove unit and is used as a first gate region, and the polycrystalline silicon is isolated from the semiconductor substrate through a first medium;
the polycrystalline silicon is arranged in the second groove unit and is used as a second gate region, and the polycrystalline silicon is isolated from the semiconductor substrate through a second medium;
an N-type carrier barrier region disposed adjacent to a bottom of the first trench unit;
the first P-type electric field shielding region is arranged at the bottom adjacent to the second groove unit;
the P-type source body region is arranged at the inner side of the first groove unit at intervals, more than one N-type source region is arranged in the P-type source body region, the N-type source region is tightly attached to the first medium of the first groove unit, and the P-type source body region and the N-type source region are arranged on the surface of the semiconductor substrate;
a P-type upper region disposed at an interval between the first and second groove units; and
the first metal layer is arranged on the top of the semiconductor substrate, contacts the source region and isolates the upper region and part or all of the first groove units through a third medium;
the second P-type electric field shielding region is arranged at the outer side of at least one of the first P-type electric field shielding regions at the outermost periphery;
the P-type doped region is formed in the semiconductor substrate in the vertical direction and contacts the second P-type electric field shielding region and the first metal layer;
a P-type semiconductor region disposed on a second side of the semiconductor substrate, the second side being opposite to the first side; and
and the second metal layer is arranged to contact the P-type semiconductor region.
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| DE102021107975A1 (en) | 2021-03-30 | 2022-10-06 | Infineon Technologies Ag | Cell design for MOS controlled power semiconductor device |
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| DE102021107975A1 (en) | 2021-03-30 | 2022-10-06 | Infineon Technologies Ag | Cell design for MOS controlled power semiconductor device |
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