CN116110791A - Trench type insulated gate field effect transistor, manufacturing method thereof and electronic device - Google Patents

Abstract

The present disclosure relates to a trench type insulated gate field effect transistor, a method of manufacturing the same, and an electronic device. The method comprises the following steps: forming a trench, wherein the trench penetrates the first and second preformed semiconductor layers and extends into the preformed composite substrate, the first and preformed composite substrates having a first doping type, the second preformed semiconductor layer having a second doping type; forming an intrinsic region located at the bottom side of the trench and extending into the pre-fabricated composite substrate; and forming an insulated gate structure, wherein the insulated gate structure is filled in the groove. The method can form an intrinsic region at the bottom side of the groove, and then a device with better comprehensive performance is manufactured.

Description

Trench type insulated gate field effect transistor, manufacturing method thereof and electronic device

Technical Field

The disclosure relates to the technical field of semiconductors, in particular to a trench type insulated gate field effect transistor, a manufacturing method thereof and an electronic device.

Background

Insulated gate field effect transistors (MOSFETs) are widely used in the power electronics industry. The traditional MOSFET device adopts a planar structure, and the device has a plurality of breakthroughs in the aspects of realizing high blocking voltage, high switching speed and other performances. However, due to structural limitations, parasitic Junction Field Effect Transistors (JFETs) are present in planar MOSFET devices, and the resulting JFET effect results in a planar MOSFET device with insufficient specific on-resistance.

Compared with a planar insulated gate field effect transistor, the trench insulated gate field effect transistor can avoid a JFET region, thereby having smaller cell size and greatly reducing on-resistance. However, when large voltages are blocked, the bottom of the insulated gate of the trench type insulated gate field effect transistor is subjected to a high electric field, and the reliability of the insulating layer of the insulated gate is threatened. The long-term reliability of trench insulated gate field effect transistors is affected.

Disclosure of Invention

Based on this, it is necessary to provide a trench type insulated gate field effect transistor, a method for manufacturing the trench type insulated gate field effect transistor and an electronic device against the high electric field threat problem of the bottom of the insulated gate.

Embodiments of the present disclosure provide a method for manufacturing a trench insulated gate field effect transistor, the method comprising: forming a trench, wherein the trench penetrates the first and second preformed semiconductor layers and extends into the preformed composite substrate, the first and preformed composite substrates having a first doping type, the second preformed semiconductor layer having a second doping type; forming an intrinsic region located at the bottom side of the trench and extending into the pre-fabricated composite substrate; and forming an insulated gate structure, wherein the insulated gate structure is filled in the groove.

The method provided by the embodiment of the disclosure can form the intrinsic region at the bottom side of the groove, so that the bottom of the insulated gate structure is protected, and meanwhile, the method is favorable for maintaining the better conductive property of the groove type insulated gate field effect transistor.

In some embodiments, the method comprises: and forming a first pre-doped region according to the intrinsic region, wherein the first pre-doped region extends into the pre-fabricated composite substrate and has a second doping type, and the first pre-doped region has a first position and a second position which is far away from the groove relative to the first position, and the doping concentration at the second position is larger than that at the first position.

The method can well protect the bottom of the insulated gate, and ensures better conductive property of the trench type insulated gate field effect transistor by setting the doping concentration at the first position to be lower.

In some embodiments, the method further comprises: forming a first pre-doped region extending into the pre-fabricated composite substrate, the first pre-doped region being located at a bottom side of the trench and having a second doping type; the step of forming the intrinsic region includes: an intrinsic region is formed extending through at least a portion of the first pre-doped region.

The method can form the first prefabricated doped region and then form the intrinsic region, is convenient to implement, and can obtain the trench type insulated gate field effect transistor with good comprehensive performance.

In some embodiments, the method further comprises: a second pre-doped region is formed from the intrinsic region, the second pre-doped region having the first doping type.

The method can form the trench type insulated gate field effect transistor with better conductivity.

In some embodiments, the intrinsic region is formed by an ion implantation process.

The manner of ion implantation is controllably effective and intrinsic regions can be formed based on the structure that has been doped.

In some embodiments, the method further comprises: forming a source metal layer in ohmic contact with the first prefabricated semiconductor layer; and forming a drain metal layer in ohmic contact with the prefabricated composite substrate.

The method provided by the embodiment of the disclosure can be used for manufacturing the trench type insulated gate field effect transistor, and the conductivity between the drain electrode metal layer and the source electrode metal layer is good and the blocking is reliable.

The disclosed embodiments provide a trench insulated gate field effect transistor, comprising: the semiconductor device comprises a composite substrate, a channel layer and a first source contact region which are stacked in sequence, wherein the composite substrate and the first source contact region are provided with a first doping type, and the channel layer is provided with a second doping type; an insulated gate structure penetrating the first source contact region and the channel layer; and the protective layer is positioned between the insulated gate structure and the composite substrate along the stacking direction, and is provided with a first position and a second position which is far away from the insulated gate structure relative to the first position, the doping type at the second position and the doping type at the first position are both second doping types, and the doping concentration at the second position is larger than that at the first position.

The trench type insulated gate field effect transistor provided by the embodiment of the disclosure can have lower on-resistance, and can realize better protection of an insulated gate structure. The trench type insulated gate field effect transistor is suitable for a high-voltage working environment and has good long-term reliability.

The embodiment of the disclosure also provides a trench type insulated gate field effect transistor, which comprises: the semiconductor device comprises a composite substrate, a channel layer and a first source contact region which are stacked in sequence, wherein the composite substrate and the first source contact region are provided with a first doping type, and the channel layer is provided with a second doping type; an insulated gate structure penetrating the first source contact region and the channel layer; and a protective layer located between the insulated gate structure and the composite substrate along the stacking direction, wherein the protective layer has a first position and a second position far away from the insulated gate structure relative to the first position, the doping type at the second position is a second doping type, and the doping type at the first position is an intrinsic type or a first doping type.

The trench type insulated gate field effect transistor can realize better protection of an insulated gate structure, obtains lower on-resistance and has better conductivity.

The present disclosure also provides, in another aspect, a trench isolation gate field effect transistor including: the semiconductor device comprises a composite substrate, a channel layer and a first source contact region which are stacked in sequence, wherein the composite substrate and the first source contact region are provided with a first doping type, and the channel layer is provided with a second doping type; an insulated gate structure penetrating the first source contact region and the channel layer; and an intrinsic region located between the insulated gate structure and the composite substrate along the stacking direction.

The trench type insulated gate field effect transistor provided by the embodiment of the disclosure can have lower on-resistance, and can realize better protection of an insulated gate structure. The trench type insulated gate field effect transistor is suitable for a high-voltage working environment and has good long-term reliability.

An electronic device, comprising: the trench type insulated gate field effect transistor; and the circuit is electrically connected with the trench type insulated gate field effect transistor.

The electronic device provided by the embodiment of the disclosure has relatively low electrical loss, can be suitable for a high-voltage environment, and has relatively high reliability.

Drawings

Fig. 1 is a flow chart of a method for manufacturing a trench insulated gate field effect transistor provided by an embodiment of the present disclosure;

fig. 2 is a flow chart of a method for fabricating a trench insulated gate field effect transistor provided by an embodiment of the present disclosure;

fig. 3 is a schematic view of a semiconductor structure after forming a second prefabricated semiconductor layer according to an embodiment of the present disclosure;

fig. 4 is a schematic view of a semiconductor structure after forming a first prefabricated semiconductor layer according to an embodiment of the present disclosure;

fig. 5 is a schematic view of a semiconductor structure after forming a third prefabricated semiconductor layer according to an embodiment of the present disclosure;

fig. 6 is a schematic view of a semiconductor structure after forming a trench according to an embodiment of the present disclosure;

fig. 7 is a schematic view of a semiconductor structure after forming a first intrinsic region according to an embodiment of the present disclosure;

fig. 8 is a schematic view of a semiconductor structure after forming a first pre-doped region according to an embodiment of the present disclosure;

fig. 9 is a schematic view of a semiconductor structure after forming a second intrinsic region according to an embodiment of the present disclosure;

fig. 10 is a schematic view of a semiconductor structure after forming a second pre-doped region according to an embodiment of the present disclosure;

fig. 11 is a schematic view of a semiconductor structure after forming a second intrinsic region according to an embodiment of the present disclosure;

fig. 12 is a schematic view of a semiconductor structure after forming a prefabricated insulating layer according to an embodiment of the present disclosure;

fig. 13 is a schematic view of a semiconductor structure after forming a prefabricated gate according to an embodiment of the present disclosure;

fig. 14 is a schematic view of a semiconductor structure after forming an interlayer dielectric according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 16 is a layout of a natural depletion region in a drift region of a trench isolation gate field effect transistor according to an embodiment of the present disclosure;

fig. 17 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 18 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 19 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 20 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 21 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 22 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 23 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 24 is a schematic structural diagram of a trench insulated gate field effect transistor provided by an embodiment of the present disclosure;

fig. 25 is a schematic structural diagram of a trench insulated gate field effect transistor provided in an embodiment of the present disclosure;

fig. 26 is a block diagram of an electronic device provided in an embodiment of the present disclosure.

Reference numerals illustrate: 1. prefabricating a substrate; 2. prefabricating an epitaxial layer; 3. prefabricating a composite substrate; 4. a second prefabricated semiconductor layer; 5. a first mask; 6. a first prefabricated semiconductor layer; 7. a second mask; 8. a third prefabricated semiconductor layer; 9. a preform region; 10. a third mask; 11. a groove; 12. a first intrinsic region; 13. a first pre-doped region; 14. a second intrinsic region; 15. prefabricating a protective layer; 16. a second pre-doped region; 17. prefabricating an insulating layer; 18. prefabricating a grid; 19. an interlayer medium;

100. a trench insulated gate field effect transistor; 101. a substrate; 102. a drift layer; 103. a composite substrate; 104. a channel layer; 105. a second source contact region; 106. a body region; 1061. a contact portion; 107. a first source contact region; 108. a gate; 109. an insulating layer; 110. an insulated gate structure; 111. a protective layer; 112. an intrinsic region; 113. a first doped region; 114. a source metal layer; 115. a drain metal layer; 116. a second doped region;

200. a circuit; 300. an electronic device.

Detailed Description

In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, a detailed description of specific embodiments of the present disclosure is provided below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. The disclosed embodiments may be embodied in many other forms other than described herein and similar modifications may be made by those skilled in the art without departing from the spirit of the disclosed embodiments, so that the disclosed embodiments are not limited to the specific examples of embodiments described below.

In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the embodiments of the present disclosure and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of the present disclosure.

In the presently disclosed embodiments, unless expressly stated and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intermediary. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. For example, the first prefabricated semiconductor layer may also be referred to as a second prefabricated semiconductor layer, which may also be referred to as a first prefabricated semiconductor layer. In the description of the embodiments of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise.

In the presently disclosed embodiments, the terms "connected," "connected," and the like are to be construed broadly and, unless otherwise specifically indicated and defined, as being either fixedly connected, detachably connected, or integrally formed, for example; can be flexible connection or rigid connection along at least one direction; can be mechanically or electrically connected; either directly, indirectly, through intermediaries, or both, or in which case the intermediaries are present, or in which case the two elements are in communication or in which case they interact, unless explicitly stated otherwise. The terms "mounted," "disposed," "secured," and the like may be construed broadly as connected. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.

As used herein, the terms "layer," "region" and "regions" refer to portions of material that include regions having a certain thickness. The layers can extend horizontally, vertically and/or along a tapered surface. The layer can be a region of uniform or non-uniform continuous structure, whose thickness perpendicular to the direction of extension may be no greater than the thickness of the continuous structure. The layer can include multiple layers. The various regions in the figures, the shapes of the layers and their relative sizes and positional relationships are exemplary only, as may be subject to variations due to manufacturing tolerances or technical limitations, and may be adjusted to actual requirements.

Referring to fig. 1, fig. 1 illustrates a process flow for fabricating a trench insulated gate field effect transistor in an embodiment of the present disclosure. The method 1000 for manufacturing a trench type insulated gate field effect transistor provided in an embodiment of the present disclosure includes the following steps S101 to S103.

Step S101, forming a trench. The prefabricated semiconductor structure comprises a prefabricated composite substrate, a second prefabricated semiconductor layer and a first prefabricated semiconductor layer which are stacked in sequence. The trench extends through the first and second preformed semiconductor layers and may extend into the preformed composite substrate. The first prefabricated semiconductor layer and the prefabricated composite substrate may have a first doping type, for example n-type doping or electron-type doping; the second prefabricated semiconductor layer may have a second doping type, for example p-type doping or hole-type doping.

In step S102, an intrinsic region is formed. The intrinsic region is located at the bottom side of the trench and extends into the pre-fabricated composite substrate. While the location of the intrinsic region is described as such, embodiments of the present disclosure do not exclude the manner in which the intrinsic region is formed first and then the trench is formed.

Step S103, forming an insulated gate structure. The insulated gate structure is filled in the trench.

According to the method provided by the embodiment of the disclosure, the intrinsic region is arranged at the bottom side of the insulated gate structure, so that the bottom of the insulated gate structure can be protected, and the reliability of the insulated gate structure is improved. In addition, the on-resistance of the prefabricated composite substrate is reduced, and the manufactured trench type insulated gate field effect transistor has good comprehensive electrical performance.

Referring to fig. 2, fig. 2 illustrates a process flow for fabricating a trench insulated gate field effect transistor in an embodiment of the disclosure. The method 2000 for manufacturing a trench type insulated gate field effect transistor according to an embodiment of the present disclosure includes the following steps S210 to S240.

In step S210, a trench is formed.

In step S220, the first pre-doped region may be formed by ion implantation. Illustratively, step S220 may include: step S221, forming a first intrinsic region; and step S222, forming a first pre-doped region according to the first intrinsic region.

In step S230, the first pre-doped region may be formed by ion implantation. Illustratively, step S230 may include step S231, forming a second intrinsic region. Step S230 may further include step S232 of forming a second pre-doped region from the second intrinsic region. In other embodiments, the second intrinsic region may be formed from the first pre-doped region.

In step S240, an insulated gate structure is formed.

The method provided by the embodiment of the disclosure can form the trench type insulated gate field effect transistor with rich structure.

A method for manufacturing a trench insulated gate field effect transistor in an embodiment of the present disclosure is described in detail with reference to fig. 3 to 14, wherein fig. 3 to 9, 12 to 14 show process diagrams of the method.

Fig. 3 illustrates the semiconductor structure after forming a second pre-formed semiconductor layer in an embodiment of the present disclosure. As shown in fig. 3, a preformed substrate 1, a preformed epitaxial layer 2, and a second preformed semiconductor layer 4 are stacked in order along the Z-axis direction. The structure shown in fig. 3 may be obtained by sequentially growing n-type epitaxy and p-type epitaxy on the pre-fabricated substrate 1, or may be obtained by epitaxially growing a thicker pre-fabricated epitaxial layer 2 on the pre-fabricated substrate 1, then performing ion implantation to form a second pre-fabricated semiconductor layer 4, and obtaining the remaining pre-fabricated epitaxial layer 2. The ion implantation process can implant aluminum ions. The doping element of the second prefabricated semiconductor layer 4 may include an aluminum element.

The pre-formed substrate 1 may have a first doping type, for example n+ type doping, and the pre-formed epitaxial layer 2 may have n type doping. The second prefabricated semiconductor layer 4 may have a second doping type, for example p-type doping, and the second prefabricated semiconductor layer 4 may be a p-well region. The pre-fabricated substrate 1 and the pre-fabricated epitaxial layer 2 may be used to constitute the pre-fabricated composite substrate 3, but this does not exclude the case that the pre-fabricated composite substrate 3 may comprise only the pre-fabricated epitaxial layer 2. In other embodiments, the pre-fabricated composite substrate 3 further comprises other functional layers, such as a transition layer between the pre-fabricated substrate 1 and the pre-fabricated epitaxial layer 2.

The material of the preformed composite substrate 3 comprises at least one of silicon carbide, silicon germanium, a group iii-v compound such as gallium nitride and gallium arsenide. For example, the material of the prefabricated composite substrate 3 comprises silicon carbide, and then the formed trench type insulated gate field effect transistor can realize high blocking voltage and high switching speed. At the side wall of the insulated gate structure, the silicon carbide crystal can be embodied as a {1-100} crystal face or a {11-20} crystal face, and the mobility of the crystal faces is high, so that the trench type insulated gate field effect transistor has low specific on-resistance.

The doping concentration of the pre-formed substrate 1 may be greater than the doping concentration of the pre-formed epitaxial layer 2. It will be appreciated that. The "doping concentration" in the present disclosure generally refers to the free carrier concentration that exhibits electrical properties. For example, the doping concentration of an electron-type semiconductor means the concentration of free electrons, and the doping concentration of a hole-type semiconductor means the concentration of holes. The free electron concentration of the electron type semiconductor exceeds the hole concentration by an order of magnitude; the hole concentration of the hole semiconductor is orders of magnitude higher than the free electron concentration.

Fig. 4 illustrates a semiconductor structure after forming a first prefabricated semiconductor layer in an embodiment of the present disclosure. The first mask 5 may be formed and patterned, and the material of the first mask 5 may include silicon oxide. Ion implantation may then be performed using the first mask 5 to form the first prefabricated semiconductor layer 6. The first prefabricated semiconductor layer 6 may have an n+ -type doping. The doping element of the first prefabricated semiconductor layer 6 may comprise nitrogen. As shown in fig. 4, the prefabricated semiconductor structure may have symmetrical halves along the X-axis direction. The structure in the first region a or the second region B can be described to understand the overall structure. Of course, the prefabricated semiconductor structure may not be entirely symmetrical, the presently disclosed embodiments being illustratively implemented only in the first region a.

Fig. 5 illustrates the semiconductor structure after forming a third prefabricated semiconductor layer in an embodiment of the present disclosure. The second mask 7 may be formed after removing the first mask 5, and the material of the second mask 7 may include silicon oxide, which may cover the first prefabricated semiconductor layer 6. Ion implantation may then be performed using the second mask 7 to form a third prefabricated semiconductor layer 8. The ion implantation process can implant aluminum ions. The third prefabricated semiconductor layer 8 may have a p+ -type doping. The doping element of the third prefabricated semiconductor layer 8 may include an aluminum element. As shown in fig. 5, the second prefabricated semiconductor layer 4 and the third prefabricated semiconductor layer 8 can be used to form a prefabricated body region 9, the prefabricated body region 9 having the second doping type.

Fig. 6 illustrates the semiconductor structure after forming a trench in an embodiment of the present disclosure. The second mask 7 may be removed and a third mask 10 may be formed, and the material of the third mask 10 may include silicon oxide. A trench 11 may then be formed by an etching process using the third mask 10, the trench 11 penetrating the first and second pre-formed semiconductor layers 6, 4 and may extend into the pre-formed epitaxial layer 2 of the pre-formed composite substrate 3.

Fig. 7 schematically illustrates the semiconductor structure after forming the first intrinsic region in an embodiment of the present disclosure. Illustratively, the first intrinsic region 12 extending into the pre-formed epitaxial layer 2 may be formed at the bottom side of the trench 11 by ion implantation, such as aluminum ion implantation, of the bottom wall of the trench 11. The first intrinsic region 12 may be referred to as an intrinsic region. It is understood that the free electron concentration and the hole concentration of the intrinsic region are approximately equal.

In other embodiments, the first intrinsic region 12 may be formed first after the formation of the pre-formed epitaxial layer 2, and then epitaxial growth may be continued. And then at least a portion of the first intrinsic region 12 is exposed when forming the trench 11.

Fig. 8 illustrates the semiconductor structure after forming a first pre-doped region in an embodiment of the present disclosure. The first pre-doped region 13 may be formed from the first intrinsic region 12. Illustratively, the ion implantation process may be performed continuously to obtain the structure shown in fig. 8 in one step in the structure shown in fig. 6. In some embodiments, the depth and dose of ion implantation may be controlled to achieve a graded doping concentration of the first pre-doped region 13, and the deeper the location the greater the doping concentration may be. Illustratively, the doping concentration of the first pre-doped region 13 may also take a multi-stage state, where the first pre-doped region 13 has a first location and a second location remote from the trench 11 relative to the first location, and the doping concentration at the second location is greater than the doping concentration at the first location. For example, the bottom of the first pre-doped region 13 may have p+ doping and the top may have approximately zero doping concentration.

Figure 9 illustrates the semiconductor structure after forming a second intrinsic region in an embodiment of the present disclosure. Illustratively, the first pre-doped region 13 has a p+ -type doping. Illustratively, the first pre-doped region 13 has a hole-type doping and the doping concentration is graded along the Z-axis direction. As shown in fig. 9, the second intrinsic region 14 extending into a portion of the first pre-doped region 13 may be formed by an ion implantation process. Understandably, at the second intrinsic region 14, the multiple doping balances the implanted p-type ions and n-type ions. The free electron concentration and the hole concentration of the second intrinsic region 14 are approximately equal, and the second intrinsic region 14 may be referred to as an intrinsic region.

The second intrinsic region 14 and the first pre-doped region 13 may be used to constitute a pre-fabricated protection layer 15. The first pre-doped region 13 is farther from the trench 11, in other words the second intrinsic region 14 is closer to the trench. In the pre-formation protective layer 15, the hole concentration of the first pre-formation doped region 13 is larger than that of the second intrinsic region 14 with the majority carrier concentration of the first pre-formation doped region 13, i.e., the hole concentration, as a viewing angle. Illustratively, when the doping concentration of the first pre-doped region 13 is graded, the depth and concentration of the ion implantation of step S231 need to be controlled to ensure that the second intrinsic region 14 is formed.

Fig. 10 illustrates the semiconductor structure after forming a second pre-doped region in an embodiment of the present disclosure. A second pre-doped region 16 may be formed from the second intrinsic region 14. The second pre-doped region 16 has a first doping type, for example n-type doping. Illustratively, ion implantation may be performed continuously to obtain the structure shown in fig. 10 in one step in the structure shown in fig. 8. The doping concentration of the second pre-doped region 16 may be comparable to the doping concentration of the pre-epitaxial layer 2.

Figure 11 illustrates the semiconductor structure after forming the second intrinsic region in an embodiment of the present disclosure. In some embodiments, the second intrinsic region 14 may be formed according to the first pre-doped region 13. During the formation of the second intrinsic region 14 by ion implantation, this step may penetrate the entire first pre-doped region 13, and the free electrons caused by the implanted n-type ions substantially neutralize the holes of the first pre-doped region 13. In some possible embodiments, the concentration of doping element in the second intrinsic region 14 may be greater than the concentration of doping element in the first intrinsic region 12, as is the intrinsic region. In other embodiments, the first intrinsic region 12 may also include a greater amount of doping elements.

Fig. 12 illustrates a semiconductor structure after forming a pre-formed insulating layer in an embodiment of the present disclosure. Taking the structure shown in fig. 9 as an example, the prefabricated insulating layer 17 may be formed by a thermal oxygen growth process and annealing. The material of the preformed insulating layer 17 comprises an oxide, such as silicon oxide. The pre-insulating layer 17 includes a pre-insulating portion extending along the inner wall of the trench 11 and a surplus insulating portion covering the first pre-semiconductor layer 6.

Fig. 13 illustrates a semiconductor structure after forming a pre-formed gate in an embodiment of the present disclosure. Deposition and etching of polysilicon may be performed to form the pre-formed gate 18. The original trench 11 may be filled. The pre-formed gate 18 may also include other conductive materials.

Fig. 14 illustrates a semiconductor structure after an interlayer dielectric is formed in an embodiment of the present disclosure. Interlayer dielectric 19 may be formed by a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. The material of interlayer dielectric 19 may include silicon dioxide. Interlayer dielectric 19 surrounds pre-formed gate 18 in conjunction with pre-formed insulating layer 17.

Illustratively, the method for manufacturing a trench insulated gate field effect transistor provided by the present disclosure further includes the steps of: etching the interlayer dielectric and the surplus insulation part to obtain an insulated gate structure; forming a source metal layer in ohmic contact with the first prefabricated semiconductor layer 6; and forming a drain metal layer in ohmic contact with the pre-fabricated composite substrate 3. The drain metal layer is in ohmic contact with the pre-formed substrate 1, for example.

Fig. 15 illustrates a trench insulated gate field effect transistor in an embodiment of the disclosure, specifically a cell structure thereof in the XZ plane. Illustratively, the trench isolation gate field effect transistor 100 may be fabricated by the methods described above. The composite substrate 103 may be obtained from a prefabricated composite substrate 3, the protective layer 111 may be obtained from a prefabricated protective layer 15, and the body region 106 may be obtained from a prefabricated body region 9. In other embodiments, the trench isolation gate fet 100 may be fabricated by other methods, for example, the drift layer 102 may be formed by step-and-step epitaxy, and structures at different positions of the protection layer 111 may be formed during each step of epitaxy.

As shown in fig. 15, the trench type insulated gate field effect transistor 100 provided in the embodiment of the present disclosure includes a composite substrate 103, a channel layer 104, a first source contact region 107, an insulated gate structure 110, and a protective layer 111.

The composite substrate 103, the channel layer 104, and the first source contact region 107 may be sequentially stacked in the Z-axis direction. The composite substrate 103 and the first source contact region 107 have a first doping type, and the first source contact region 107 may have n+ type doping, and the composite substrate 103 includes, for example, the substrate 101 having n+ type doping and the drift layer 102 having n type doping. The channel layer 104 has a second doping type, such as a p-well region.

The insulated gate structure 110 extends through the first source contact region 107 and the channel layer 104 and may extend into the drift layer 102. The insulated gate structure 110 may include a gate 108 and an insulating layer 109 surrounding the gate 108.

The protective layer 111 is located between the insulated gate structure 110 and the composite substrate 103 in the stacking direction. Illustratively, the protective layer 111 includes an intrinsic region 112 and a first doped region 113 located on a side of the intrinsic region 112 facing away from the insulated gate structure 110. The first doped region 113 may have a second doping type, for example, p+ -type doping. The intrinsic region 112 has a doping concentration less than that of the first doped region 113 with respect to the hole concentration.

Fig. 16 shows a depletion region distribution in a natural state in a drift region of a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. As shown in fig. 16, the trench type insulated gate field effect transistor 100 according to the embodiment of the present disclosure has a third region C, a fourth region D, and a fifth region E in the drift layer 102. The third region C may be a first depletion region generated due to the channel layer 104. The fourth region D may be a second depletion region generated due to the first doped region 113. The fifth region E may have free carriers remaining therein. Due to the arrangement of the intrinsic region 112, the first doped region 113 is farther from the insulated gate structure 110 and the channel layer 104, and the fifth region E is wider, so that the current width of the trench insulated gate field effect transistor 100 is larger during operation, i.e. the current flow area during forward conduction is increased, thereby reducing the on-resistance.

In studying how to protect the bottom of the insulated gate structure, it was noted that after some kind of protection layer, such as a p+ doped protection layer, a parasitic JFET region was introduced in the trench insulated gate field effect transistor. Occasionally, a trench type insulated gate field effect transistor which not only ensures the protection effect on the bottom of an insulated gate structure, but also realizes smaller on-resistance is discovered.

The trench type insulated gate field effect transistor provided by the embodiment of the disclosure has better electrical performance and long-term reliability. By arranging the intrinsic region, the first doping type structure or the structure with the second doping type and lower doping concentration, the situation that the whole protection layer is provided with the second doping type with higher doping concentration can be avoided, the bottom of the insulated gate structure is well protected, and the on-resistance of the drift region and the whole device is smaller.

Illustratively, as shown in fig. 15, the trench insulated gate field effect transistor 100 further includes a source metal layer 114 and a drain metal layer 115, which may be in ohmic contact with the semiconductor structure, respectively.

Illustratively, the trench isolation gate field effect transistor 100 includes a body region 106, and the body region 106 may include a channel layer 104 and a second source contact region 105. The second source contact region 105 is located on a side of the first source contact region 107 facing away from the insulated gate structure 110. Along the Z-axis direction, the second source contact region 105 may be electrically connected to the source metal layer 114 and extend into the channel layer 104. The second source contact region 105 may have a second doping type, for example p+ -type doping.

Fig. 17 shows a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. Illustratively, the body region 106 of the trench isolation gate fet 100 of fig. 17 is a unitary structure, and the contact 1061 may have the same doping concentration as the channel layer 104. The protection layer 111 comprises an intrinsic region 112 and a first doped region 113 at a side of the intrinsic region 112 facing away from the insulated gate structure 110. In some embodiments, the first doped region 113 may have a graded concentration, and the doping concentration may be higher at locations where the first doped region 113 is farther from the insulated gate structure 110.

Fig. 18 illustrates a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. Illustratively, in the trench-type insulated gate field effect transistor 100, the protective layer 111 includes a second doped region 116 near the insulated gate structure 110 and a first doped region 113 far from the insulated gate structure 110. The second doped region 116 may have a first doping type. Illustratively, the doping concentration of the second doped region 116 may be comparable to the doping concentration of the drift layer 102. Illustratively, the doping concentration of the second doped region 116 may be greater than the doping concentration of the drift layer 102. The trench-type insulated gate field effect transistor 100 has lower on-resistance and better conductive performance.

Fig. 19 shows a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. Illustratively, the body region 106 of the trench isolation gate fet 100 of fig. 19 is a unitary structure, and the contact 1061 may have the same doping concentration as the channel layer 104. The protective layer 111 comprises a second doped region 116 and a first doped region 113 located on a side of the second doped region 116 facing away from the insulated gate structure 110. The trench-type insulated gate field effect transistor 100 has low on-resistance and good conductivity.

Fig. 20 shows a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. Illustratively, in the trench type insulated gate field effect transistor 100 shown in fig. 20, the protection layer 111 includes a first doped region 113. The doping concentration of the first doping region 113 may be graded along the Z-axis, with higher doping concentrations at locations farther from the insulated gate structure 110. Illustratively, the first doped region 113 may have a first location and a second location remote from the insulated gate structure 110 relative to the first location, the doping concentration at the first location being less than the doping concentration at the second location. The body region 106 includes the channel layer 104 and the second source contact region 105. The trench type insulated gate field effect transistor 100 has low on-resistance and good long-term reliability, and the bottom of the insulated gate structure 110 is well protected.

Fig. 21 shows a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. Illustratively, in the trench type insulated gate field effect transistor 100 shown in fig. 21, the protection layer 111 includes a first doped region 113. The first doped region 113 may have a graded doping concentration, with the doping concentration being higher at a location further from the insulated gate structure 110. Illustratively, the first doped region 113 may have a first location and a second location remote from the insulated gate structure 110 relative to the first location, the doping concentration at the first location being less than the doping concentration at the second location. Illustratively, the body region 106 is a unitary structure and the contact 1061 may have the same doping concentration as the channel layer 104. The trench type insulated gate field effect transistor 100 has a simple structure and is easy to manufacture.

In summary, the protection layer 111 may have a first location and a second location remote from the insulated gate structure 110 with respect to the first location, where the doping type is a second doping type, and the doping concentration at the first location is smaller than the doping concentration at the second location. The doping type at the first location is illustratively an intrinsic type or a first doping type.

Fig. 22 shows a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. In some embodiments, the trench type insulated gate field effect transistor 100 includes a composite substrate 103, a channel layer 104, and a first source contact region 107 stacked in sequence, and further includes an insulated gate structure 110 and an intrinsic region 112 located at a bottom side of the insulated gate structure 110. Along the Z-axis, the intrinsic region 112 is located between the composite substrate 103 and the insulated gate structure 110. The trench isolation gate fet 100 may be fabricated by the methods described above and the intrinsic region 112 may be obtained based on either the first intrinsic region 12 or the second intrinsic region 14.

The concentration profile of the doping element of the intrinsic region 112 may be relatively uniform. The intrinsic region 112 has a free electron concentration approximately equal to a hole concentration and may exhibit insulating properties. The intrinsic region 112 may protect the bottom of the insulated gate structure 110 so that the trench insulated gate field effect transistor 100 has long-term reliability. Meanwhile, the intrinsic region 112 hardly exerts a depletion effect on the drift layer 102, so that the flow area of the drift layer 102 is large. The trench isolation gate fet 100 has a low on-resistance.

Illustratively, the body region 106 includes a channel layer 104 and a second source contact region 105.

Fig. 23 shows a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. Illustratively, the body region 106 of the trench isolation gate fet 100 of fig. 23 is a unitary structure, and the contact 1061 may have the same doping concentration as the channel layer 104. The trench type insulated gate field effect transistor 100 has a simple structure and is easy to manufacture.

Fig. 24 shows a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. The drift layer 102 of the trench isolation gate field effect transistor 100 may be formed by segment epitaxy, and the intrinsic region 112 may be formed in the middle of the segment epitaxy process. Illustratively, the intrinsic region 112 is wider than the insulated gate structure 110 in the X-axis direction perpendicular to the Z-axis direction. In other words, the projection of the intrinsic region 112 along the Z-axis direction covers the projection of the insulated gate structure 110. Illustratively, the body region 106 includes a channel layer 104 and a second source contact region 105.

Fig. 25 illustrates a trench insulated gate field effect transistor provided by an embodiment of the present disclosure. In the trench-type insulated gate field effect transistor 100, the projection of the intrinsic region 112 along the Z-axis direction covers the projection of the insulated gate structure 110. Body region 106 is a unitary structure. The trench type insulated gate field effect transistor 100 has a simple structure and good protection effect on the insulated gate structure 110.

Fig. 26 shows an electronic device provided by an embodiment of the present disclosure. The disclosed embodiments provide an electronic device 300, the electronic device 300 comprising a trench insulated gate field effect transistor 100 and a circuit 200. The trench isolation gate fet 100 may be provided by the various embodiments described above.

The circuit 200 is electrically connected to the trench isolation gate fet 100, and may be electrically connected to the source metal layer 114, the drain metal layer 115, and the gate 108, for example. The circuit 200 may include metal interconnects or contacts and the material may include copper.

The electronic device provided by the embodiment of the disclosure has long-term reliability and lower circuit loss. The electronic device is applicable to high-voltage use environments.

The technical features of the embodiments disclosed above may be combined in any way, and for brevity, all of the possible combinations of the technical features of the embodiments described above are not described, however, they should be considered as the scope of the description provided in this specification as long as there is no contradiction between the combinations of the technical features.

In the embodiments disclosed above, the order of execution of the steps is not limited, and may be performed in parallel, or performed in a different order, unless explicitly stated and defined otherwise. The sub-steps of the steps may also be performed in an interleaved manner. Various forms of procedures described above may be used, and steps may be reordered, added, or deleted as long as the desired results of the technical solutions provided by the embodiments of the present disclosure are achieved, which are not limited herein.

The above disclosed examples represent only a few embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the inventive concept, which falls within the scope of the invention as claimed. The scope of the invention should, therefore, be determined with reference to the appended claims.

Claims (10)

1. A method for fabricating a trench insulated gate field effect transistor, comprising:

forming a trench, wherein the trench penetrates a first prefabricated semiconductor layer and a second prefabricated semiconductor layer and extends into a prefabricated composite substrate, the first prefabricated semiconductor layer and the prefabricated composite substrate having a first doping type, and the second prefabricated semiconductor layer having a second doping type;

forming an intrinsic region at the bottom side of the trench and extending into the pre-fabricated composite substrate; and

and forming an insulated gate structure, wherein the insulated gate structure is filled in the groove.

2. The method for manufacturing a trench isolation gate field effect transistor of claim 1, wherein the method comprises: and forming a first prefabricated doping region according to the intrinsic region, wherein the first prefabricated doping region extends into the prefabricated composite substrate and has the second doping type, the first prefabricated doping region has a first position and a second position which is far away from the groove relative to the first position, and the doping concentration at the second position is larger than that at the first position.

3. The method for manufacturing a trench isolation gate field effect transistor of claim 1, further comprising: forming a first pre-doped region extending into the pre-fabricated composite substrate, the first pre-doped region being located at a bottom side of the trench and having the second doping type;

the step of forming the intrinsic region includes: an intrinsic region is formed extending through at least a portion of the first pre-doped region.

4. The method for manufacturing a trench isolation gate field effect transistor as claimed in claim 3, further comprising: and forming a second prefabricated doping region according to the intrinsic region, wherein the second prefabricated doping region has the first doping type.

5. The method for fabricating a trench isolation gate field effect transistor as claimed in claim 1, wherein the intrinsic region is formed by an ion implantation process.

6. The method for manufacturing a trench isolation gate field effect transistor of claim 1, further comprising:

forming a source metal layer in ohmic contact with the first prefabricated semiconductor layer; and

and forming a drain metal layer in ohmic contact with the prefabricated composite substrate.

7. The trench type insulated gate field effect transistor is characterized by comprising:

the semiconductor device comprises a composite substrate, a channel layer and a first source contact region which are stacked in sequence, wherein the composite substrate and the first source contact region are provided with a first doping type, and the channel layer is provided with a second doping type;

an insulated gate structure penetrating the first source contact region and the channel layer; and

the protective layer is positioned between the insulated gate structure and the composite substrate along the stacking direction and is provided with a first position and a second position which is far away from the insulated gate structure relative to the first position, the doping type at the second position and the doping type at the first position are both the second doping type, and the doping concentration at the second position is larger than that at the first position.

8. The trench type insulated gate field effect transistor is characterized by comprising:

the semiconductor device comprises a composite substrate, a channel layer and a first source contact region which are stacked in sequence, wherein the composite substrate and the first source contact region are provided with a first doping type, and the channel layer is provided with a second doping type;

an insulated gate structure penetrating the first source contact region and the channel layer; and

the protective layer is positioned between the insulated gate structure and the composite substrate along the stacking direction, and is provided with a first position and a second position which is far away from the insulated gate structure relative to the first position, the doping type at the second position is the second doping type, and the doping type at the first position is an intrinsic type or the first doping type.

9. The trench type insulated gate field effect transistor is characterized by comprising:

the semiconductor device comprises a composite substrate, a channel layer and a first source contact region which are stacked in sequence, wherein the composite substrate and the first source contact region are provided with a first doping type, and the channel layer is provided with a second doping type;

an insulated gate structure penetrating the first source contact region and the channel layer; and

and the intrinsic region is positioned between the insulated gate structure and the composite substrate along the stacking direction.

10. An electronic device, comprising:

a trench insulated gate field effect transistor as claimed in any one of claims 7 to 9; and

And the circuit is electrically connected with the trench type insulated gate field effect transistor.

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