CN115548078A - Display panel and display device - Google Patents

Abstract

The application discloses display panel and display device relates to and shows technical field. The display panel has a first control line electrically connected to a first gate of the first transistor in a first overlap region where the first gate overlaps at least partially, and a second control line electrically connected to a second gate of the second transistor in a second overlap region where the second gate overlaps at least partially. Therefore, the control over the first transistor and the second transistor can be achieved, the situation that the first control line and the second control line occupy too much layout space in the second direction can be avoided, and the narrow frame of the display panel is convenient to achieve.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

Organic Light Emitting Diode (OLED) display panels are widely used due to their characteristics of self-luminescence, low driving voltage, fast response, and the like.

In the related art, a plurality of testing links are usually set in the production process of the display panel to ensure the quality of the display panel and improve the production efficiency. At present, a lighting test circuit may be designed in a peripheral area of the display panel, and the lighting test circuit may be used for performing a lighting test on the display panel to check a display failure of the display panel.

However, since the lighting test circuit occupies a large space in the peripheral area, the screen occupation ratio of the display panel is low, which affects the reduction of the frame width of the display panel.

Disclosure of Invention

The application provides a display panel and display device, can solve among the correlation technique display panel's screen and account for than lower, influence display panel's narrow frame's problem. The technical scheme is as follows:

in one aspect, a display panel having a display area and a peripheral area surrounding the display area is provided, including: the test circuit comprises a substrate base plate, a plurality of sub-pixels and a plurality of test circuit groups, wherein the sub-pixels are positioned on one side of the substrate base plate; the plurality of sub-pixels are positioned in the display area; the plurality of test circuit groups are positioned in the peripheral area and are distributed along the extending direction of the boundary of the display area; the set of test circuits includes at least one first test circuit, each of the first test circuits including:

a first transistor including a first gate;

the first control line extends along a first direction, an orthographic projection of the first control line on the substrate base plate and an orthographic projection of the first grid electrode on the substrate base plate are provided with a first overlapping area formed by at least partially overlapping, the first control line is electrically connected with the first grid electrode in the first overlapping area, the first control line is used for providing a first control signal for the first grid electrode, and the first transistor is turned on or turned off under the control of the first control signal provided by the first control line;

a second transistor including a second gate;

and the second control line extends along the first direction, an orthographic projection of the second control line on the substrate and an orthographic projection of the second grid electrode on the substrate have a second overlapping region formed by at least partially overlapping, the second control line is electrically connected with the second grid electrode in the second overlapping region, the second control line is used for providing a second control signal for the second grid electrode, and the second transistor is turned on or turned off under the control of the second control signal provided by the second control line.

Optionally, the display panel includes: the active layer, the first insulating layer, the first gate layer, the second insulating layer, the second gate layer, the third insulating layer, the first source drain layer, the fourth insulating layer and the second source drain layer are sequentially stacked on the substrate base plate; the active layer includes an active pattern; the first gate layer comprises at least a first gate pattern and a second gate pattern arranged along the second direction, the overlapped part of the first gate pattern and the active pattern forms the first gate, and the overlapped part of the second gate pattern and the active pattern forms the second gate;

the first control line and the second control line are positioned on the first source drain layer, the first control line and the first grid pattern are electrically connected through the second insulating layer and a first through hole in the third insulating layer, and the second control line and the second grid pattern are electrically connected through the second insulating layer and a second through hole in the third insulating layer.

Optionally, each of the first test circuits further includes: a first signal input line, a second signal input line and a first signal output line; the first transistor further comprises a first source and a first drain, and the second transistor further comprises a second source and a second drain;

the first signal input line and the second signal input line both extend in the first direction, the first signal input line being electrically connected to the first source or the second source for providing a first input signal to the first source and the second source, the second signal input line being electrically connected to the first source or the second source for providing a second input signal to the second source;

the first signal output line extends in a second direction intersecting the first direction, is electrically connected to the first drain and the second drain, and is further connected to the plurality of subpixels, and is configured to transmit an input signal received from the first drain to the plurality of subpixels, in a case where the first control line controls the first transistor to be turned on and the second control line controls the second transistor to be turned off, and to transmit an input signal received from the second drain to the plurality of subpixels, in a case where the first control line controls the first transistor to be turned off and the second control line controls the second transistor (M2) to be turned on.

Optionally, the first signal input line and the second signal input line are located in the second source-drain layer; the first signal output line is positioned on the second gate layer; the first source drain layer at least comprises a first source drain pattern, a second source drain pattern and a third source drain pattern which are arranged along the second direction; the first control line is positioned between the first source drain pattern and the second source drain pattern, and the second control line is positioned between the second source drain pattern and the third source drain pattern;

the orthographic projection of the first source-drain pattern on the substrate base plate is at least partially overlapped with the orthographic projection of the first signal input line on the substrate base plate, the first source-drain pattern is electrically connected with the first signal input line through a third through hole in the fourth insulating layer, and the first source-drain pattern is a first source electrode of the first transistor;

the orthographic projection of the second source-drain pattern on the substrate base plate is at least partially overlapped with the orthographic projection of the first signal output line on the substrate base plate, the second source-drain pattern is electrically connected with the first signal output line through a fourth through hole in the third insulating layer, and the second source-drain pattern is a first drain electrode of the first transistor and a second drain electrode of the second transistor;

an orthographic projection of the third source drain pattern on the substrate base plate is at least partially overlapped with an orthographic projection of the second signal input line on the substrate base plate, the third source drain pattern and the second signal input line are electrically connected through a fifth via hole in the fourth insulating layer, and the third source drain pattern is a second source electrode of the second transistor.

Optionally, an orthographic projection of the first via hole on the substrate base plate and an orthographic projection of the second via hole on the substrate base plate are both located within an orthographic projection of the active pattern on the substrate base plate;

the orthographic projection of the first gate pattern on the substrate base plate covers the orthographic projection of the first via hole on the substrate base plate, and the orthographic projection of the second gate pattern on the substrate base plate covers the orthographic projection of the second via hole on the substrate base plate.

Optionally, an orthographic projection of the first via hole on the substrate base plate and an orthographic projection of the second via hole on the substrate base plate are not overlapped with an orthographic projection of the active pattern on the substrate base plate.

Optionally, the second insulating layer and the third insulating layer at least include two first vias and two second vias; the active pattern comprises a first part and two second parts positioned on two sides of the first part, wherein the orthographic projection of the first part on the substrate is overlapped with the orthographic projection of the first grid pattern on the substrate and the orthographic projection of the second grid pattern on the substrate, one orthographic projection of one second part on the substrate is overlapped with the orthographic projection of the first source-drain pattern on the substrate, and the other orthographic projection of the other second part on the substrate is overlapped with the orthographic projection of the second source-drain pattern on the substrate;

at least two first via holes and the first portion are arranged along the first direction, at least two first via holes are positioned on two sides of the first portion, the length of the first gate pattern along the first direction is greater than that of the first portion along the first direction, the first gate pattern comprises a first region and a second region which are not overlapped with the first portion and are arranged along the first direction, and the first control line and the first gate pattern are electrically connected through at least one first via hole in the first region and the second region respectively;

the at least two second via holes and the first portion are arranged along the first direction, the at least two second via holes are located on two sides of the first portion, the length of the second gate pattern along the first direction is larger than that of the first portion along the first direction, the second gate pattern comprises a third area and a fourth area which are not overlapped with the first portion and are arranged along the first direction, and the second control line and the second gate pattern are electrically connected through at least one second via hole in the third area and the fourth area respectively.

Optionally, the second insulating layer and the third insulating layer at least include two first vias and two second vias; the active pattern comprises a first part and two second parts positioned on two sides of the first part, wherein an orthographic projection of the first part on the substrate is overlapped with an orthographic projection of the first gate pattern on the substrate and an orthographic projection of the second gate pattern on the substrate, one orthographic projection of the second part on the substrate is overlapped with the first source part of the first transistor, and the other orthographic projection of the second part on the substrate is overlapped with the second source part of the second transistor;

at least two first via holes and the first portion are arranged along the first direction and are positioned on one side of the first portion, the length of the first gate pattern along the first direction is greater than that of the first portion along the first direction, the first gate pattern comprises a fifth area which is not overlapped with the first portion, and the first control line and the first gate pattern are electrically connected through at least two first via holes in the fifth area;

the at least two second via holes and the first portion are arranged along the first direction and are located on one side of the first portion, the length of the second gate pattern along the first direction is greater than that of the first portion along the first direction, the second gate pattern comprises a sixth area which is not overlapped with the first portion, and the second control line and the second gate pattern are electrically connected in the sixth area through the at least two second via holes.

Optionally, at least two of the first vias are arranged along the first direction, or at least two of the first vias are arranged along the second direction;

at least two of the second via holes are arranged along the first direction, or at least two of the second via holes are arranged along the second direction.

Optionally, a length of the first portion in the first direction is less than or equal to a length of the second portion in the first direction.

Optionally, for each of the first source-drain pattern, the second source-drain pattern, and the third source-drain pattern, an orthographic projection of the source-drain pattern on the substrate base plate is at least partially overlapped with an orthographic projection of the active pattern on the substrate base plate, and the source-drain pattern and the active pattern are electrically connected through the first insulating layer, the second insulating layer, and a sixth via hole in the third insulating layer.

Optionally, the test circuit group includes two first test circuits arranged along the second direction; two of the first test circuits share a first signal input line, or two of the first test circuits share a second signal input line.

Optionally, the first signal output line in the first test circuit and the first signal output line in the second test circuit are respectively located on two sides of the transistors included in the two first test circuits.

Optionally, the display panel further includes a plurality of second test circuits, where the plurality of second test circuits are located in the peripheral region and arranged along an extending direction of a boundary of the display region; each of the second test circuits includes a second signal output line; the plurality of sub-pixels form a plurality of first pixel columns and a plurality of second pixel columns, each first pixel column comprises a plurality of first color sub-pixels and a plurality of second color sub-pixels, and each second pixel column comprises a plurality of third color sub-pixels;

the first signal output line of each of the first test circuits is connected to the plurality of first color sub-pixels and the plurality of second color sub-pixels of one of the first pixel columns, and the second signal output line of each of the second test circuits is connected to the plurality of third color sub-pixels of one of the second pixel columns.

In another aspect, there is provided a display device including: a power supply assembly and a display panel as described in the above aspects;

the power supply assembly is used for supplying power to the display panel.

The beneficial effect that technical scheme that this application provided brought includes at least:

the application provides a display panel and a display device, wherein a first control line in the display panel is electrically connected with a first grid electrode of a first transistor in a first overlapping area which is at least partially overlapped, and a second control line is electrically connected with a second grid electrode of a second transistor in a second overlapping area which is at least partially overlapped. Therefore, the control over the first transistor and the second transistor can be achieved, the layout space of the second direction occupied by the first control line and the second control line can be avoided too much, and the narrow frame of the display panel is convenient to achieve.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a partial schematic diagram of a test circuit in the related art;

fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a first test circuit according to an embodiment of the present disclosure;

FIG. 4 is a cross-sectional view along direction AA of the first test circuit shown in FIG. 3;

FIG. 5 is a schematic view of an electron microscope provided in an embodiment of the present application;

FIG. 6 is a cross-sectional view of the FIG. 5;

FIG. 7 is a schematic view of another electron microscope provided in the embodiments of the present application;

FIG. 8 is a cross-sectional view of the device shown in FIG. 7;

FIG. 9 is a partial schematic diagram of a test circuit group according to an embodiment of the present application;

FIG. 10 is a partial schematic diagram of another test circuit set provided in the embodiments of the present application;

FIG. 11 is a partial schematic diagram of another test circuit group provided in the embodiments of the present application;

FIG. 12 is a partial schematic diagram of another test circuit set provided in an embodiment of the present application;

FIG. 13 is a partial schematic diagram of another testing circuit set according to an embodiment of the present application;

FIG. 14 is an equivalent circuit diagram of a first test circuit and a second test circuit provided in the embodiments of the present application;

FIG. 15 is a timing diagram of signals provided by an embodiment of the present application;

fig. 16 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

An Organic Light Emitting Diode (OLED) belongs to a new current type semiconductor light emitting device. The organic light emitting diode realizes the display function by controlling the injection of current carriers and simultaneously compositely exciting the light emission of organic materials. The driving method of the organic light emitting diode can be divided into active driving and passive driving. Accordingly, the display panel may be an active-matrix display panel (AMOLED) or a passive-matrix display Panel (PMOLED). Compare with passive drive, active drive can be for every sub-pixel in the display panel is equipped with Thin Film Transistor (TFT) and charge storage capacitance to improve load drive ability, easily realize high resolution and hi-lite, have advantages such as work efficiency height and low power dissipation. The AMOLED display panel is convenient to integrate in the display panel, is easier to improve the circuit integration level to realize large-area display, and is an ideal device of a low-power-consumption large-size display device.

The AMOLED display panel still has a significantly short panel in terms of structure. For example, peripheral circuits of the AMOLED display panel need to occupy a large space in the layout, so the frame width of the display panel is large, which affects the narrow frame of the AMOLED display product.

In the related art, the display panel has a display area and a peripheral area surrounding the display area. The peripheral region includes a fan-out bonding region located on one side of the display region, and the lighting test circuit (celltest) is located on a side of the bonding region away from the display region. Since the lighting test circuit has a limited design space in the pixel row direction of the display panel, it is necessary to design two rows of lighting test circuits. Referring to fig. 1, a related art will be briefly described by taking two rows of lighting test circuits as an example. The two-row lighting test circuit includes two first control lines (CTSW 21 and CTSW 22), one second control line (CTSW 3), two first signal input lines (CTDR 1 and CTDR 2), and two second signal input lines (CTDB 1 and CTDB 2).

The pixel driving circuit comprises a first control line (CTSW 21), a second signal input line (CTDB 1), a first signal input line (CTDR 1), a second control line (CTSW 3), a second signal input line (CTDB 2), a first signal input line (CTDR 2) and a first control line (CTSW 22), wherein the first control line (CTSW 21), the second signal input line (CTDB 1), the second signal input line (CTDB 3), the first signal input line (CTDB 2) and the first control line (CTSW 22) extend along the direction of a pixel row and are sequentially arranged along the direction of a pixel column. Also, each lighting test circuit includes one first transistor and one second transistor. The first transistor and the second transistor of the first lighting test circuit are located between the first control line (CTSW 21) and the second control line (CTSW 3), and the first transistor and the second transistor of the second lighting test circuit are located between the second control line (CTSW 3) and the first control line (CTSW 22).

The first transistor includes a first gate, a first source and a first drain, and the second transistor includes a second gate, a second source and a second drain. The first control line (CTSW 21) is transitionally connected to the first gate of the first transistor of one lighting test circuit through the vertical trace transitionally connected to the first gate layer, and the first control line (CTSW 22) is transitionally connected to the first gate of the first transistor of the other lighting test circuit through the vertical trace transitionally connected to the first gate layer. Two sides of the second control line (CTSW 3) are transitionally connected to the second grid of the second transistor of the two lighting test circuits through vertical routing transitionally connected to the first grid layer.

The first signal input lines (CTDR 1 and CTDR 2) are used for writing data signals of red subpixels, and the second signal input lines (CTDB 1 and CTDB 2) are used for writing data signals of blue subpixels, and are usually dc signals with fixed voltage values. The first control lines (CTSW 21 and CTSW 22) are used to control the on or off of the first transistors. The second control line (CTSW 3) is used to control the second transistor to be turned on or off.

The first transistor in each lighting test circuit may be turned on or off under the control of a control signal supplied from the first control line (CTSW 21 or CTSW 22), and the second transistor in each lighting test circuit may be turned on or off under the control of a control signal supplied from the second control line (CTSW 3). The lighting test circuit further includes a first signal output line extending in the pixel column direction. The first signal input line (CTDR 1 or CTDR 2) transmits a first input signal to the first signal output line through the first transistor with the first transistor turned on and the second transistor turned off. The second signal input lines (CTDB 1 and CTDB 2) transmit a second input signal to the first signal output line through the second transistor in a case where the first transistor is turned off and the second transistor is turned on. Thereby realizing a lighting test by alternately turning on the first transistor and the second transistor.

However, such a scheme causes the traces to occupy more layout space in the pixel column direction, which results in a wider width of the peripheral region and makes it difficult to realize a narrow frame of the display panel.

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present application. Referring to fig. 2, the display panel 10 may include: the pixel circuit includes a substrate 101, a plurality of sub-pixels 102 and a plurality of test circuit groups 103 on one side of the substrate 101. The display panel 10 may have a display area 10a, and a peripheral area 10b surrounding the display area 10a. The plurality of sub-pixels 102 are located in the display area 10a, and the plurality of test circuit groups 103 are located in the peripheral area 10b and arranged along the extending direction of the boundary of the display area 10a.

Fig. 3 is a schematic structural diagram of a test circuit group according to an embodiment of the present disclosure. Referring to fig. 3, the test circuit group 103 includes at least one first test circuit 1031. In fig. 3, one test circuit group 103 is shown, and the test circuit group 103 includes one first test circuit 1031. Referring to fig. 3, each of the first test circuits 1031 may include: a first transistor M1, a first control line 10311, a second transistor M2, and a second control line 10312.

The first transistor M1 includes a first gate, and the second transistor M2 includes a second gate. The first control line 10311 and the second control line 10312 both extend in the first direction X.

In the embodiment of the present application, an orthogonal projection of the first control line 10311 on the substrate base plate 101 and an orthogonal projection of the first gate of the first transistor M1 on the substrate base plate 101 have a first overlapping region which is at least partially overlapped, and the first control line 10311 and the first gate are electrically connected in the first overlapping region. The first control line 10311 is used to provide a first control signal to the first gate. The first transistor M1 is turned on or off under the control of a first control signal provided by a first control line 10311 for the first gate.

An orthogonal projection of the second control line 10312 on the substrate base 101 and an orthogonal projection of the second gate of the second transistor M2 on the substrate base 101 have a second overlapping region in which at least a part of them overlap each other, and the second control line 10312 and the second gate are electrically connected in the second overlapping region. The second control line 10312 is used to provide a second control signal to the second gate. The second transistor M2 is turned on or off under the control of a second control signal provided to the second gate by a second control line 10312.

In summary, embodiments of the present application provide a display panel in which a first control line is electrically connected to a first gate electrode of a first transistor in a first overlap region that at least partially overlaps, and a second control line is electrically connected to a second gate electrode of a second transistor in a second overlap region that at least partially overlaps. Therefore, the control over the first transistor and the second transistor can be achieved, the situation that the first control line and the second control line occupy too much layout space in the second direction can be avoided, and the narrow frame of the display panel is convenient to achieve.

Alternatively, by the design of the embodiment of the present application, a size of about 23 μm (micrometers) to 28 μm in the display panel along the second direction Y can be saved.

In an embodiment of the present application, referring to fig. 3, the first test circuit 1031 further includes a first signal input line 10313, a second signal input line 10314 and a first signal output line 10315. The first signal input line 10313, the second signal input line 10314, and the first signal output line 10315 all extend in the first direction X. The first signal input line 10313, the first control line 10313, the second control line 10316 and the second signal input line 10314 are sequentially arranged along the second direction Y. The second direction Y intersects the first direction X, for example, the first direction X is a pixel row direction of the display panel, and the second direction Y is a pixel column direction of the display panel. In addition, the first transistor M1 may further include a first source and a first drain, and the second transistor M2 may further include a second source and a second drain.

The first signal input line 10313 is electrically connected to a first source of the first transistor M1 or a second source of the second transistor M2, and is configured to provide a first input signal to the first source or the second source. The second signal input line 10314 is electrically connected to the first source of the first transistor M1 or the second source of the second transistor M2, and is used for providing a second input signal to the first source or the second source.

The first signal output line 10315 is electrically connected to the first and second drains of the first transistor M1, and the first signal output line 10315 is also connected to the plurality of sub-pixels 102 located in the display region 10a. In a case where the first control line 10311 controls the first transistor M1 to be turned on and the second control line 10312 controls the second transistor M2 to be turned off, the first signal output line 10315 is used to transmit an input signal received from the first drain to the plurality of subpixels 102. The first signal output line 10315 is also used to transmit an input signal received from the second drain to the plurality of sub-pixels 102 in a case where the first control line 10311 controls the first transistor M1 to be turned off and the second control line 10312 controls the second transistor M2 to be turned on.

Referring to fig. 4, the display panel 10 may include: an active layer (poly) a1, a first insulating layer a2, a first Gate layer (Gate 1) a3, a second insulating layer a4, a second Gate layer (Gate 2) a5, a third insulating layer a6, a first source/drain layer (SD 1) a7, a fourth insulating layer a8, and a second source/drain layer (SD 2) a9 are sequentially stacked on the substrate base 101. Alternatively, the first insulating layer a2 may be a first gate insulating layer (GI). The second insulating layer a4 may be a second gate insulating layer. The third insulating layer a6 may be an (inter level dielectric, ILD). The fourth insulating layer a8 may include a passivation layer (PVX) a81 and a Planarization Layer (PLN) a82.

Wherein the active layer a1 includes an active pattern a11. The first gate layer a3 includes at least a first gate pattern a31 and a second gate pattern a32 arranged in the second direction Y. A portion where the first gate pattern a31 and the active pattern a11 overlap constitutes a first gate of the first transistor M1, and a portion where the second gate pattern a32 and the active pattern a11 overlap constitutes a second gate of the second transistor M2. The first source-drain layer a7 includes at least a first source-drain pattern a71, a second source-drain pattern a72, and a third source-drain pattern a73 arranged in the second direction Y.

In the embodiment of the present application, the first control line 10311 and the second control line 10312 are both located on the first source drain layer a7. The first control line 10311, the second control line 10312, the first source-drain pattern a71, the second source-drain pattern a72, and the third source-drain pattern a73 may be made of the same material and by the same patterning process. Wherein the first control line 10311 is located between the first source-drain pattern a71 and the second source-drain pattern a72, and the second control line 10312 is located between the second source-drain pattern a72 and the third source-drain pattern a73. In addition, the first signal output line 10315 is located on the second gate layer a5.

An insulating film layer between the first control line 10311 and the first gate pattern a31 includes a second insulating layer a4 and a third insulating layer a6, and the second insulating layer a4 and the third insulating layer a6 may have a first via hole therein, through which the first control line 10311 and the first gate pattern a31 may be electrically connected. Similarly, the insulating film layer between the second control line 10312 and the second gate pattern a32 also includes a second insulating layer a4 and a third insulating layer a6, the second insulating layer a4 and the third insulating layer a6 may have a second via hole therein, and the second control line 10312 and the second gate pattern a32 may be electrically connected through the second via hole.

An orthographic projection of the first source-drain pattern a71 on the substrate base plate 101 at least partially overlaps with an orthographic projection of the first signal input line 10313 on the substrate base plate 101, and the first source-drain pattern a71 and the first signal input line 10313 are electrically connected through a third via hole in the fourth insulating layer a 8. The first source-drain pattern a71 may be a first source of the first transistor M1.

An orthographic projection of the second source-drain pattern a72 on the substrate base plate 101 is at least partially overlapped with an orthographic projection of the first signal output line 10315 on the substrate base plate 101, the second source-drain pattern a72 is electrically connected with the first signal output line 10315 through a fourth via hole in the third insulating layer a6, and the second source-drain pattern a72 is a first drain electrode of the first transistor M1 and a second drain electrode of the second transistor M2. That is, the first drain of the first transistor M1 and the second drain of the second transistor M2 are common.

An orthogonal projection of the third source drain pattern a73 on the substrate base plate 101 at least partially overlaps an orthogonal projection of the second signal input line 10314 on the substrate base plate 101, and the third source drain pattern a73 and the second signal input line 10314 are electrically connected through a fifth via hole in the fourth insulation layer a 8. The third source drain pattern a73 may be a second source of the first transistor M1.

In addition, in the embodiment of the present application, for each of the first source-drain pattern a71, the second source-drain pattern a72, and the third source-drain pattern a73, an orthographic projection of the source-drain pattern on the substrate base 101 at least partially overlaps an orthographic projection of the active pattern a11 on the substrate base 101. The source-drain pattern and the active pattern a11 are electrically connected by a sixth via hole in the first insulating layer a2, the second insulating layer a4, and the third insulating layer a 6.

As a first alternative implementation, referring to fig. 3 and 9, an orthographic projection of the first via hole on the substrate base 101 and an orthographic projection of the second via hole on the substrate base 101 are both located within an orthographic projection of the active pattern a11 on the substrate base 101. That is, a region where the first control line 10311 and the first gate pattern a31 are electrically connected, and a region where the second control line 10312 and the second gate pattern a32 are electrically connected are both located within an orthographic projection of the active pattern a11 on the substrate 101.

In this implementation, referring to fig. 5 to 8, if the size of the first via (or the second via) is too large and the boundary of the first gate pattern a31 (or the second gate pattern a 32) is exposed, the formed first control line 10311 (or the second control line 10312) may cover the sidewall of the first gate pattern a31 (or the second gate pattern a 32), the first control line 10311 (or the second control line 10312) may be shorted (Short) with the active pattern a11 due to a Short distance, and the first transistor M1 (or the second transistor M2) may fail.

Based on this, in order to avoid the transistor failure, the orthographic projection of the first gate pattern a31 on the substrate base 101 may cover the orthographic projection of the first via hole on the substrate base 101, and the orthographic projection of the second gate pattern a32 on the substrate base 101 covers the orthographic projection of the second via hole on the substrate base 101.

Optionally, the aperture of the first via and the second via ranges from 2 μm to 2.5 μm. In the original design, the length of the first gate pattern a31 along the second direction Y (i.e., the width of the first gate pattern a 31) and the length of the second gate pattern a32 along the second direction Y (i.e., the width of the second gate pattern a 32) range from about 3.2 μm to about 4.5 μm. In order to avoid the transistor failure, the width of the first gate pattern a31 and the width of the second gate pattern a32 may be in a range of 4.5 μm to 6.4 μm.

Without changing the width-to-length ratio of the channels of the first transistor M1 and the second transistor M2, since the width of the first gate pattern a31 and the width of the second gate pattern a32 are increased (equivalent to increasing the length of the channels of the first transistor M1 and the second transistor M2), it is necessary to appropriately increase the length of the active pattern a11 in the first direction X to increase the length of the overlapping region of the first gate pattern a31 and the active pattern a11 in the first direction X and the length of the overlapping region of the second gate pattern a32 and the active pattern a11 in the first direction X (equivalent to increasing the width of the channels of the first transistor M1 and the second transistor M2). Thus, the range of the length of the active pattern a11 in the first direction X may be changed from the original 15 μm to 17 μm to 18 μm to 20 μm. In addition, the length of the first gate pattern a31 in the first direction X (i.e., the length of the first gate pattern a 31) and the length of the second gate pattern a32 in the first direction X (i.e., the length of the second gate pattern a 32) may be changed from the original 21 μm to 24 μm to 26 μm to 30 μm.

As a second optional implementation, the second and third insulating layers a4 and a6 include at least two first vias and two second vias. The active pattern a11 includes one first portion a111 and two second portions a112 positioned at both sides of the first portion a 111. The orthographic projection of the first portion a111 on the base substrate 101 overlaps with the orthographic projection of the first gate pattern a31 on the base substrate 101 and the orthographic projection of the second gate pattern a32 on the base substrate 101. The orthographic projection of one second part a112 on the substrate base plate 101 is overlapped with the orthographic projection of the first source-drain pattern a71 on the substrate base plate 101, and the orthographic projection of the other second part a112 on the substrate base plate 101 is overlapped with the orthographic projection of the second source-drain pattern a72 on the substrate base plate 101.

In a first scheme, referring to fig. 10, at least two first vias and the first portion a111 are arranged along the first direction X, and the at least two first vias are located at two sides of the first portion a 111. The length of the first gate pattern a31 in the first direction X is greater than the length of the first portion a111 in the first direction X. The first gate pattern a31 includes a first region and a second region that are not overlapped with the first portion a111 and are arranged in the first direction X. The first control line 10311 and the first gate pattern a31 are electrically connected through at least one first via hole in the first region and the second region, respectively. The second and third insulating layers a4 and a6 of fig. 10 include two first vias.

Also, referring to fig. 10, at least two second vias are arranged with the first portion a111 along the first direction X, and the at least two second vias are located at both sides of the first portion a 111. The length of the second gate pattern a32 in the first direction X is greater than the length of the first portion a111 in the first direction X. The second gate pattern a32 includes third and fourth regions that are not overlapped with the first portion a111 and are arranged in the first direction X. The second control line 10312 and the second gate pattern a32 are electrically connected through at least one second via hole in the third region and the fourth region, respectively. The second and third insulating layers a4 and a6 of fig. 10 include two second vias.

In a second scheme, referring to fig. 11, at least two first vias and the first portion a111 are arranged along the first direction X, and the at least two first vias are located at one side of the first portion a 111. The length of the first gate pattern a31 in the first direction X is greater than the length of the first portion a111 in the first direction X. The first gate pattern a31 includes a fifth region (the fifth region may be located at the left or right side of the first portion a 111) that does not overlap with the first portion a 111. The first control line 10311 and the first gate pattern a31 are electrically connected through at least two first vias in the fifth region. The second and third insulating layers a4 and a6 in fig. 11 include two first vias.

Also, referring to fig. 11, at least two second vias are arranged along the first direction X with the first portion a111, and the at least two second vias are located at one side of the first portion a 111. The length of the second gate pattern a32 in the first direction X is greater than the length of the first portion a111 in the first direction X. The second gate pattern a32 includes a sixth region that is not overlapped with the first portion a111 (the sixth region may be located on the left or right side of the first portion a111, and the sixth region and the fifth region may be located on the same side of the first portion a111 or on both sides of the first portion a 111). The second control line 10312 and the second gate pattern a32 are electrically connected through at least two second vias in the sixth region. The second and third insulating layers a4 and a6 of fig. 11 include two second vias.

Referring to fig. 11 described above, two first vias may be arranged along the first direction X, and two second vias may be arranged along the first direction X. Of course, referring to fig. 12, two first vias may also be arranged along the second direction Y, and two second vias may also be arranged along the second direction Y. In addition, two first vias may be arranged along the first direction X, and two second vias may be arranged along the second direction Y. Or, the two first vias are arranged along the second direction Y, and the two second vias are arranged along the first direction X.

That is, in the embodiment of the present application, at least two first vias are arranged along the first direction X, or at least two first vias are arranged along the second direction Y. The at least two second via holes are arranged along the first direction X, or the at least two second via holes are arranged along the second direction Y.

In the embodiment of the present application, the length of the first portion a111 in the first direction X may be less than or equal to the length of the second portion a112 in the first direction X. Referring to fig. 9 to 12, the length of the first portion a111 in the first direction X is equal to the length of the second portion a112 in the first direction X. In this case, the length of the first gate pattern a31 and the length of the second gate pattern a32 along the first direction X need to be designed to be greater than the length of the second portion a112 along the first direction X. Of course, referring to fig. 13, the length of the first portion a111 in the first direction X is smaller than the length of the second portion a112 in the first direction X. In this case, the length of the first gate pattern a31 in the first direction X and the length of the second gate pattern a32 in the first direction X may be greater than or equal to the length of the second portion a112 in the first direction X. Alternatively, the length of the first portion a111 along the first direction X ranges from 15 μm to 17 μm. The length of the second portion a112 in the first direction X ranges from 18 μm to 20 μm.

In the second implementation manner, since the orthographic projection of the first via on the substrate base plate 101 and the orthographic projection of the second via on the substrate base plate 101 are not overlapped with the orthographic projection of the active pattern a11 on the substrate base plate 101, the electrical connection between the first control line 10311 and the first gate pattern a31 and the electrical connection between the second control line 10312 and the second gate pattern a32 do not affect the active pattern a11, and the performance of the first transistor M1 and the second transistor M2 is ensured.

In the embodiment of the present application, referring to fig. 9 to 13, the test circuit group 103 includes two first test circuits 1031 arranged in the second direction Y. The two first test circuits 1031 may share one first signal input line 10313, or the two first test circuits 1031 may share one second signal input line 10314.

If two first test circuits 1031 share one first signal input line 10313, the first signal input line 10313 may provide a first input signal for the sources of two transistors connected to the first signal input line 10312 among the two first test circuits 1031. If two first test circuits 1031 share one second signal input line 10314, the second signal input line 10314 may provide a second input signal for transistors of two of the two first test circuits 1031 connected to the second signal input line 10314.

As can be seen with reference to fig. 9 to 13, the first signal output lines 10315 in the first test circuits 1031, and the first signal output lines 10315 in the second first test circuits 1031 are respectively located at both sides of the transistors included in the two first test circuits 1031. Therefore, the pattern uniformity of the layout design can be improved.

In the embodiment of the present application, the display panel 10 may further include a plurality of second test circuits (not shown in the figure), and the plurality of second test circuits may be located in the peripheral region 10b and arranged along the extending direction of the boundary of the display region 10a. For example, the plurality of second test circuits may be located on a side of the test circuit group 103 away from the display area 10a.

Referring to fig. 9 to 13, each second test circuit 104 includes a second signal output line 1041, the second signal output line 1041 may extend along the second direction Y, and of course, the second signal output line 1041 may also be bent appropriately to suit the layout design. Of course, the second test circuit 104 may further include a third transistor M3 (the third transistor is shown in fig. 14 described below), a third signal input line, and a third control line (the third transistor, the third signal input line, and the third control line are not shown in fig. 9 to 13). The third transistor includes a third gate, a third source, and a third drain. The third control line is electrically connected to the third gate and is used for providing a third control signal for the third gate. The third transistor is turned on or off under the control of a third control signal provided by a third control line. The third signal input line is electrically connected to the third source for providing a third input signal to the third source. The second signal output line is electrically connected to the third drain, and is configured to transmit a third input signal received from the third drain to the plurality of sub-pixels 102 when the third control line controls the third transistor to be turned on.

In addition, referring to fig. 14, the plurality of sub-pixels 102 may constitute a plurality of first pixel columns 102a and a plurality of second pixel columns 102b. Each first pixel column 102a includes a plurality of first color sub-pixels and a plurality of second color sub-pixels. Each second pixel column 102b includes a plurality of third color sub-pixels. Alternatively, the first color sub-pixel may be a red (R) sub-pixel, the second color sub-pixel may be a blue (B) sub-pixel, and the third color sub-pixel may be a green (G) sub-pixel.

The first signal output line 10315 of each first test circuit 1031 is connected to the plurality of first color sub-pixels and the plurality of second color sub-pixels of one first pixel column 102 a. The second signal output line of each second test circuit is connected to a plurality of third color sub-pixels of one second pixel column 102b.

In fig. 14, CTSW1 is used to represent a third control signal provided by a third control line, CTSW2 is used to represent a first control signal provided by a first control line, and CTSW3 is used to represent a second control signal provided by a second control line. CTDG is used to represent a third input signal provided by a third signal input line, CTDR is used to represent a first input signal provided by a first signal input line, and CTDB is used to represent a second input signal provided by a second signal input line.

Fig. 15 is a timing diagram of signals provided by an embodiment of the present application. Referring to fig. 15, in a case where the display panel 10 displays a white screen, the potential of the first control signal CTSW2 supplied by the first control line 10311 and the potential of the second control signal CTSW3 supplied by the second control line 10312 are alternately the first potential L, and the first control signal CTSW2 and the second control signal CTSW3 may be ac signals. The potential of a third control signal CTSW1 provided by the third control line is the first potential L, and the third control signal CTSW1 is a dc signal. The first potential L may be an active potential, the second potential H may be an inactive potential, and the first potential L may be a low potential with respect to the second potential H.

In addition, the first input signal CTDR supplied from the first signal input line 10313, the second input signal CTDB supplied from the second signal input line 10314, and the third input signal CTDG supplied from the third signal input line are all fixed voltage signals. For example, the fixed voltage signal ranges from 0V (volts) to 8V. For example, if the fixed voltage signal received by the sub-pixel is 0V, the sub-pixel can emit light; if the fixed voltage signal received by the sub-pixel is 7V, the sub-pixel may not emit light.

In the process of lighting test of the display panel, the display picture of the display panel can be adjusted by controlling the size of the fixed voltage signal input by each signal input line, and then the test is realized.

Fig. 16 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure. As can be seen with reference to fig. 16, the display panel 10 may include a power driving circuit 105, a first power line 106 and a second power line 107. The power driving circuit 105 may be located in the peripheral region and on a side of the testing circuit group 103 away from the display region 10a. For example, the power supply driving circuit 105 may be located at a lower side of the display region 10a.

The power driving circuit 105 may be connected to a first power line 106 and a second power line 107, and the power driving circuit is configured to provide a first power signal (VSS signal) to the first power line 106, so that the first power line 106 provides the first power signal from the power driving circuit 105 to the cathodes of the plurality of sub-pixels 102. Also, the power driving circuit 105 may be further configured to provide a second power signal (VDD signal) to the second power line 107, such that the second power line 107 provides the second power signal from the power driving circuit 105 to the anodes of the plurality of sub-pixels 102.

For example, one first power line 106 is shown in fig. 16, and the first power line 106 may at least partially surround the display region 10a. Also, two second power supply lines 107 are shown in fig. 16 (one second power supply line 107 on each of the upper and lower sides).

Referring to fig. 16, the display panel 10 further includes a driving Integrated Circuit (IC) circuit 108. The driving integrated circuit 108 may be located on a side of the test circuit group 103 and the second test circuit 104 away from the display area 10a. The driver integrated circuit 108 may be used to provide the respective input signals and control signals to the first test circuit 1031 and the second test circuit 104. The peripheral region 10b of the substrate base 101 may include a fan-out binding region 101b1, and the first test circuit 1031 and the second test circuit 104 may be connected to the plurality of sub-pixels 102 in the display region 10a through the fan-out binding region 101b 1.

Referring to fig. 16, the display panel 10 may further include a gate driver on array (GOA) 109, a first reset (vinit) circuit 110 and a second reset circuit 111. The row driving circuit 109 may include a first sub driving circuit and a second sub driving circuit located at both sides of the display area 10a. The first reset circuit 110 may include a first sub-reset circuit and a second sub-reset circuit located at both sides of the display region 10a. The second reset circuit 111 may include a third sub-reset circuit and a fourth sub-reset circuit located at both sides of the display region 10a.

Optionally, the display panel 10 further includes a plurality of power connection lines 112 extending along the second direction. The power connection line 112 may be connected to the second power line 107 and a column of sub-pixels in the display area 10a. The power connection line 112 may transmit a second power signal provided by the second power line 107 to a column of sub-pixels.

In addition, the display panel 10 may further include a plurality of row driving signal lines 113, a plurality of first reset signal lines 114, and a plurality of second reset signal lines 115. Two ends of each row driving signal line 113 are respectively connected with the first sub-driving circuit and the second sub-driving circuit included in the row driving circuit 109, and each row driving signal line 113 is further connected with a row of sub-pixels in the display area 10a for providing a row driving signal for the row of sub-pixels. Two ends of each first reset signal line 114 are respectively connected to two first sub-reset circuits and a second sub-reset circuit included in the first reset circuit 110, and each first reset signal line 114 is further connected to a row of sub-pixels in the display area 10a, and is configured to provide a first reset signal to the row of sub-pixels. Two ends of each second reset signal line 115 are respectively connected to two third sub-reset circuits and four sub-reset circuits included in the second reset circuit 111, and each second reset signal line 115 is further connected to a row of sub-pixels in the display region 10a, and is configured to provide a second reset signal to the row of sub-pixels.

In summary, the embodiments of the present application provide a display panel in which a first control line is electrically connected to a first gate electrode of a first transistor in a first overlap region that at least partially overlaps, and a second control line is electrically connected to a second gate electrode of a second transistor in a second overlap region that at least partially overlaps. Therefore, the control over the first transistor and the second transistor can be achieved, the situation that the first control line and the second control line occupy too much layout space in the second direction can be avoided, and the narrow frame of the display panel is convenient to achieve.

Fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present application. Referring to fig. 17, the display device may include the power supply assembly 20 and the display panel 10 provided as the above embodiment. The power supply assembly 20 may be used to supply power to the display panel 10.

Optionally, the display device may be: any product or component having a display function, such as a Liquid Crystal Display (LCD), an organic light-emitting diode (OLED) display, electronic paper, a Low Temperature Polysilicon (LTPS) display, a Low Temperature Polysilicon (LTPO) display, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

Since the display device may have substantially the same technical effects as the display panel described in the previous embodiment, for the sake of brevity, the technical effects of the display device will not be described repeatedly herein.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (15)

1. A display panel having a display area (10 a), and a peripheral area (10 b) surrounding the display area (10 a), comprising: a substrate (101), a plurality of sub-pixels (102) and a plurality of test circuit groups (103) located on one side of the substrate (101); the plurality of sub-pixels (102) are located in the display area (10 a); the plurality of test circuit groups (103) are positioned in the peripheral area (10 b) and are arranged along the extending direction of the boundary of the display area (10 a); the set of test circuits (103) comprises at least one first test circuit (1031), each of the first test circuits (1031) comprising:

a first transistor (M1), the first transistor (M1) comprising a first gate;

a first control line (10311), wherein the first control line (10311) extends along a first direction (X), an orthographic projection of the first control line (10311) on the substrate (101) and an orthographic projection of the first gate electrode on the substrate (101) have a first overlapping region formed by at least partially overlapping, the first control line (10311) is electrically connected with the first gate electrode in the first overlapping region, the first control line (10311) is used for providing a first control signal for the first gate electrode, and the first transistor (M1) is turned on or off under the control of the first control signal provided by the first control line (10311);

a second transistor (M2), the second transistor (M2) comprising a second gate;

and a second control line (10312), wherein the second control line (10312) extends along the first direction (X), an orthogonal projection of the second control line (10312) on the substrate (101) and an orthogonal projection of the second gate electrode on the substrate (101) have a second overlapping region which is at least partially overlapped, the second control line (10312) and the second gate electrode are electrically connected in the second overlapping region, the second control line (10312) is used for providing a second control signal for the second gate electrode, and the second transistor (M2) is turned on or off under the control of the second control signal provided by the second control line (10312).

2. The display panel according to claim 1, characterized in that the display panel comprises: the substrate comprises an active layer (a 1), a first insulating layer (a 2), a first gate layer (a 3), a second insulating layer (a 4), a second gate layer (a 5), a third insulating layer (a 6), a first source drain layer (a 7), a fourth insulating layer (a 8) and a second source drain layer (a 9) which are sequentially stacked on the substrate base plate (101); the active layer (a 1) includes an active pattern (a 11); the first gate layer (a 3) includes at least a first gate pattern (a 31) and a second gate pattern (a 32) arranged along the second direction (Y), a portion where the first gate pattern (a 31) and the active pattern (a 11) overlap constitutes the first gate, and a portion where the second gate pattern (a 32) and the active pattern (a 11) overlap constitutes the second gate;

the first control line (10311) and the second control line (10312) are located on the first source drain layer (a 7), the first control line (10311) and the first gate pattern (a 31) are electrically connected through a first via hole in the second insulating layer (a 4) and the third insulating layer (a 6), and the second control line (10312) and the second gate pattern (a 32) are electrically connected through a second via hole in the second insulating layer (a 4) and the third insulating layer (a 6).

3. The display panel according to claim 2, wherein each of the first test circuits (1031) further comprises: a first signal input line (10313), a second signal input line (10314), and a first signal output line (10315); the first transistor (M1) further comprises a first source and a first drain, the second transistor (M2) further comprises a second source and a second drain;

-the first signal input line (10313) and the second signal input line (10314) each extend in the first direction (X), the first signal input line (10313) being electrically connected to the first source or the second source for providing a first input signal to the first source and the second source, the second signal input line (10314) being electrically connected to the first source or the second source for providing a second input signal to the second source;

the first signal output line (10315) extends in a second direction (Y) intersecting the first direction (X), the first signal output line (10315) is electrically connected to the first drain and the second drain, and the first signal output line (10315) is further connected to the plurality of sub-pixels (102), the first signal output line (10315) is used to transmit an input signal received from the first drain to the plurality of sub-pixels (102) in a case where the first control line (10311) controls the first transistor (M1) to be turned on and the second control line (10312) controls the second transistor (M2) to be turned off, the first signal output line (10315) is further used to transmit an input signal received from the second drain to the plurality of sub-pixels (102) in a case where the first control line (10311) controls the first transistor (M1) to be turned off and the second control line (10312) controls the second transistor (M2) to be turned on.

4. The display panel according to claim 3, wherein the first signal input line (10313) and the second signal input line (10314) are located at the second source drain layer (a 9); the first signal output line (10315) is located on the second gate layer (a 5); the first source-drain layer (a 7) includes at least a first source-drain pattern (a 71), a second source-drain pattern (a 72), and a third source-drain pattern (a 73) arranged along the second direction (Y); the first control line (10311) is located between the first source-drain pattern (a 71) and the second source-drain pattern (a 72), and the second control line (10312) is located between the second source-drain pattern (a 72) and the third source-drain pattern (a 73);

an orthographic projection of the first source-drain pattern (a 71) on the substrate base plate (101) is at least partially overlapped with an orthographic projection of the first signal input line (10313) on the substrate base plate (101), the first source-drain pattern (a 71) is electrically connected with the first signal input line (10313) through a third through hole in the fourth insulating layer (a 8), and the first source-drain pattern (a 71) is a first source electrode of the first transistor (M1);

an orthographic projection of the second source-drain pattern (a 72) on the substrate base plate (101) is at least partially overlapped with an orthographic projection of the first signal output line (10315) on the substrate base plate (101), the second source-drain pattern (a 72) is electrically connected with the first signal output line (10315) through a fourth through hole in the third insulating layer (a 6), and the second source-drain pattern (a 72) is a first drain electrode of the first transistor (M1) and a second drain electrode of the second transistor (M2);

an orthographic projection of the third source drain pattern (a 73) on the substrate base plate (101) is at least partially overlapped with an orthographic projection of the second signal input line (10314) on the substrate base plate (101), and the third source drain pattern (a 73) is electrically connected with the second signal input line (10314) through a fifth via hole in the fourth insulating layer (a 8), the third source drain pattern (a 73) being a second source of the second transistor (M2).

5. The display panel according to claim 4, wherein an orthographic projection of the first via on the substrate base plate (101) and an orthographic projection of the second via on the substrate base plate (101) are both located within an orthographic projection of the active pattern (a 11) on the substrate base plate (101);

an orthographic projection of the first gate pattern (a 31) on the substrate base plate (101) covers an orthographic projection of the first via hole on the substrate base plate (101), and an orthographic projection of the second gate pattern (a 32) on the substrate base plate (101) covers an orthographic projection of the second via hole on the substrate base plate (101).

6. The display panel according to claim 4, wherein an orthographic projection of the first via hole on the substrate base (101) and an orthographic projection of the second via hole on the substrate base (101) are non-overlapping with an orthographic projection of the active pattern (a 11) on the substrate base (101).

7. The display panel according to claim 6, wherein the second insulating layer (a 4) and the third insulating layer (a 6) comprise at least two of the first vias and two of the second vias; the active pattern (a 11) comprises a first part (a 111) and two second parts (a 112) positioned at two sides of the first part (a 111), the orthographic projection of the first part (a 111) on the substrate (101) is overlapped with the orthographic projection of the first gate pattern (a 31) on the substrate (101) and the orthographic projection of the second gate pattern (a 32) on the substrate (101), wherein the orthographic projection of one second part (a 112) on the substrate (101) is overlapped with the orthographic projection of the first source-drain pattern (a 71) on the substrate (101), and the orthographic projection of the other second part (a 112) on the substrate (101) is overlapped with the orthographic projection of the second source-drain pattern (a 72) on the substrate (101);

at least two of the first vias are arranged along the first direction (X) with the first portion (a 111), and at least two of the first vias are located at both sides of the first portion (a 111), a length of the first gate pattern (a 31) along the first direction (X) is greater than a length of the first portion (a 111) along the first direction (X), the first gate pattern (a 31) includes a first region and a second region which are not overlapped with the first portion (a 111) and are arranged along the first direction (X), and the first control line (10311) and the first gate pattern (a 31) are electrically connected through at least one of the first vias in the first region and the second region, respectively;

at least two of the second vias are arranged along the first direction (X) with the first portion (a 111), and at least two of the second vias are located at both sides of the first portion (a 111), a length of the second gate pattern (a 32) along the first direction (X) is greater than a length of the first portion (a 111) along the first direction (X), the second gate pattern (a 32) includes a third region and a fourth region which are not overlapped with the first portion (a 111) and are arranged along the first direction (X), and the second control line (10312) and the second gate pattern (a 32) are electrically connected through at least one of the second vias in the third region and the fourth region, respectively.

8. The display panel according to claim 6, wherein the second insulating layer (a 4) and the third insulating layer (a 6) comprise at least two of the first vias and two of the second vias; the active pattern (a 11) includes a first portion (a 111), and two second portions (a 112) located at both sides of the first portion (a 111), an orthographic projection of the first portion (a 111) on the substrate base (101) overlaps with an orthographic projection of the first gate pattern (a 31) on the substrate base (101) and an orthographic projection of the second gate pattern (a 32) on the substrate base (101), wherein an orthographic projection of one of the second portions (a 112) on the substrate base (101) overlaps with the first source portion of the first transistor (M1), and an orthographic projection of the other of the second portions (a 112) on the substrate base (101) overlaps with the second source portion of the second transistor (M2);

at least two of the first vias are arranged along the first direction (X) with the first portion (a 111) and are located at one side of the first portion (a 111), a length of the first gate pattern (a 31) along the first direction (X) is greater than a length of the first portion (a 111) along the first direction (X), the first gate pattern (a 31) includes a fifth region that is not overlapped with the first portion (a 111), and the first control line (10311) and the first gate pattern (a 31) are electrically connected by at least two of the first vias in the fifth region;

at least two of the second vias are arranged along the first direction (X) with the first portion (a 111) and are located at one side of the first portion (a 111), a length of the second gate pattern (a 32) along the first direction (X) is greater than a length of the first portion (a 111) along the first direction (X), the second gate pattern (a 32) includes a sixth region that is not overlapped with the first portion (a 111), and the second control line (10312) and the second gate pattern (a 32) are electrically connected through at least two of the second vias in the sixth region.

9. The display panel according to claim 8, wherein at least two of the first vias are arranged along the first direction (X) or at least two of the first vias are arranged along the second direction (Y);

at least two of the second vias are arranged along the first direction (X), or at least two of the second vias are arranged along the second direction (Y).

10. A display panel as claimed in any one of the claims 7 to 9 characterized in that the length of the first portion (a 111) in the first direction (X) is smaller than or equal to the length of the second portion (a 112) in the first direction (X).

11. The display panel according to any of claims 4 to 9, wherein for each of the first source-drain pattern (a 71), the second source-drain pattern (a 72) and the third source-drain pattern (a 73), an orthographic projection of the source-drain pattern on the substrate base plate (101) at least partially overlaps an orthographic projection of the active pattern (a 11) on the substrate base plate (101), and the source-drain pattern and the active pattern (a 11) are electrically connected through a sixth via in the first insulating layer (a 2), the second insulating layer (a 4) and the third insulating layer (a 6).

12. The display panel according to any of claims 1 to 9, wherein the group of test circuits (103) comprises two first test circuits (1031) arranged in the second direction (Y); two of the first test circuits (1031) share one first signal input line (10313), or two of the first test circuits (1031) share one second signal input line (10314).

13. A display panel according to claim 12, wherein the first signal output line (10315) in a first one of the first test circuits (1031) and the first signal output line (10315) in a second one of the first test circuits (1031) are respectively located on both sides of transistors included in the two first test circuits (1031).

14. The display panel according to any one of claims 1 to 9, further comprising a plurality of second test circuits located in the peripheral region (10 b) and arranged along an extending direction of a boundary of the display region (10 a); each of the second test circuits includes a second signal output line; the plurality of sub-pixels (102) form a plurality of first pixel columns (102 a) and a plurality of second pixel columns (102 b), each of the first pixel columns (102 a) comprising a plurality of first color sub-pixels and a plurality of second color sub-pixels, each of the second pixel columns (102 b) comprising a plurality of third color sub-pixels;

a first signal output line (10315) of each of the first test circuits (1031) is connected to a plurality of first color sub-pixels and a plurality of second color sub-pixels of one of the first pixel columns (102 a), and a second signal output line of each of the second test circuits is connected to a plurality of third color sub-pixels of one of the second pixel columns (102 b).

15. A display device, characterized in that the display device comprises: -a power supply assembly (20) and a display panel (10) according to any of claims 1 to 14;

the power supply assembly (20) is used for supplying power to the display panel (10).

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