CN115470750A - Chip performance verification system based on tracking file - Google Patents

Chip performance verification system based on tracking file Download PDF

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CN115470750A
CN115470750A CN202211160337.XA CN202211160337A CN115470750A CN 115470750 A CN115470750 A CN 115470750A CN 202211160337 A CN202211160337 A CN 202211160337A CN 115470750 A CN115470750 A CN 115470750A
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CN115470750B (en
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不公告发明人
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Muxi Technology Beijing Co ltd
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Abstract

The invention relates to a chip performance verification system based on a trace file, which realizes the step S1 of obtaining IT (information technology) based on a DUT (device under test) k Corresponding description information; s2, running the DUT and unloading IT from the DUT k A corresponding bus interface active bus interface data record, the bus interface including an IT bus interface k The signal value, absolute time and/or clock cycle number corresponding to each signal in the signal is based on IT k Generating a tracking file by the corresponding description information and the effective bus interface data record of the bus interface; step S3, based on IT k Corresponding trace file determination IT k Corresponding throughput and delay, and applying the IT k And comparing the corresponding throughput and delay with the corresponding throughput target value and delay target value in the configuration file to realize chip performance verification. The invention can quickly and accurately acquire the data of all target nodes for performance verification, and improves the efficiency and the accuracy of chip performance verification.

Description

Chip performance verification system based on trace file
Technical Field
The invention relates to the technical field of chip verification, in particular to a chip performance verification system based on a trace file.
Background
Large multichip chips are currently available that are highly stacked from multiple constituent modules, such as GPU chips. In the prior art, in the process of performing performance verification on a chip, performance verification is usually performed by writing a corresponding RTL (Register translator Level) code, and since the chip is large in scale, a large amount of RTL codes need to be written. In the process of verifying the chip performance, the performance parameters may change continuously, so that a large amount of RTL codes need to be changed continuously. In addition, in the performance verification process, the chip design is usually in a deep Pipeline (Pipeline) form, data of a head node and a tail node of the Pipeline can be directly acquired for performance verification, but data of many Pipeline intermediate nodes cannot be directly acquired for performance verification, so that the efficiency of chip performance verification is low, and errors are prone to occur. Therefore, how to improve the efficiency and accuracy of chip performance verification becomes an urgent technical problem to be solved.
Disclosure of Invention
The invention aims to provide a chip performance verification system based on a trace file, which can quickly and accurately acquire data of all target nodes for performance verification and improve the efficiency and accuracy of chip performance verification.
The invention provides a chip performance verification system based on trace files, which comprises a to-be-tested chip design DUT = { U = 1 ,U 2 ,…U M U, a performance profile, a memory storing a computer program, and a processor, wherein U m Forming a module for the mth component of the DUT, wherein the value of M ranges from 1 to M, U 1 ,U 2 ,…U M Hierarchical arrangement, U i And U j Are interconnected through at least one bus interface, U i And U j For two constituent modules with an interconnection relationship, the value ranges of i and j are from 1 to M, U i And U j The bus interfaces are brother modules or father and child modules with an interconnection relationship, and the brother modules or the father and child modules with the interconnection relationship are interconnected through at least one bus interface; the presence of at least one target bus interface IT in a DUT k K ranges from 1 to K, K is the total number of target bus interfaces, and the performance configuration file is used for configuring IT k A corresponding throughput target value and a delay target value;
the processor, when executing the computer program, implements the steps of:
step S1, obtaining IT based on DUT k Corresponding description information including IT k Corresponding component module identification, bus interface signal and IT k Signal mapping information, signal description information, data valid identification constraint information of, saidGenerating a bus interface identifier based on hierarchy information corresponding to the bus interface and a bus interface instance name, wherein the signal description information comprises signal width and signal direction;
s2, running the DUT and unloading IT from the DUT k A corresponding bus interface active bus interface data record, the bus interface including an IT bus interface k The signal value, absolute time and/or clock cycle number corresponding to each signal in the signal is based on IT k Generating a tracking file by recording corresponding description information and bus interface effective bus interface data;
step S3, based on IT k Corresponding trace file determination IT k Corresponding throughput and delay, and converting the IT k And comparing the corresponding throughput and delay with the corresponding throughput target value and delay target value in the configuration file to realize chip performance verification.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the chip performance verification system based on the trace file can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:
the system of the invention realizes the performance verification by rapidly and accurately acquiring the data of all target nodes and improving the efficiency and the accuracy of the chip performance verification by setting the target bus interfaces and the performance configuration files and storing the data corresponding to each target bus interface.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are specifically described below with reference to the accompanying drawings.
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FIG. 1 is a schematic diagram of a trace file based chip performance verification system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a trace file format according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a trace file format according to another embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, the following detailed description will be given with reference to the accompanying drawings and preferred embodiments of a chip performance verification system based on trace files according to the present invention.
An embodiment of the present invention provides a trace file based chip performance verification system, as shown in fig. 1, including a Design Under Test (DUT), and the DUT = { U = 1 ,U 2 ,…U M A performance profile, a memory storing a computer program, and a processor. Wherein, U m The M-th component module of the DUT, wherein the value of M ranges from 1 to M, U 1 ,U 2 ,…U M Hierarchical arrangement, U i And U j Are interconnected through at least one Bus Interface (U) i And U j For two constituent modules with an interconnection relationship, the value ranges of i and j are both 1 to M and U i And U j The modules are interconnected through at least one bus interface, wherein the modules are brother modules or father-child modules with an interconnection relationship, and the brother modules or father-child modules with the interconnection relationship; the presence of at least one target bus interface IT in a DUT k The value range of K is 1 to K, and K is the total number of target bus interfaces, and it can be understood that the target bus interfaces may be external bus interfaces of the DUT, or bus interfaces corresponding to intermediate nodes between component modules inside the DUT or between the component modules and sub-modules. The performance configuration file is used for configuring IT k A corresponding throughput target value and a delay target value.
When the processor executes the computer program, the following steps are realized:
step S1, obtaining IT based on DUT k Corresponding description information including IT k Corresponding component module identification, bus interface identification and bus interface informationNumber and IT k Signal mapping information, signal description information, and data valid identification constraint information, wherein the signal description information includes signal width and signal direction.
Wherein, IT k The corresponding component module may be IT k The initiating terminal or the receiving terminal as an initiating terminal component module, IT k The corresponding bus interface information is stored in the corresponding component module, and it can be understood that each bus interface information will be stored in the corresponding initiating terminal component module or in the corresponding receiving terminal component module. The description information also comprises IT k And identifying the corresponding bus interface type.
Step S2, operating the DUT, and transferring (Dump) IT from the DUT k A corresponding active bus interface data record comprising IT k The signal value, absolute time and/or clock cycle number corresponding to each signal in the signal processing unit is based on IT k The corresponding description information and the valid bus interface data record generate a trace file.
Wherein, the DUT is driven by a verification platform (Testbench) corresponding to the DUT. The serial number of the clock Cycle (Cycle) indicates the corresponding clock Cycle, the absolute time indicates the time counted from the initial time, and the time corresponding to a group of signals corresponding to an effective bus interface data record is collected.
Step S3, based on IT k Corresponding trace file determination IT k Corresponding throughput and delay, and applying the IT k And comparing the corresponding throughput and delay with the corresponding throughput target value and delay target value in the configuration file to realize chip performance verification.
As an example, in the step S2, based on IT k Generating a trace file according to a preset trace file structure by corresponding description information and effective bus interface data records, wherein the preset trace file structure comprises a first file area and a second file area, and the first file area is used for storing IT k And the second file area is used for storing effective bus interface data records. What is needed isThe active bus interface data records are stored row by row, i.e., each active bus interface data record occupies one row, as illustrated by example in fig. 2. The active bus interface data records may also be stored column by column, i.e. each active bus interface data record occupies one column, as illustrated in the example of fig. 3. Target data corresponding to any one target bus interface bus can be quickly and accurately acquired through the trace file, chip performance verification is achieved, Z in both the graph 2 and the graph 3 represents the total number of effective bus interface data records, the reference numeral 1 represents a first file area, and the reference numeral 2 represents a second file area.
As an example, U m The atomic unit may be an atomic unit or a module composed of atomic units, the atomic unit is preset with a corresponding RTL code, and the RTL code may be specifically written in hardware programming languages such as Verilog, system Verilog, VHDL, and the like. Set m = i1, U i1 Including a module unique identifier MID i1 And Mod i1 Z1 (i 1) module internal bus Interface (Interface) list (InI) of interconnection of sub-modules 1 ,InI 2 ,...,InI Z1(i1) ) And with Mod i1 Z2 (i 1) module External bus Interface (External Interface) list (MExI) of sibling module interconnections of 1 ,MExI 2 ,...,MExI Z2(i1) ). The Mod i1 Is positioned at Mod i1 Internal and proportional Mod i1 One level lower constituent modules. The DUT further comprises a device capable of generating K4 Design Interconnect assemblY DIY (Design Interconnect assemblY) = (X) based on the internal bus interface list and the external bus interface list corresponding to all the component modules 1 _Y 1 _CMD 1 ,X 2 _Y 2 _CMD 2 ,......，X K4 _Y K4 _CMD K4 ) Wherein X is i5 And Y i5 Belong to { U 1 ,U 2 ,…U M I5 ranges from 1 to K4; x i5 And Y i5 Modules of mutual brothers, or X i5 Is Y i5 Or Y, or i5 Is X i5 The parent module of (1).
As an example, X i5 And X i6 May be the same or different；Y i5 And Y i6 May be the same or different; the value of i6 ranges from 1 to K4.CMD i5 For IDF-ID, the bus Interface Description reconstruction library is used for acquiring corresponding bus Interface detail information from the bus Interface Description reconstruction library, and the bus Interface Description reconstruction library comprises K3 predefined bus Interface reconstruction structures IDF (Interface Description factor) = (IDF) 1 ,IDF 2 ,...,IDF K3 )，K3>And =0. Wherein, IDF i3 Including bus interface unique identification IDF-ID i3 Z4 (i 3) signals (Sig) i3 1 ,Sig i3 2 ,...,Sig i3 z4(i3) )，Sig i3 i4 Including signal direction, signal width Wid (i 3, i 4), reSeT (ReSeT) value (RST) i3i4 1 ，RST i3i4 2 ，...，RST i3i4 Wid(i3,i4) ) Default (Default) value (Def) i3i4 1 ，Def i3i4 2 ，...，Def i3i4 Wid(i3,i4) ) And data valid identification constraint information. i3 has a value from 1 to K3, i4 has a value from 1 to Z4 (i 3), Z4 (i 3) being a function of i 3.
Preferably, IDF-ID i3 Associated with the bus interface type. The bus interface type is, for example, an AMBA bus, a PCIE bus, a SATA bus, a USB bus, an HBM bus, or a custom bus interface type. The signal directions may be set to an Input direction (Input), an Output direction (Output), and a bidirectional direction (Inout). The signal width Wid (i 3, i 4) is signal Sig i3 i4 The number of signal lines (Wire) used.
As an example, IT k The corresponding signals include at least one valid identification signal, a trace id signal, and a data signal, the data valid identification constraint information including a constraint generated based on all valid identification signals. By IT k The corresponding signal includes { Si 1 ,Si 2 ,…Si R For example, si may be provided only 1 For valid identification signals, when Si 1 When the signal value of (c) is equal to the preset signal value, the corresponding Si is described 2 ,…Si R Is valid data. Or a plurality of signals, e.g. Si 1 ,Si 2 ,Si 3 Satisfies a predetermined constraint, e.g. when the sum equals a predetermined signal value, corresponding to Si 1 ,Si 4 …Si R Is valid data. One of the signals, e.g. Si R For tracking id signals, the id signals may be specifically configured as a structure or a complex, it should be noted that the id signals are in the same data chain, and the same data transmitted by the id signals are the same, but because signal formats corresponding to different bus interface buses may be different, forms corresponding to different bus interface buses of the id signals may be different. The tracking id signal and the valid identification signal correspond to different signals, IT k All signals except the valid identification signal and the trace id signal in the corresponding signals are data signals.
Based on the U i1 DIY and IDF information can be automatically generated into IT k Corresponding description information.
In the step S2, when IT is in the DUT k Unloading IT from the DUT when the corresponding valid identification signal satisfies the corresponding data valid identification constraint information k The corresponding active bus interface data record.
Get each IT in dump k After the corresponding trace file, corresponding file information can be extracted in a post-processing mode and stored in a database, and chip performance verification is further realized based on the database. As an embodiment, the system further includes a database, and after the step S2, the method further includes:
step S10, corresponding values of the corresponding tracking id signals in the data records of each effective bus interface are recorded according to IT k And decoding the corresponding encoding rule, and then storing the trace file decoded by the trace id into the database.
As an example, IT k The corresponding signal is listed as { Si 1 ,Si 2 ,…Si f(k) },Si ik Is IT k Corresponding ik signal, ik ranging from 1 to f (k) as a function of k, si ik Corresponding signal width We ik The step S3 includes:
step S31, based on IT k Acquiring a corresponding tracking file by using the corresponding bus interface identifier;
step S32, slave IT k Selecting F-line effective bus interface data records from the corresponding tracking files, determining the time TF required for acquiring the F-line effective bus interface data records based on the absolute time and/or clock cycle serial number corresponding to the F-line effective bus interface data records, and based on the TF and We ik F determining IT k Corresponding throughput TH k :
Figure BDA0003859529970000061
From IT k Selecting a target tracking id and an absolute time and/or a clock cycle sequence number corresponding to the target request information from the corresponding tracking file, and selecting the target tracking id and the absolute time and/or the clock cycle sequence number from the IT according to the target tracking id k Absolute time and/or clock cycle sequence number corresponding to target response information corresponding to target request information in the corresponding trace file, and IT is determined based on the absolute time and/or clock cycle sequence number corresponding to the target request information and the target response information k Correspondingly delaying time;
step S33, converting the IT k And comparing the corresponding throughput and delay with the corresponding throughput target value and delay target value in the configuration file, if the throughput and the delay are matched, the chip performance passes verification, and otherwise, generating early warning information.
It should be noted that the throughput target value and the delay target value may be specific values, or may be a range of values, which is specifically determined according to the performance test requirement. If the throughput target value and the delay target value are specific values, IT k And determining that the throughput is matched when the corresponding throughput is equal to the corresponding throughput target value in the configuration file. IT (information technology) device k And determining that the corresponding delay is equal to the corresponding delay target value in the configuration file as delay matching. If the throughput target value and the delay target value are in the numerical range, IT k When the corresponding throughput is in the numerical range of the throughput target value, determining that the throughput is matched; if IT is k Determining when the corresponding delay is within the value range of the delay target valueIs delay matching.
After the database is generated based on the trace file, the performance verification result can be further visually displayed through a display interface, and the chip performance verification efficiency is further improved. As one example. The system further comprises a display interface, and the display interface can be a GUI interface. The display interface is configured to present a data stream topology corresponding to the DUT, where the data stream topology includes component modules of the DUT and bus interfaces between the component modules, and in step S3, if the early warning information is generated, the step S3 further includes:
step S4, if TH is true k If the throughput target value is higher than the target value, the IT corresponding to the data stream topological structure k Displaying a first prompt identifier; if TH k If the throughput is lower than the target value, the IT corresponding to the data stream topological structure k Displaying a second prompt identifier; if IT k If the corresponding delay is higher than the delay target value, the IT corresponding to the data stream topological structure k Displaying a third prompt identification; if TH k If the throughput is lower than the target value, the IT corresponding to the data stream topological structure k And displaying a fourth prompt mark.
It should be noted that the first prompt identifier, the second prompt identifier, the third prompt identifier, and the fourth prompt identifier may be displayed in different colors, shapes, and the like. Can also be based on TH k By a magnitude of a difference from a target value of throughput, IT k The throughput and the throughput target value are further displayed by adopting prompt marks of different levels.
As an embodiment, the step S4 may further include:
step S5, if a first display instruction generated aiming at a first prompt identifier is received or a second display instruction generated aiming at a second prompt identifier is received, analyzing IT from the first display instruction or the second display instruction k A corresponding bus interface identifier;
the prompt mark can be selected directly by clicking and the like to generate a corresponding display instruction.
Step (ii) ofS6, based on IT k And retrieving the database by the corresponding bus interface identifier, and displaying the generated F-row effective bus interface data record corresponding to the corresponding early warning information on the display interface.
As an embodiment, the step S4 may further include:
step S5', if a third display instruction generated aiming at a third prompt mark or a fourth display instruction generated aiming at a fourth prompt mark is received, analyzing IT from the third display instruction or the fourth display instruction k A corresponding bus interface identifier;
step S6' based on IT k And retrieving the database by the corresponding bus interface identifier, and displaying the generated target request information corresponding to the corresponding early warning information and the effective bus interface data record corresponding to the target response information on the display interface.
By displaying the corresponding prompt identification and presenting the corresponding effective bus interface data record on the display interface, the relevant data of the chip performance test can be visually tracked, and the efficiency of the chip performance test is improved.
Because the performance test parameters of the DUT can be changed at any time, the corresponding performance test parameters can be changed by changing the performance configuration file, so that the change of a large amount of RTL codes is avoided, and errors are not easy to occur k Corresponding throughput target value and delay target value, wherein the performance configuration file comprises IT k Identification and IT k Identifying the corresponding processor, when executing the computer program, to implement the steps of:
step S100, if a performance configuration file updating instruction is received, updating the performance configuration file, specifically including adding an IT newly k And IT k Deleting IT according to the throughput target value and the delay target value k And IT k Corresponding throughput target value and delay target value, and updating existing IT k A corresponding throughput target value and/or a delay target value.
The system of the invention realizes the rapid and accurate acquisition of the data of all target nodes for performance verification by setting the target bus interfaces and the performance configuration file and transferring the data corresponding to each target bus interface, thereby improving the efficiency and the accuracy of chip performance verification.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but could have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A chip performance verification system based on trace files is characterized in that,
design DUT = { U) including chip under test 1 ,U 2 ,…U M }, a performance profile, a memory storing a computer program and a processor, wherein U m Forming a module for the mth component of the DUT, wherein the value of M ranges from 1 to M, U 1 ,U 2 ,…U M Hierarchical arrangement, U i And U j Are interconnected by at least one bus interface, U i And U j For two constituent modules with an interconnection relationship, the value ranges of i and j are from 1 to M, U i And U j The bus interface is brother module or father-son module with interconnection relationshipThe interconnection relation brother modules or the father and son modules are interconnected through at least one bus interface; the presence of at least one target bus interface IT in a DUT k K ranges from 1 to K, K is the total number of target bus interfaces, and the performance configuration file is used for configuring IT k A corresponding throughput target value and a delay target value;
when the processor executes the computer program, the following steps are realized:
step S1, obtaining IT based on DUT k Corresponding description information including IT k Corresponding component module identification, bus interface signal and IT k The bus interface identifier is generated based on the hierarchy information corresponding to the bus interface and the name of the bus interface instance, and the signal description information comprises signal width and signal direction;
s2, running the DUT and unloading IT from the DUT k A corresponding bus interface active bus interface data record, the bus interface including an IT bus interface k The signal value, absolute time and/or clock cycle number corresponding to each signal in the signal processing unit is based on IT k Generating a tracking file by the corresponding description information and the effective bus interface data record of the bus interface;
step S3, based on IT k Corresponding trace file determination IT k Corresponding throughput and delay, and applying the IT k And comparing the corresponding throughput and the corresponding delay with the corresponding throughput target value and the corresponding delay target value in the configuration file to realize the chip performance verification.
2. The system of claim 1,
IT k the corresponding signals comprise at least one valid identification signal, a tracking id signal and a data signal, and the data valid identification constraint information comprises a constraint condition generated based on all valid identification signals;
in the step S2, when IT is in the DUT k Corresponding valid identification signal fullWhen the corresponding data is valid for identifying the constraint information, the IT is transferred and stored from the DUT k The corresponding bus interface valid bus interface data records the bus interface.
3. The system of claim 1,
the system further comprises a database, and after the step S2, the method further comprises:
step S10, recording the effective bus interface data of each bus interface into the corresponding value of the corresponding tracking id signal in the bus interface according to IT k And decoding the corresponding encoding rule, and then storing the trace file decoded by the trace id into the database.
4. The system of claim 1,
IT k the corresponding signal list is { Si 1 ,Si 2 ,…Si f(k) },Si ik Is IT k Corresponding ik signal, ik ranging from 1 to f (k) as a function of k, si ik Corresponding signal width of We ik And the step S3 comprises the following steps:
step S31, based on IT k Acquiring a corresponding tracking file by the corresponding bus interface identifier;
step S32, slave IT k Selecting F-line effective bus interface data records from the corresponding tracking files, determining the time TF required for acquiring the F-line effective bus interface data records based on the absolute time and/or clock cycle serial number corresponding to the F-line effective bus interface data records, and based on the TF and We ik F determining IT k Corresponding throughput TH k :
Figure FDA0003859529960000021
From IT k Selecting a target tracking id and an absolute time and/or a clock cycle sequence number corresponding to the target request information from the corresponding tracking file, and selecting the target tracking id and the absolute time and/or the clock cycle sequence number from the IT based on the target tracking id k Target request information in corresponding trace fileAbsolute time and/or clock cycle sequence number corresponding to the corresponding target response information, and determining IT based on the absolute time and/or clock cycle sequence number corresponding to the target request information and the target response information k Correspondingly delaying time;
step S33, converting the IT k And comparing the corresponding throughput and delay with the corresponding throughput target value and delay target value in the configuration file, if the throughput and the delay are matched, the chip performance passes verification, and otherwise, generating early warning information.
5. The system of claim 1,
the system further includes a display interface, where the display interface is configured to present a data stream topology corresponding to the DUT, where the data stream topology includes constituent modules of the DUT and bus interfaces between the constituent modules, and in step S3, if the early warning information is generated, the step S3 further includes:
step S4, if TH is true k If the throughput target value is higher than the target value, the IT corresponding to the data stream topological structure k Displaying a first prompt mark; if TH k If the throughput is lower than the target value, the IT corresponding to the data stream topological structure k Displaying a second prompt identifier; if IT is k If the corresponding delay is higher than the delay target value, the IT corresponding to the data stream topological structure k Displaying a third prompt identification; if TH k If the throughput is lower than the target value, the IT corresponding to the data stream topological structure k And displaying a fourth prompt identification.
6. The system of claim 5,
after the step S4, the method further includes:
step S5, if a first display instruction generated aiming at a first prompt identifier is received or a second display instruction generated aiming at a second prompt identifier is received, analyzing IT from the first display instruction or the second display instruction k A corresponding bus interface identifier;
step S6, based on IT k Corresponding busAnd the interface identifier retrieves the database and displays the generated F-row effective bus interface data record corresponding to the corresponding early warning information on the display interface.
7. The system of claim 5,
after the step S4, the method further includes:
step S5', if a third display instruction generated aiming at a third prompt mark or a fourth display instruction generated aiming at a fourth prompt mark is received, analyzing IT from the third display instruction or the fourth display instruction k A corresponding bus interface identifier;
step S6' based on IT k And retrieving the database by the corresponding bus interface identifier, and displaying the target request information corresponding to the generated corresponding early warning information and the effective bus interface data record corresponding to the target response information on the display interface.
8. The system of claim 1,
IT k corresponding throughput target value and delay target value, wherein the performance configuration file comprises IT k Identification and IT k Identifying the corresponding processor, when executing the computer program, to implement the steps of:
step S100, if a performance configuration file updating instruction is received, updating the performance configuration file, specifically including adding an IT newly k And IT k Deleting IT corresponding to the target value of throughput and the target value of delay k And IT k Updating the existing T according to the corresponding target value of throughput and target value of delay k A corresponding throughput target value and/or a delay target value.
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