CN113702816B - Register unit design method based on boundary scanning - Google Patents
Register unit design method based on boundary scanning Download PDFInfo
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- CN113702816B CN113702816B CN202110991352.8A CN202110991352A CN113702816B CN 113702816 B CN113702816 B CN 113702816B CN 202110991352 A CN202110991352 A CN 202110991352A CN 113702816 B CN113702816 B CN 113702816B
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000013461 design Methods 0.000 title claims abstract description 9
- 238000012360 testing method Methods 0.000 claims description 17
- 238000004088 simulation Methods 0.000 claims description 16
- 238000012905 input function Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 8
- 238000005206 flow analysis Methods 0.000 abstract description 3
- 238000005457 optimization Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 11
- 230000002457 bidirectional effect Effects 0.000 description 4
- 230000003993 interaction Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000013101 initial test Methods 0.000 description 1
- 238000013433 optimization analysis Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318583—Design for test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318597—JTAG or boundary scan test of memory devices
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of integrated circuits, in particular to a register unit design method based on boundary scanning, which adds capture_en and update_en signals as capturing triggers and updating the enabling ends of the triggers on the basis of the traditional boundary scanning register unit structure, and the technical scheme combines a gate circuit with optimal performance as far as possible according to the performance parameters of the gate circuit in the process of gradually optimizing the circuit from a complex circuit structure to an optimized circuit to form an optimized bc_2 unit; in addition, in the optimization process aiming at the bc_7 unit, an independent function data flow analysis method is adopted, the functions to be realized by a single circuit are split one by one, the data flow paths of the single circuit are analyzed for each function, and finally, various independent data flows are combined, so that redundant signals or circuit structures in the original circuit structure are abandoned.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a register unit design method based on boundary scanning.
Background
Boundary scan, an IEEE (1149.1) or JTAG (Joint Test Action Group) standard, aims to realize controllability and observability of input and output pins of a chip, and further test logic and interconnection inside the chip.
The basic boundary scan chain structure includes a generic data port for external Pin (PAD) and internal logic interactions and a test data port; the test data port is used for serial shift-in of initial test data and serial shift-out of test feedback data.
Boundary scan registers are considered the most important of all registers within the IEEE 1149.1 standard, placed at the boundary of the core logic under test. The register unit may enter between an external Pin (PAD) and the core logic port, which may improve the controllability and observability of the core logic inputs and outputs. Fig. 1 shows a conventional boundary scan register cell structure, where DataIn and DataOut are general purpose data ports and ScanIn and ScanOut are test data ports.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a register unit design method based on boundary scanning, and the technical problem to be solved is how to optimize a BC unit based on the traditional boundary scanning register unit by changing the number of signals and gates according to the design.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: a register unit design method based on boundary scan increases capture_en and update_en signals as enabling ends of capture triggers and update triggers on the basis of a traditional boundary scan register unit structure;
After the simulation mode is started, test data sequentially pass through bc_2 units of each stage to be shifted into a scanning chain in series under the control of a shift_dr signal and a capture_en signal, and the captured test data is output from a data output port under the enabling of the update_en signal and the mode signal. When the data output port is respectively connected with the OEN and the I end of the PAD, under the condition that the OEN value is 0, the output function simulation can be completed;
Under the condition that the value of the OEN end is 1, the PAD port is assigned, the value of the C port of the PAD is located at the D input end of the capture register, then under the control of a capture_en signal and a shift_dr signal, data in a capture state are serially shifted out of a scanning chain through ScanIn and ScanOut ports of each stage bc_2 unit, observation of data at the output end of the PAD is achieved, and simulation of input functions can be completed.
And analyzing the data flow directions of the input and output simulation processes under the test mode by utilizing the bidirectional test function of the bc_2 unit to the PAD, and further fusing the two to form the bc_7 unit. After the test data shift is completed, the updated output data in the bc_2 unit is used for controlling the OEN port value corresponding to the PAD, so that the simulation of the input or output function of the PAD is determined, and the bc_7 unit at the subsequent stage realizes the bidirectional passage of the PAD port data and the internal logic data at the same time, so that the corresponding simulation is performed according to the OEN value.
The beneficial effects brought by the technical scheme are as follows: in the technical scheme, in the process of gradually optimizing a circuit from a complex circuit structure, according to the performance parameters of the gate circuit, the gate circuit with optimal performance is combined as far as possible; in addition, in the optimization process aiming at the bc_7 unit, an independent function data flow analysis method is adopted, the functions to be realized by a single circuit are split one by one, the data flow paths of the single circuit are analyzed for each function, and finally, various independent data flows are combined, so that redundant signals or circuit structures in the original circuit structure are abandoned.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a block diagram of a conventional boundary scan register unit;
FIG. 2 is a block diagram of the Synopsys DW series DW_bc_2 unit;
FIG. 3 is a block diagram of the bc_2 cell with an active low enable signal D flip-flop;
FIG. 4 is a block diagram of the bc_2 cell with 4-input multiplexer;
FIG. 5 is a block diagram of an optimized bc_2 unit in the present invention;
FIG. 6 is a block diagram of the Synopsys DW series DW_bc_7 unit;
FIG. 7 is a block diagram of the bc_7 unit of simplified construction;
FIG. 8 is a flow chart of simulated data of the output function in the present invention;
FIG. 9 is a flow chart of simulated data for input functions in the present invention;
FIG. 10 is a block diagram of an optimized bc_7 cell of the present invention;
FIG. 11 is a circuit block diagram of a boundary scan chain based on a single bc_2 cell;
FIG. 12 is a circuit block diagram of a boundary scan chain based on the merging of bc_2 and bc_7 cells;
FIG. 13 is a diagram of an optimized boundary scan chain circuit configuration in accordance with the present invention.
Detailed description of the inventionpreferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for purposes of illustration and explanation only, and are not intended to limit the present invention.
As shown in FIG. 2, the Synopsys DW series BC unit DW_bc_2 is added with two multiplexers based on the traditional boundary scan register unit structure, and the signals of capture_en and update_en are used as respective selection terminals and are respectively used as the D terminal input of a capture trigger and an update trigger.
On the basis, the multiplexer under the control of capture_en and the capture trigger under the control of capture_clk are combined to form a D trigger with an active low enable signal, and two-input multiplexers under the control of capture_en and shift_dr can be combined into a four-input multiplexer. The above-mentioned deformation processes are shown in fig. 3 and fig. 4, respectively, and these two cell structures are two boundary scan bc_2 cell structures that occur in the DW series at present.
Thus, the multiplexers and flip-flops can be combined maximally based on the original dw_bc_2 unit, i.e. the multiplexers under the control of capture_en and update_en are combined with the flip-flops under the control of capture_clk and update_clk, respectively, and the optimized circuit is shown in fig. 5.
To enable bi-directional interaction of the external Pin (PAD) and the internal logic, another Synopsys DW series BC unit dw_bc_7 is introduced here, as shown in fig. 6.
The multiplexer under the control of mode2 can be omitted for the purpose of simplifying the data path on the basis, and the unit structure is the boundary scan bc_7 unit which is present in the current DW series, as shown in fig. 7.
In the simulation mode, the simulation data flows of the output function and the input function are as shown in fig. 8 and 9, and the middle redundant logic is omitted in the external pin and the internal logic data interaction path; the simulation mode realizes the control and observation of the bidirectional data flow in the same boundary scan register unit according to the data path in the figure, and the optimized bc_7 unit circuit is shown in fig. 10.
The two boundary scan chain circuit architecture designs used at this stage are based on a single bc_2 cell and a combination of bc_2 and bc_7 cells, respectively. The circuit configuration of the former is shown in fig. 11. After the simulation mode is started, test data sequentially pass through bc_2 units of each stage to be shifted into a scanning chain in series under the control of a shift_dr signal and a capture_en signal, and the captured test data is output from a data output port under the enabling of the update_en signal and the mode signal. When the data output port is respectively connected with the OEN and the I end of the PAD, under the condition that the OEN value is 0, the output function simulation can be completed; under the condition that the value of the OEN end is 1, the PAD port is assigned, the value of the C port of the PAD is located at the D input end of the capture register, then under the control of a capture_en signal and a shift_dr signal, data in a capture state are serially shifted out of a scanning chain through ScanIn and ScanOut ports of each stage bc_2 unit, observation of data at the output end of the PAD is achieved, and simulation of input functions can be completed.
As shown in FIG. 12, after the test data shift is completed, the updated output data in the bc_2 unit controls the OEN port value of the corresponding PAD, thereby determining the simulation of the input or output function of the PAD. The bc_7 unit of the latter stage may implement bidirectional paths of PAD port data and internal logic data at the same time.
From the previous BC unit optimization analysis, the multiplexer select signal of the bc_7 unit controlled by the OEN port of the PAD can be ignored, thus combining the optimized bc_2 and bc_7 units, and the final optimized boundary scan chain circuit is shown in fig. 13.
In the technical scheme, in the process of gradually optimizing a circuit from a complex circuit structure, according to the performance parameters of the gate circuit, the gate circuit with optimal performance is combined as far as possible; in addition, in the optimization process aiming at the bc_7 unit, an independent function data flow analysis method is adopted, the functions to be realized by a single circuit are split one by one, the data flow paths of the single circuit are analyzed for each function, and finally, various independent data flows are combined, so that redundant signals or circuit structures in the original circuit structure are abandoned.
Finally, it should be noted that: the foregoing is merely a preferred example of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (1)
1. A register unit design method based on boundary scan is characterized in that a traditional boundary scan register unit structure comprises two-input multiplexers and two capture triggers; the first input ends of the two-input multiplexers are connected with a DataIn port, the second input end of the two-input multiplexer under the control of a shift_dr signal is connected with a ScanIn port, the output end of the two-input multiplexer under the control of a capture_clk signal is connected with the D input end of the capture trigger under the control of the capture_clk signal and a ScanOut port, the Q output end of the capture trigger under the control of the update_clk signal is connected with the second input end of the two-input multiplexer under the control of a mode signal, and the output end of the two-input multiplexer under the control of the mode signal is connected with the DataOut port; two-input multiplexers are additionally arranged on the basis of the traditional boundary scan register unit structure, and the capture_en signal and the update_en signal are respectively used as enabling ends of a capture trigger and an update trigger;
combining a two-input multiplexer under the control of a capture_en signal and a capture trigger under the control of a capture_clk signal to form a D trigger with an active low enable signal, or combining two-input multiplexers under the control of the capture_en signal and a shift_dr signal into a four-input multiplexer, thereby improving the structure of a traditional boundary scan register unit into a bc_2 unit;
the boundary scan chain circuit structure comprises three bc_2 units, wherein DI ports of the three bc_2 units are respectively connected with C ports of internal logic output multiplexing, OEN multiplexing and PAD, and DO ports of the three bc_2 units are respectively connected with I ports of the PAD, OEN ports of the PAD and internal logic input multiplexing;
after the simulation mode is started, test data sequentially enter a scanning chain through serial shifting of bc_2 units of each stage under the control of shift_dr signals and capture_en signals, and the captured test data are output from a data output port under the enabling of the update_en signals and the mode signals; under the condition that the value of the OEN port is 0, finishing the simulation of the output function;
Under the condition that the value of the OEN port is 1, the PAD port is assigned, the assignment is transmitted to the D1 input end of the third bc_2 unit through the C port of the PAD, then under the control of the capture_en signal and the shift_dr signal, the data in the capturing state are serially shifted out of the scanning chain through the ScanIn port and the ScanOut port of each stage bc_2 unit, the observation of the data at the output end of the PAD is realized, and the simulation of the input function is completed.
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