CN113284815B - Semiconductor device and trace misalignment detection method - Google Patents
Semiconductor device and trace misalignment detection method Download PDFInfo
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- CN113284815B CN113284815B CN202010101610.6A CN202010101610A CN113284815B CN 113284815 B CN113284815 B CN 113284815B CN 202010101610 A CN202010101610 A CN 202010101610A CN 113284815 B CN113284815 B CN 113284815B
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- 238000001514 detection method Methods 0.000 title claims abstract description 96
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000012360 testing method Methods 0.000 claims abstract description 173
- 230000002093 peripheral effect Effects 0.000 claims abstract description 91
- 239000000523 sample Substances 0.000 claims description 120
- 238000007689 inspection Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 238000006073 displacement reaction Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000013102 re-test Methods 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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Abstract
A semiconductor device includes a first test pad and a plurality of second test pads. The first test pad includes a central portion and a plurality of peripheral portions. The plurality of peripheral portions are disposed adjacent to the edges of the central portion. The peripheral portions are not in contact with each other and with the central portion. The first test pad has a plurality of detection orientations, and at least one peripheral portion is disposed on each detection orientation. Each second testing part is electrically connected with one of the plurality of peripheral parts through the first connecting wire.
Description
Technical Field
The present invention relates to a detection technology, and more particularly, to a semiconductor device capable of monitoring whether a probe set is offset in real time and a method for detecting the offset of a trace.
Background
It is known that a large number of integrated circuit chips can be fabricated on a single wafer, and that the wafer can be singulated through a singulation process to separate the integrated circuit chips for subsequent packaging and use. Generally, during the period from when the wafer has completed all the processes of the semiconductor to when it leaves the factory, a wafer acceptance test (Wafer Acceptable Test, WAT) is performed on the wafer to understand the electrical characteristics of the wafer, so as to determine whether the wafer has defects in the process. Thus, the quality and stability of the wafer to a certain extent can be ensured.
In wafer acceptance testing, a probe set (which may be referred to as a probe card) including a plurality of probes is typically used to contact test pads on a wafer to feed test signals to understand electrical characteristics within the wafer. However, slippage of the probe set may occur when it comes into contact with the test pad, and neither displacement of the tip of the probe set out of the test pad nor scraping out of the test pad is an undesirable test situation. Thus, there is a great need for related mechanisms that can monitor the needle down position of a probe set in real time to reduce test risk. Furthermore, due to the limited area available on the wafer, it is also desirable to save as much floor space as is needed for testing.
Disclosure of Invention
One embodiment of the present invention discloses a semiconductor device. The semiconductor device includes a first test pad and a plurality of second test pads. The first test pad includes a central portion and a plurality of peripheral portions. The plurality of peripheral portions are disposed adjacent to the edges of the central portion. The plurality of peripheral portions are not in contact with each other and the central portion. The first test pad has a plurality of detection orientations, and at least one peripheral portion is disposed on each detection orientation. Each second test pad is electrically connected with one of the plurality of peripheral portions through the first connecting wire.
An embodiment of the invention discloses a method for detecting needle mark deviation. The needle mark deviation detection method comprises the following steps: the method comprises the steps of utilizing a probe set to contact a semiconductor device, wherein the semiconductor device comprises a first test pad and a plurality of second test pads, the first test pad comprises a central part and a plurality of peripheral parts, the plurality of peripheral parts are arranged adjacent to the edge of the central part, the plurality of peripheral parts are not contacted with each other and are not contacted with the central part, the central part is provided with a plurality of detection orientations, at least one peripheral part is arranged on each detection orientation, each second test pad is electrically connected with one of the plurality of peripheral parts through a first connecting wire, the probe set comprises a first probe and a plurality of second probes, the first probe is used for contacting the first test pad, and the plurality of second probes are used for contacting the plurality of second test pads; outputting a test signal through the first probe; detecting whether the test signal is received or not by using a plurality of second probes respectively so as to obtain a plurality of detection states; and judging the needle-down position of the probe set according to the detection states.
Drawings
FIG. 1 is a schematic diagram of a detection system and a semiconductor device according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a semiconductor device and a probe set according to an embodiment of the invention.
FIG. 3 is a schematic diagram of an embodiment of a first test pad and a test orientation.
Fig. 4 is a schematic diagram of a semiconductor device according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a semiconductor device according to an embodiment of the invention.
Fig. 6 is a schematic diagram of a first test pad according to an embodiment of the invention.
Fig. 7 is a flowchart of a method for detecting a trace offset according to an embodiment of the invention.
FIG. 8 is a schematic diagram illustrating a schematic relation between detection states and judgment results of a plurality of second probes according to an example.
Reference numerals and signs
100 Semiconductor device
110 First test pad
111 Central portion
1121 To 1128 peripheral portion
121-128 Second test pad
131-137 First connecting wiring
141 Second connecting trace
200 Detection System
210 Probe set
211 First probe
2121 To 2127 second probe
A1 to A8 first configuration section
D1 setting direction
V1-V8 detection azimuth
S10-S40 steps
Detailed Description
The foregoing objects, features, and advantages of embodiments of the invention will be more readily apparent from the following detailed description taken in conjunction with the accompanying drawings.
Referring to fig. 1 and 2, a semiconductor device 100 includes a test pad set. The test pad set may include a plurality of test pads, and the plurality of test pads may be divided into a first test pad 110 and a plurality of second test pads. In the following, eight test pads are taken as an example, one of the test pads may be the first test pad 110, and seven test pads are the second test pads 121-127. However, the number of the test pads is not limited thereto. In one embodiment, the number of second test pads 121-127 required may depend on the number of peripheral portions of first test pad 110. In another embodiment, the number of the second test pads 121-127 may be greater than the number of the peripheral portions of the first test pad 110. In some embodiments, the semiconductor device 100 may be a wafer including a plurality of integrated circuit chips, and the first test pads 110 and the second test pads 121-127 may be disposed in scribe lines of the wafer, but the invention is not limited thereto.
The inspection system 200 may be used to perform electrical inspection of the semiconductor device 100, such as performing wafer acceptance testing (Wafer Acceptable Test, WAT). The inspection system 200 may include a probe set 210, and the inspection system 200 may be contacted with the semiconductor device 100 through the probe set 210 to perform electrical inspection. In one embodiment, the probe set 210 includes a first probe 211 and a plurality of second probes. Hereinafter, the number of the second probes 2121 to 2127 corresponding to the number of the second test pads 121 to 127 is also described as an example, but the number is not limited thereto.
The first probe 211 is configured to contact the first test pad 110, and each of the second probes 2121-2127 is configured to contact one of the second test pads 121-127. In addition, the first probe 211 and the second probes 2121-2127 of the probe set 210 are moved together such that when the first probe 211 contacts the first test pad 110, the second probes 2121-2127 also contact the second test pads 121-127. In this case, the inspection system 200 may vertically move down the probe set 210 or vertically raise the semiconductor device 100 to make the probe set 210 contact the semiconductor device 100.
It should be noted that, for clarity of illustration of the present invention, fig. 1 and 2 only show elements relevant to the present invention. It should be understood that the inspection system 200 and the semiconductor device 100 may also include other components for providing specific functions.
The first test pad 110 includes a central portion 111 and a plurality of peripheral portions 1121 to 1127. Hereinafter, the seven peripheral portions 1121 to 1127 will be mainly described as examples. The central portion 111 is located at the center of the contact surface when the contact surface of the first test pad 110 is viewed from a top view, and the central portion 111 has a certain area, so that the needle mark of the first probe 211 can be covered in the central portion 111 when the first probe 211 is poked at the center of the central portion 111. In some embodiments, when the tip of the first probe 211 is about 15 micrometers (μm), the trace of the first probe 211 may be about 15 micrometers to 20 micrometers, and the length and/or width of the central portion 111 may be about 20 micrometers to 30 micrometers, respectively, but the present invention is not limited thereto.
The plurality of peripheral portions 1121-1127 are disposed adjacent to the edge of the central portion 111 to collectively enclose the central portion 111. The peripheral portions 1121 to 1127 are spaced apart from each other so as not to be in direct contact with each other, and are electrically independent of each other. In addition, each of the peripheral portions 1121 through 1127 is also spaced from the central portion 111 so as not to directly contact the central portion 111.
Referring to fig. 2 and 3, the first test pad 110 may have a plurality of different test orientations. In some embodiments, the number of detection orientations may correspond to the number of sides of the central portion 111 of the first test pad 110. For example, in one embodiment, the central portion 111 of the first test pad 110 may be rectangular and have four sides, and the first test pad 110 may have four detection orientations V1-V4, which substantially correspond to the orientations of the four sides of the central portion 111, respectively. In another embodiment, the central portion 111 of the first test pad 110 may also have an octagonal shape, and the first test pad 110 may have eight detection orientations V1 to V8 corresponding to the orientations of eight sides of the central portion 111, respectively, as shown in fig. 3. However, the present invention is not limited thereto, and the number of the detecting orientations may not correspond to the number of sides of the central portion 111 of the first test pad 110. Furthermore, the shape of the central portion 111 is not limited thereto, and the central portion 111 may take any suitable shape.
In the following, eight detection orientations V1 to V8 will be described as examples. Here, the detection orientations V1 to V8 are horizontal orientations parallel to the contact surface. In addition, the first test pad 110 is provided with at least one peripheral portion at each of the detection orientations V1 to V8, so that the detection system 200 can determine the needle-down position of the probe set 210 according to which orientation the peripheral portion receiving the signal is located in during the detection described later.
The second test pads 121-127 are disposed adjacent to the first test pad 110. In addition, the semiconductor device 100 may further include a plurality of first connection wires. In the following, the number of the second test pads 121 to 127 is equal to seven, and the first connection traces 131 to 137 are also described as an example. Each of the second test pads 121 to 127 may be indirectly connected to one of the peripheral portions 1121 to 1127 through a corresponding one of the first connection traces 131 to 137, respectively, such that each of the second test pads 121 to 127 may be electrically connected to the corresponding peripheral portion 1121 to 1127, as shown in fig. 2.
In some embodiments, the size of the first test pad 110 (i.e. the entire outermost peripheral extent of the central portion 111 and the peripheral portions 1121-1127, i.e. the occupied area of the contact surface) may be substantially equal to the occupied area of the contact surface of each of the second test pads 121-127, but the invention is not limited thereto.
The detection system 200 can output a test signal through the first probe 211, and can detect whether the test signal can be received through the second probes 2121 to 2127, so as to determine the needle-down position of the probe set 210 according to a plurality of detection states of the plurality of second probes 2121 to 2127. Therefore, when the probe set 210 contacts the semiconductor device 100, if the probe set 210 slides so that the first probe 211 is not completely poked at the central portion 111 of the first test pad 110, for example, when the tip of the first probe 211 contacts at least one peripheral portion, the detection system 200 can receive the test signal through at least one corresponding second probe, and further determine that the needle-down position of the probe set 210 is shifted accordingly. Conversely, if the first probe 211 is completely poked at the central portion 111 of the first test pad 110, the detection system 200 can determine that the probe set 210 is not shifted due to the fact that the second probes 2121 to 2127 do not receive the test signal.
Referring to fig. 4 to 6, in some embodiments, the semiconductor device 100 may further include a second connection trace 141. The second connection trace 141 is connected between the central portion 111 of the first test pad 110 and one of the plurality of peripheral portions 1121-1127, such that the central portion 111 can be electrically connected to the corresponding peripheral portion through the second connection trace 141. For example, as shown in fig. 4, the second connection trace 141 may be connected between the peripheral portion 1124 and the central portion 111. In this way, if the first probe 211 is completely stuck on the central portion 111 of the first test pad 110 while the probe set 210 is in contact with the semiconductor device 100, the detection system 200 will only receive the test signal on the second probe 2112, thereby further determining that the probe set 210 is not deflected, rather than the probe set 210 is not in contact with the first test pad 110 and the second test pads 121-127. Hereinafter, the first connection pad 110 provided with the second connection trace 141 will be mainly described.
In some embodiments, the first test pad 110 (i.e., the central portion 111 and the peripheral portions 1121-1127), the second test pads 121-127, the first connecting traces 131-137 and the second connecting traces 141 can be fabricated by the same metal layer (e.g., the M0 layer, the TV layer, etc.) through the wafer manufacturing process, such as photolithography, etching, etc., so that the semiconductor device 100 of any embodiment of the present invention is simpler and more convenient than conventional one.
The first test pad 110 and the second test pads 121 to 127 of the semiconductor device 100 may be disposed at intervals along the same disposing direction D1 so as to be substantially aligned in the same linear direction. In some embodiments, the first test pad 110 may be located between the second test pads 121-127 to facilitate the arrangement of the peripheral portion and/or to save the area of the connection traces connected to the peripheral portion. For example, the first test pad 110 may be located approximately in the middle of the second test pads 121-127. However, the present invention is not limited thereto, and in other embodiments, the first test pad 110 and the second test pads 121-127 may be arranged in any order, as long as the first connection wires 131-137 may be connected to the peripheral portions 1121-1127 of the first test pad 110 and the second test pads 121-127. The first probe 211 and the second probes 2121 to 2127 of the probe set 210 may be arranged substantially on the same line at intervals along the mounting direction D1.
In some embodiments, each peripheral portion 1121-1127 of the first test pad 110 may extend along an edge of the central portion 111 to encompass at least two detection orientations. For example, as shown in FIG. 4, the peripheral portion 1121 may cover the detection orientations V1, V2, the peripheral portion 1122 may cover the detection orientations V2, V3, and so on.
In other embodiments, as shown in fig. 5, each peripheral portion of the first test pad 110 may further cover at least two test orientations in a sequential coverage manner. Here, the first test pad 110 may be configured with eight peripheral portions 1121 to 1128, and the semiconductor device 100 may be correspondingly configured with eight second test pads 121 to 128. As shown, the peripheral portion 1121 may cover the detection orientations V1, V2, the peripheral portion 1122 may cover the detection orientations V2, V3, and so on, the peripheral portion 1128 may cover the detection orientations V8, V1.
In another embodiment, where the peripheral portions 1121-1128 sequentially cover three detection orientations, as shown in FIG. 6, the peripheral portion 1121 may cover detection orientations V8, V1, V2, the peripheral portion 1122 may cover detection orientations V1-V3, and so on.
It should be noted that, no matter whether each of the peripheral portions 1121-1128 sequentially covers two or three inspection orientations, or even eight inspection orientations, the first test pad 110 still only needs to divide the eight peripheral portions 1121-1128, and the semiconductor device 100 still only needs to configure eight second test pads 121-128. Therefore, the arrangement area required for performing offset detection can be greatly reduced.
In some embodiments, referring to FIG. 6, each peripheral portion 1121-1128 covering at least two detection orientations may include a first configuration segment. The first arrangement sections A1 to A8 of the peripheral portions 1121 to 1128 are provided in one of the detection orientations V1 to V8, respectively, and the other peripheral portion is not provided between each of the first arrangement sections A1 to A8 and the central portion 111. In this way, the peripheral portions 1121 to 1128 can surround the central portion 111 in a staggered manner.
In some embodiments, the plurality of test orientations V1-V8 of the first test pad 110 can be divided into a high probability test orientation and a low probability test orientation. The high probability detection orientation refers to an orientation that is more often shifted when the probe set 210 slides. Moreover, the first test pad 110 may be configured with at least two peripheral portions in the high probability of detecting orientation, such that the detecting system 200 may further divide the degree of offset of the probe set 210 in the Gao Jilv detecting orientation.
Referring to fig. 3, for example, since the probe set 210 is less shifted downward (such as the detection direction V5 in fig. 3) when the probe set is dropped, in some embodiments, only one peripheral portion 1123, 1124 may be disposed on the detection directions V4, V5, respectively, while two peripheral portions are disposed on the other detection directions.
The inspection system 200 can perform the trace offset inspection method according to any of the embodiments of the present invention to monitor the needle-down position of the probe set 210 on the semiconductor device 100 in real time.
Fig. 7 is a flowchart of a method for detecting a trace offset according to an embodiment of the invention. Referring to fig. 7, in an embodiment of the trace offset detection method, the detection system 200 may first contact the first test pad 110 and the second test pad 121' 127 of the semiconductor device 100 by using the probe set 210 (step S10). Then, the detection system 200 outputs a test signal through the first probes 211 in the probe set 210 (step S20), and performs detection by using the second probes 2121 to 2127 in the probe set 210 to obtain a plurality of detection states of the second probes 2121 to 2127 (step S30). Then, the detection system 200 can rapidly determine the needle-down position of the probe set 210 according to the plurality of detection states obtained in step S30 (step S40). Wherein the needle down position includes a needle down direction (also may be referred to as an offset direction) and/or an offset.
In an embodiment of step S40, the detection system 200 may determine the needle-down position of the probe set 210 according to at least one detection state indicated as receiving the test signal.
In the following, several examples are described to determine how the detection system 200 performs the determination. In one example, when the first probe 211 contacts the central portion 111 and the peripheral portion 1121 shown in fig. 4, the second probe 2122 contacting the second test pad 122 and the second probe 2125 contacting the second test pad 125 receive the test signal. Thus, the detection system 200 can determine that the probe set 210 is shifted toward the detection orientation V1. Moreover, since the second probes 2126 contacting the second test pads 126 do not receive the test signal, which indicates that the probe set 210 is shifted toward the testing direction V1 but not beyond the contact surface of the first test pad 110, the testing system 200 can determine that the probe set 210 is only slightly shifted toward the testing direction V1. Further, the detection system 200 may even calculate the offset of the probe set 210 based on a known distance (e.g., herein, the distance between the peripheral portion 1121 and the central portion 111) and the width of the peripheral portion 1121, and correct accordingly. For example, the probe set 210 is moved by the calculated offset amount toward the detection azimuth V5 opposite to the detection azimuth V1.
In one example, when the first probe 211 contacts the central portion 111, the peripheral portion 1121, and the peripheral portion 1127 shown in fig. 4, the second probe 2122 contacting the second test pad 122, the second probe 2125 contacting the second test pad 125, and the second probe 2126 contacting the second test pad 126 receive the test signal. Thus, the detection system 200 can determine that the probe set 210 is shifted toward the detection orientation V1. Moreover, since the second probes 2125, 2126 coupled to the peripheral portions 1121, 1127 at the detection position V1 and the second probe 2122 coupled to the central portion 111 can both receive the test signal, which indicates that the probe set 210 is shifted to the edge of the test pad (i.e., the first test pad 110 and the second test pads 121-127) toward the detection position V1, the detection system 200 can determine that the probe set 210 is shifted to the edge of the test pad toward the detection position V1. Similarly, the detection system 200 may calculate the offset of the probe set 210 based on a known distance (for example, the distance between the peripheral portion 1121 and the central portion 111 and the distance between the peripheral portion 1121 and the peripheral portion 1127), the width of the peripheral portion 1121 and the width of the peripheral portion 1127, and the like, and correct the offset accordingly.
In one example, when the first probe 211 contacts the peripheral portion 1121 and the peripheral portion 1127 shown in fig. 4, the second probe 2125 contacting the second test pad 125 and the second probe 2126 contacting the second test pad 126 receive the test signal. Thus, the detection system 200 can determine that the probe set 210 is shifted toward the detection orientation V1. Moreover, since the second probe 2122 coupled to the central portion 111 does not receive the test signal, which indicates that the probe set 210 is severely shifted toward the testing direction V1 (or, when there is only the test signal of the second probe 2126 coupled to the second test pad 126, the probe set 210 is also severely shifted toward the testing direction V1), the testing system 200 can determine that the probe set 210 is shifted toward the testing direction V1 and is completely punched out of the test pad. Similarly, the detection system 200 can calculate the offset of the probe set 210 and correct accordingly.
Since the determination of the offset of the detection system 200 in the other detection directions V2 to V8 is substantially the same as the determination of the offset in the detection direction V1, those skilled in the art should understand and know how to make corresponding changes, and thus the description thereof is omitted herein.
FIG. 8 is a schematic diagram illustrating a schematic relation between detection states and judgment results of a plurality of second probes according to an example. Referring to fig. 2 and 8, after the inspection system 200 inspects the semiconductor device 100 of the embodiment shown in fig. 2, an example of a plurality of possible inspection states and corresponding determination results thereof may be shown in the relationship diagram of fig. 8. Wherein, the sign very good indicates that the detection state of the second probe is that the test signal is received.
In summary, the embodiments of the invention provide a semiconductor device and a trace offset detection method, in which a central portion of a first test pad is divided and a plurality of peripheral portions of the central portion are staggered and surrounded, so that a test signal is output by a first probe during detection, and a needle-down position of a probe set is rapidly detected according to a combination result of a plurality of detection states of a plurality of second probes. Furthermore, the semiconductor device and the trace offset detection method according to the embodiment of the invention can monitor on line in real time, so that the measurement quality can be ensured and the retest rate can be reduced. In addition, the semiconductor device and the trace offset detection method of the embodiment of the invention can greatly reduce the number and the occupied area of the second test pads of the required stay wires and simplify the process complexity.
The present invention is not limited to the above embodiments, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the embodiments of the invention, and the scope of the invention is defined by the appended claims.
Claims (10)
1. A semiconductor device, the device comprising:
the first test pad comprises a central part and a plurality of peripheral parts, wherein the peripheral parts are arranged adjacent to the edge of the central part, and are not contacted with each other and are electrically independent of each other; and
A plurality of second test pads, each of which is electrically connected with one of the peripheral portions through a first connection trace, the first test pad and the second test pads are arranged along a setting direction, and the first test pad is arranged between the second test pads;
The detection orientations comprise a plurality of high-probability detection orientations and at least one low-probability detection orientation, and the number of the peripheral parts arranged on the low-probability detection orientations is smaller than that of the peripheral parts arranged on the high-probability detection orientations.
2. The semiconductor device of claim 1, wherein each of the peripheral portions extends along the edge of the central portion to encompass at least two of the inspection orientations.
3. The semiconductor device of claim 2, wherein each of the peripheral portions includes a first arrangement section, the first arrangement section of each of the peripheral portions being located on one of the plurality of inspection orientations, and there being no other peripheral portion between the first arrangement section of each of the peripheral portions and the central portion.
4. The semiconductor device according to claim 1, wherein at least two of the peripheral portions are provided in each of the high probability detection orientations.
5. The semiconductor device of claim 1, wherein the central portion is further electrically connected to one of the peripheral portions by a second connection trace for electrically connecting to one of the second test pads.
6. The semiconductor device of claim 1, wherein the contact surface of the first test pad occupies the same range as the contact surface of each of the second test pads.
7. The semiconductor device of claim 1, wherein the first test pad, the second test pads and the first connection traces are formed by the same metal layer.
8. A method for detecting needle mark displacement, the method comprising:
A probe set is utilized to contact a semiconductor device, wherein the semiconductor device comprises a first test pad and a plurality of second test pads, the first test pad and the second test pad are arranged along a setting direction, the first test pad is arranged between the second test pads, the first test pad comprises a central part and a plurality of peripheral parts, the peripheral parts are arranged adjacent to the edge of the central part, the peripheral parts are not contacted with each other and are electrically independent from each other, the first test pad is provided with a plurality of detection orientations, at least one peripheral part is arranged on each detection orientation, the detection orientations comprise a plurality of high-probability detection orientations and at least one low-probability detection orientation, the number of the peripheral parts arranged on the low-probability detection orientations is smaller than the number of the peripheral parts arranged on the high-probability detection orientations, each second test pad is electrically connected with one of the peripheral parts through a first connecting wire, the probe set comprises a first probe and a plurality of second probes, the first probe is used for contacting the first test pad, and the second probe is used for contacting the second test pad;
outputting a test signal through the first probe;
Detecting by using the second probes to obtain a plurality of detection states; and
And judging the needle-down position of the probe set according to the detection states.
9. The method of claim 8, wherein determining the needle down position of the probe set determines the needle down position of the probe set based on at least one of the detection states indicated as receiving the test signal.
10. The method of claim 8, wherein each of the peripheral portions extends along the edge of the central portion to cover at least two of the detecting orientations.
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| JP2015015441A (en) * | 2013-07-08 | 2015-01-22 | 富士通セミコンダクター株式会社 | Semiconductor device, and method of detecting probe position relative to inspecting pad of semiconductor device |
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| JPH06216214A (en) * | 1993-01-12 | 1994-08-05 | Fujitsu Ltd | Package testing method, package alignment method, probe contact condition discrimination device and brazing device |
| JPH09107011A (en) * | 1995-10-11 | 1997-04-22 | Sharp Corp | Semiconductor device and aligning method thereof |
| JPH10223710A (en) * | 1997-02-03 | 1998-08-21 | Mitsubishi Electric Corp | Semiconductor integrated circuit device and testing method thereof |
| JP2007335550A (en) * | 2006-06-14 | 2007-12-27 | Seiko Instruments Inc | Semiconductor device |
| KR20090050416A (en) * | 2007-11-15 | 2009-05-20 | 삼성전자주식회사 | Test structure |
| US7759955B2 (en) * | 2007-12-21 | 2010-07-20 | Infineon Technologies Ag | Method and device for position detection using connection pads |
| TWI394221B (en) * | 2009-04-30 | 2013-04-21 | Advanced Semiconductor Eng | Silicon wafer having a testing pad and method for testing the same |
| CN106024739A (en) * | 2016-05-13 | 2016-10-12 | 上海华力微电子有限公司 | Metallic pad device and test system and method using same |
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