CN110808737A - Digital correction method for delay chain circuit of asynchronous SAR-ADC - Google Patents

Abstract

The invention discloses a digital correction method for a delay chain circuit of an asynchronous SAR-ADC (synthetic aperture radar-analog converter). an internal Clear signal Clear of the asynchronous SAR-ADC samples a Ready signal through two D flip-flops connected in series to obtain a correction bit CAL; the Ready signal is a clock signal generated by XOR of two differential outputs of a comparator in the asynchronous SAR-ADC; according to sampling clock CLK output by clock generation circuit in asynchronous SAR-ADC_sampleThe selection control word TDC is output to the multiplexer of the delay chain circuit by determining the level of the correction enable signal CAL _ EN and determining the state of the correction bit CAL. The invention can realize the maximization of the delay time.

Description

Digital correction method for delay chain circuit of asynchronous SAR-ADC

Technical Field

The invention relates to the field of data conversion integrated circuits, in particular to a digital correction method for a delay chain circuit of an asynchronous SAR-ADC.

Background

The successive approximation analog-digital converter (SAR-ADC) has the characteristics of simple structure, low power consumption, small area, easiness in integration and the like, and is widely applied to the field of medium-precision (8-16 bits) and medium-speed (<150 Msps).

The clock control of the conventional SAR-ADC is a synchronous mode, namely, one clock is externally accessed, and each step of sampling, converting, storing and outputting in a chip is defined by the external clock. The accuracy of the external clock is matched to the sampling accuracy of the SAR-ADC. This accuracy is quite high for the clock source required for high speed high resolution SAR-ADCs. Besides the need to ensure the purity of the clock source, great care must be taken to the noise from the clock to each link inside the chip. Furthermore, such high clock frequency requires strong driving capability of logic gates within the chip, which means large power consumption.

Asynchronous clocking is the most important system-level solution for SAR-ADC speed up in recent years. The SAR-ADC has some characteristics, such as high clock precision requirement of sampling, but almost no clock precision requirement of conversion, and just provides a space for exerting advantages for an asynchronous clock. The pulse required by the control circuit is generated by itself, and the asynchronous clock control abandons the frequency division operation of a synchronous clock, but adopts an external clock with the same sampling frequency to divide the clock into two stages of sampling and conversion. The system only has requirements on the operation sequence during conversion, and has no requirements on the clock edge, so that the conversion is made into asynchronous trigger, the comparator is used for triggering the SAR logic, and the SAR logic drives the DAC to complete N times of comparison. And finally outputting results of N data which are sequentially finished but not aligned with the clock in a synchronous mode.

The basic structure of an asynchronous SAR-ADC is shown in FIG. 2, where an external clock signal generates a sampling clock CLK via a clock generation circuit_sample. After sampling the input differential signals INP and INN by the sampling clock, comparing the input differential signals by a high-speed comparator, generating a Ready signal through exclusive OR, inputting the Ready signal into a multi-phase clock generating circuit and a successive approximation logic circuit, generating a clock signal to provide a comparison clock for the comparator through delay chain delay on one hand, and controlling a switched capacitor Array (digital-analog conversion Array, DAC Array) of the SAR-ADC through a DAC control circuit on the other hand. The clock generating circuit also generates a Clear signal Clear in order to Clear the circuit after each signal comparison is completed, thereby preventing charge accumulation. A reference voltage of DAC (digital-to-analog conversion) is generated by an external reference source (BG) through a reference voltage buffer (VREF BUF). The delay loop of the whole asynchronous SAR-ADC is composed of a comparator, an exclusive-OR gate, a multi-phase clock generation circuit and a delay chain. Since the delays of the other circuits are substantially fixed, the adjustment of the delay chain delay time becomes the only controllable factor.

A conventional asynchronous SAR-ADC delay control circuit is shown in fig. 3, where VIN is used as the input signal of the delay chain. The multiplexer (muxnx 1) selects one path from the taps of the N DELAY units (DELAY) as the output signal VOUT. Due to variations in delay time of the delay chain with process corner, voltage and temperature (PVT), the delay time varies by even more than a factor of two under different PVT variations. The larger delay time can increase the settling time of the DAC, thereby improving the overall performance of the ADC, but may cause the loss of the last several comparison pulses of the ADC, which affects the yield of the ADC in mass production. Smaller delay times can cause poor performance of the ADC.

Disclosure of Invention

The invention aims to provide a digital correction method for a delay chain circuit of an asynchronous SAR-ADC (synthetic aperture radar-analog converter), which can realize the maximization of delay time.

The technical scheme for realizing the purpose is as follows:

a digital correction method for a delay chain circuit of an asynchronous SAR-ADC, the delay chain circuit comprising:

receiving an input signal VIN, and forming a delay chain by cascading N stages of delay units; n is more than or equal to 2 and is a positive integer; and

the multiplexer is respectively connected with the output end of each delay unit in the delay chain;

the digital correction method comprises the following steps:

step S1, sampling the Ready signal by the internal Clear signal Clear of the asynchronous SAR-ADC through two serially connected D triggers to obtain a correction bit CAL; the Ready signal is a clock signal generated by XOR of two differential outputs of a comparator in the asynchronous SAR-ADC;

step S2, according to the sampling clock CLK outputted by the clock generating circuit in the asynchronous SAR-ADC_sampleThe selection control word TDC is output to the multiplexer by determining the level of the correction enable signal CAL _ EN and determining the state of the correction bit CAL.

Preferably, the step S2 includes:

after the asynchronous SAR-ADC is electrified, judging whether a correction enabling signal CAL _ EN is in a high level, if not, setting a selected control word TDC to be a maximum bit NMAX, and finishing correction; if yes, entering the next step;

setting a selection control word TDC as a maximum bit NMAX, wherein i is 0;

judging whether the correction bit CAL is 1, if so, setting i to be i +1, selecting the control word TDC to be NMAX-i, and judging whether the correction bit CAL is 1 again; if not, setting the selection control word TDC to be NMAX-i-1, and entering the next step;

judging whether the correction enable signal CAL _ EN is in a high level or not, and if not, finishing correction; if yes, whether the calibration bit CAL is 1 is determined again.

Preferably, the asynchronous SAR-ADC comprises a clock generation circuit, a digital-analog conversion array and a comparator;

the clock generation circuit receives an external clock signal and outputs a sampling clock CLK_sampleAnd an internal Clear signal Clear;

the sampling clock CLK_sampleAfter sampling the input differential signals INP, INN with a digital-to-analog conversion array, the signals are compared by the comparator, and a Ready signal is generated by an exclusive or.

The invention has the beneficial effects that: according to the invention, after the circuit is powered on, the delay unit of the delay chain is controlled by using the ADC internal signal to realize the maximization of the delay time, and the variation of the comparison clock period generated by the asynchronous SAR-ADC delay loop along with the process angle, the voltage and the temperature (PVT) is reduced. Therefore, in a large-scale mass-produced chip, the conversion time of the asynchronous sar ADC can be kept substantially unchanged, thereby leaving sufficient margin for the settling time (settling time) of the capacitive digital-to-analog conversion array in the ADC. The invention can improve the working speed of the asynchronous SAR-ADC and improve the linearity and the signal-to-noise ratio of the ADC. Under a CMOS process platform, the high-speed asynchronous SAR-ADC integrated in a chip is realized, and the performance and yield of a mass production chip are improved.

Drawings

FIG. 1 is a schematic diagram of the digital correction method of the present invention for the delay chain circuit of an asynchronous SAR-ADC;

FIG. 2 is a schematic diagram of the basic structure of a conventional asynchronous SAR-ADC;

FIG. 3 is a circuit diagram of a prior art delay chain circuit of an asynchronous SAR-ADC;

FIG. 4 is a flow chart of digital calibration according to the present invention;

FIG. 5 is a normal timing diagram of the digitally corrected asynchronous SAR-ADC of the present invention;

fig. 6 is a timing diagram of the digital correction asynchronous SAR-ADC of the present invention when an abnormality occurs.

Detailed Description

The invention will be further explained with reference to the drawings.

As can be seen from fig. 3, the delay chain circuit includes: receiving an input signal VIN, and forming a DELAY chain by cascading N stages of DELAY units (DELAY); n is more than or equal to 2 and is a positive integer; and the multiplexers are respectively connected with the output ends of all the delay units in the delay chain. The multiplexer selects one path from the taps of the N delay units as the output voltage VOUT. The multiplexer is controlled by a selection control word TDC.

As can be seen in fig. 2, the asynchronous SAR-ADC includes a clock generation circuit, a digital-to-analog conversion Array (DAC Array), and a comparator. The clock generation circuit receives an external clock signal and outputs a sampling clock CLK_sampleAnd an internal Clear signal Clear. Sampling clock CLK_sampleAfter sampling the input differential signals INP, INN with a digital-to-analog conversion array, the signals are compared by the comparator, and a Ready signal is generated by an exclusive or.

Referring to fig. 1, the digital calibration method for the delay chain circuit of the asynchronous SAR-ADC of the present invention includes the following steps:

step S1, sampling the Ready signal by an internal Clear signal Clear of the asynchronous SAR-ADC through two D triggers (DFFs) connected in series to obtain a correction bit CAL; the Ready signal is a clock signal generated by XOR of two differential outputs of a comparator in the asynchronous SAR-ADC;

step S2, implementing digital control: according to sampling clock CLK output by clock generation circuit in asynchronous SAR-ADC_sampleThe selection control word TDC is output to the multiplexer by determining the level of the correction enable signal CAL _ EN and determining the state of the correction bit CAL. Thereby maximizing delay time without losing useful information. Specifically, referring to fig. 4, step S2 includes the following steps:

1) after the asynchronous SAR-ADC is electrified, judging whether a correction enabling signal CAL _ EN is in a high level, if not, setting a selected control word TDC to be a maximum bit NMAX, and finishing correction; if yes, entering the next step;

2) setting a selection control word TDC as a maximum bit NMAX, wherein i is 0;

3) judging whether the correction bit CAL is 1, if so, setting i to be i +1, selecting the control word TDC to be NMAX-i, and judging whether the correction bit CAL is 1 again; if not, setting the selection control word TDC to be NMAX-i-1, and entering the next step;

4) judging whether the correction enable signal CAL _ EN is in a high level or not, and if not, finishing correction; if yes, whether the calibration bit CAL is 1 is determined again.

FIG. 5 is a digitally corrected asynchronous SAR-ADC normal timing. In the figure, CLK_sampleIs the sampling clock of the asynchronous SAR-ADC; READY is a clock signal generated by XOR of two differential outputs of the asynchronous SAR-ADC comparator; CLEAR is the CLEAR signal after the end of each comparison period of the asynchronous SAR-ADC. When the asynchronous SAR-ADC works normally, the CLEAR signal occurs after READY is completed, so that the CAL signal generated by CLEAR sampling READY through DFF is in a low level. Tsample represents the sampling time of the ADC.

Fig. 6 is a timing chart when an abnormality occurs in the digitally corrected asynchronous SAR-ADC. When the asynchronous SAR-ADC works abnormally. The CLEAR signal occurs before READY ends, so that the CAL signal generated by CLEAR sampling READY through DFF is at high level, and the READY signal loses useful pulses because the SAR-ADC enters a sampling stage. This phenomenon must be avoided by digital correction.

The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and therefore all equivalent technical solutions should also fall within the scope of the present invention, and should be defined by the claims.

Claims (3)

1. A digital correction method for a delay chain circuit of an asynchronous SAR-ADC, the delay chain circuit comprising:

receiving an input signal VIN, and forming a delay chain by cascading N stages of delay units; n is more than or equal to 2 and is a positive integer; and

the multiplexer is respectively connected with the output end of each delay unit in the delay chain;

the digital correction method is characterized by comprising the following steps:

step S1, sampling the Ready signal by the internal Clear signal Clear of the asynchronous SAR-ADC through two serially connected D triggers to obtain a correction bit CAL; the Ready signal is a clock signal generated by XOR of two differential outputs of a comparator in the asynchronous SAR-ADC;

step S2, according to the sampling clock CLK outputted by the clock generating circuit in the asynchronous SAR-ADC_sampleThe selection control word TDC is output to the multiplexer by determining the level of the correction enable signal CAL _ EN and determining the state of the correction bit CAL.

2. The digital correction method for the delay chain circuit of the asynchronous SAR-ADC according to claim 1, wherein said step S2 comprises:

after the asynchronous SAR-ADC is electrified, judging whether a correction enabling signal CAL _ EN is in a high level, if not, setting a selected control word TDC to be a maximum bit NMAX, and finishing correction; if yes, entering the next step;

setting a selection control word TDC as a maximum bit NMAX, wherein i is 0;

judging whether the correction bit CAL is 1, if so, setting i to be i +1, selecting the control word TDC to be NMAX-i, and judging whether the correction bit CAL is 1 again; if not, setting the selection control word TDC to be NMAX-i-1, and entering the next step;

judging whether the correction enable signal CAL _ EN is in a high level or not, and if not, finishing correction; if yes, whether the calibration bit CAL is 1 is determined again.

3. The digital correction method for the delay chain circuit of the asynchronous SAR-ADC according to claim 1, wherein the asynchronous SAR-ADC comprises a clock generation circuit, a digital-to-analog conversion array and a comparator;

the clock generation circuit receives an external clock signalOutputs a sampling clock CLK_sampleAnd an internal Clear signal Clear;

the sampling clock CLK_sampleAfter sampling the input differential signals INP, INN with a digital-to-analog conversion array, the signals are compared by the comparator, and a Ready signal is generated by an exclusive or.

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