CN110534577B - Thin film transistor and preparation method thereof - Google Patents

Thin film transistor and preparation method thereof Download PDF

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CN110534577B
CN110534577B CN201910739513.7A CN201910739513A CN110534577B CN 110534577 B CN110534577 B CN 110534577B CN 201910739513 A CN201910739513 A CN 201910739513A CN 110534577 B CN110534577 B CN 110534577B
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electrode
active layer
insulating layer
layer
thin film
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CN110534577A (en
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陈宇怀
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

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Abstract

The transistor comprises a substrate and a bottom grid electrode arranged on the substrate, wherein an active layer is further arranged above the bottom grid electrode, the active layer comprises a part which is arranged in parallel with one side surface of the bottom grid electrode, and the other side of the part, opposite to the side surface of the bottom grid electrode, of the active layer is further provided with a top grid electrode. Compared with the planar thin film transistor, compared with the prior art, the method can shorten the size (Critical Dimension, CD) of the channel system Cheng Linjie of the thin film transistor, thereby reducing the occupied area of the whole device and improving the PPI of the panel; and the vertical structure thin film transistor with the double gate structure has higher electron mobility and device stability.

Description

Thin film transistor and preparation method thereof
Technical Field
The invention relates to a new TFT design, in particular to an optimized design of a thin film transistor with a vertical structure.
Background
With the development of active matrix organic light emitting diode displays (AMOLED) and high performance Active Matrix Liquid Crystal Displays (AMLCD), TFTs are generally required to have higher current-voltage driving capability in order to obtain high resolution and high frame rate displays, and thus how to design and manufacture high performance and small size thin film transistors becomes an increasingly required research topic.
IGZO is an amorphous oxide containing indium, gallium and zinc, the carrier mobility is 20-30 times of that of amorphous silicon, the charge and discharge rate of TFT to pixel electrode can be greatly improved, the response speed of pixel is improved, the panel refresh frequency is faster, and the ultra-high resolution TFT-LCD can be realized. Meanwhile, the existing amorphous silicon production line can be compatible with an IGZO process by only slightly changing, so that the low-temperature polysilicon (LTPS) has more competitiveness in the aspect of cost.
The mobility of the oxide semiconductor (10-30 cm < 2 >/V.s) can meet the driving requirement of the AMOLED display array substrate, the IGZO TFT device has more excellent Ioff than a low-temperature polysilicon TFT, and the pixel TFT can inhibit the leakage problem by only needing a single grid electrode, thereby being beneficial to the miniaturization of the TFT device and realizing the manufacture of the ultra-high resolution TFT substrate. Therefore, the high-resolution OLED display matched with the IGZO TFT driving circuit has good market prospect, and is a research and development hot spot for main panel factories at home and abroad at present.
Compared with a planar thin film transistor, the size (Critical Dimension, CD) of the thin film transistor channel structure Cheng Linjie can be shortened, so that the occupied area of the whole device is reduced, and the PPI of the panel is improved. The vertical structure TFT can reduce the device area, but the electron mobility and the device stability of the structure still need to be further improved in view of the existing process debugging situation. Compared with the traditional single gate, the double gate TFT device has better electrical stability and stronger gate control capability, the threshold voltage drift amount caused by negative voltage bias or positive voltage bias of the double gate IGZO TFT is smaller than that of the Shan Shan IGZO TFT, and compared with a single gate structure, the current driving capability of the double gate device is obviously improved.
Disclosure of Invention
Therefore, it is desirable to provide a thin film transistor and a display structure incorporating the same, which can reduce the size (Critical Dimension, CD) of the channel structure Cheng Linjie of the thin film transistor compared to a planar thin film transistor, thereby reducing the overall device footprint and improving the PPI of the panel.
In order to achieve the above object, the present inventors provide a thin film transistor, including a substrate, and a bottom gate electrode disposed on the substrate, wherein an active layer is further disposed above the bottom gate electrode, the active layer includes a portion disposed parallel to one side of the bottom gate electrode, and the other side of the portion of the active layer opposite to the side of the bottom gate electrode is further disposed with a top gate electrode.
Further, the semiconductor device further comprises a first electrode, wherein the first electrode is arranged above the substrate and below the bottom grid electrode, and the active layer is in contact with the first electrode.
Further, the semiconductor device further comprises a second electrode, wherein the second electrode is arranged above the active layer and is in contact with the active layer.
Specifically, a first insulating layer is arranged between the first electrode and the bottom gate electrode.
Specifically, a second insulating layer is arranged between the bottom gate and the active layer, and a third insulating layer is arranged between the active layer and the top gate.
A thin film transistor manufacturing method includes the steps of patterning a bottom gate metal layer, disposing a second insulating layer mask on the bottom gate metal layer, patterning an active layer on the second insulating layer such that the active layer includes at least a portion disposed parallel to one side of the bottom gate, disposing a third insulating layer on the portion, and patterning a top gate on the third insulating layer such that the top gate is disposed on the other side of the portion of the active layer opposite to the side of the bottom gate.
Specifically, the method further comprises the steps of arranging a first electrode on the substrate, arranging a first insulating layer on the first electrode, and arranging a bottom gate metal layer on the first insulating layer; and after the second insulating layer mask is arranged, etching the second insulating layer and the first insulating layer to obtain a via hole, exposing the first electrode, and patterning the active layer on the second insulating layer to enable the active layer to be in contact with the first electrode.
Specifically, the method further comprises the step of patterning the top gate on the third insulating layer, specifically, providing a metal layer on the third insulating layer, patterning the metal layer to form the top gate, and patterning the metal layer to form a second electrode, wherein the second electrode is in contact with the active layer.
Compared with the planar thin film transistor, compared with the prior art, the method can shorten the size (Critical Dimension, CD) of the channel system Cheng Linjie of the thin film transistor, thereby reducing the occupied area of the whole device and improving the PPI of the panel; and the vertical structure thin film transistor with the double gate structure has higher electron mobility and device stability.
Drawings
FIG. 1 is a schematic view of a TFT according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a TFT channel according to an embodiment of the invention;
FIG. 3 is a schematic view of a TFT manufacturing process according to an embodiment of the invention;
FIG. 4 is a schematic illustration of a continuous film formation according to an embodiment of the present invention;
FIG. 5 is a schematic illustration of two metal film forming according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a dual gate scan line according to an embodiment of the present invention;
fig. 7 is a view of an OLED display panel with a vertical thin film transistor according to an embodiment of the present invention.
Detailed Description
In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.
Fig. 1 shows a schematic view of a thin film transistor and an OLED panel thereon according to the present invention, in which a thin film transistor with a vertical structure is referred to as a transistor structure in which an active layer channel is formed by a side surface of a gate electrode, and some of the vertical structures in the prior art are simplified to be "" structures on the outer side of the gate electrode, which is also the origin of the name of the vertical structures. Fig. 2 illustrates the benefits of a vertical structure, and it can be seen that the active layer can actually be at an oblique angle ranging from 30 ° to 90 °, and that a true design that is completely vertical is detrimental to the stability of the structure, and also inconvenient to pattern the active layer. As can be seen from fig. 2, since the active layer is mainly attached to the side wall of the bottom gate, at least one side surface of the bottom gate forms an inclination angle α with the bottom surface in the view of the screen capturing, and the cross section of the bottom gate may be isosceles trapezoid, right trapezoid, irregular polygon, triangle, etc. in view of the practical effect of shortening the channel length and the adhesiveness of the active layer. In this embodiment, the bottom gate tilt angle α is controlled to be between 30 ° and 90 °, and specific values will be defined according to actual design requirements and process capability. Due to the inclination angle, the actual channel occupation length of the active layer can be greatly reduced. In our design, please refer back to fig. 1 here, the device includes a substrate, a bottom gate disposed on the substrate, an active layer disposed above the bottom gate, the active layer including a portion disposed parallel to one side of the bottom gate, and a top gate disposed on the other side of the portion of the active layer opposite to the side of the bottom gate. By means of the design of the double gates, the top gate is arranged on the part, opposite to the side face of the bottom gate, of the active layer, so that the transistor has higher electron mobility and device stability, and the area of the device can be further reduced.
The active layer material of the present invention preferably adopts a metal oxide such as IGZO, IZO, IGZTO, but is not limited thereto, and semiconductor materials such as organic semiconductors and carbon nanotubes may be used as the active layer of the TFT of the present invention. The metal film layer, the organic insulating layer, the inorganic insulating layer and the semiconductor layer are not limited by special materials.
In a further embodiment as shown in fig. 1, a first electrode is further included, the first electrode being disposed above the substrate and below the bottom gate, the active layer being in contact with the first electrode. The first electrode is a metal electrode, and is produced by etching a metal layer. The semiconductor device further comprises a second electrode, wherein the second electrode is arranged above the active layer and is in contact with the active layer. The first electrode and the second electrode can be respectively arranged as a source electrode and a drain electrode, thereby achieving the technical effect of transistor construction.
In some other specific embodiments, a first insulating layer is disposed between the first electrode and the bottom gate. Specifically, a second insulating layer is arranged between the bottom gate and the active layer, and a third insulating layer is arranged between the active layer and the top gate. By constructing the insulating layer, the double gate and the active layer can work normally.
In the embodiment shown in fig. 3, we also introduce a method for manufacturing a thin film transistor, comprising the steps of,
s3: patterning the bottom gate metal layer, s4: disposing a second insulating layer mask on the bottom gate metal layer, s5: patterning the active layer on the second insulating layer such that the active layer includes at least a portion disposed parallel to a side of the bottom gate electrode, s6: a third insulating layer is provided on the portion, s7: the top gate electrode is patterned on the third insulating layer such that the top gate electrode is disposed at the other side of the portion of the active layer opposite to the bottom gate electrode side. By the method, the side face of the bottom grid electrode is used for arranging the channel of the active layer in the transistor with the vertical structure, meanwhile, the electron mobility of the active layer is further improved through the design of the double grid electrodes, the current is improved, and the area of the transistor is further reduced.
In order to better realize the function of the active layer, the active layer is brought into contact with the electrode, and specifically, the method further comprises the step of s1: disposing a first electrode on a substrate, s2: a first insulating layer is arranged on the first electrode, and a bottom grid metal layer is arranged on the first insulating layer; and step s4, after the second insulating layer mask is arranged, a specific step is carried out, and s41 etches the second insulating layer and the first insulating layer to obtain a via hole, so that the first electrode is exposed. Step s5 patterns the active layer on the second insulating layer so that the active layer is also in contact with the first electrode. In some other specific embodiments, step s7, patterning the top gate on the third insulating layer is specifically to provide a metal layer on the third insulating layer, patterning the metal layer to form the top gate, and patterning the metal layer to form a second electrode, where the second electrode is in contact with the active layer. By the method, the embodiment of the invention designs the top grid with the complete vertical structure, thereby achieving the technical effect of improving the electron mobility.
In other embodiments, the TFT structure design process of the present invention is as follows:
in the first step, a first electrode is fabricated on a glass or PI substrate, where the first electrode may be a source signal line or a drain electrode, and the source signal line is taken as an example.
The second step forms a film over the first electrode covering the first insulating layer.
And a third step of forming a film on the first insulating layer and patterning the bottom gate metal layer.
And fourthly, manufacturing a gate insulating layer on the gate driving circuit, and etching out the through hole to expose the surface of the first electrode.
And fifthly, forming an IGZO active layer and patterning the active layer, wherein the active layer is connected with the first electrode through the second insulating layer via hole, and the active layer is preferably made of an IGZO metal oxide material.
And a sixth step of forming a third insulating layer on the active layer, patterning the third insulating layer and exposing one end of the surface of the active layer.
A seventh step of forming a third metal layer on the third insulating layer and patterning the third metal layer as a top gate electrode and a second electrode, wherein the second electrode may be a source signal line or a drain electrode, and the active layer is connected to the third insulating layer by way of example.
And eighth step, a passivation layer (fourth insulating layer) is formed on the third metal layer to protect the TFT from being damaged by external water/oxygen.
According to the embodiment, the novel vertical structure TFT can be designed through the scheme, and the technical effects of improving the electron mobility of the active layer, improving the current and further reducing the area of the transistor are achieved through the design of the double-grid structure.
In the embodiment shown in fig. 4, it is shown that in some embodiments, after the second insulating layer is etched in s41, the active layer and the third insulating layer can be formed by continuous film forming, and then the patterns of the active layer and the third insulating layer are defined by etching twice by using the gray-scale mask at the same time, so that a step of one layer of mask can be further reduced, the cost is saved, and the manufacturing efficiency is improved.
In the example shown in fig. 5, we also provide an embodiment in which the second electrode and the top gate electrode are formed in two films. Specifically, after step s5, we further perform the steps of disposing a second electrode metal over the top of the active layer, then performing the coating of a third insulating layer to isolate the second electrode, the active layer from external contact, and then performing step s7 of patterning the top gate such that the top gate is disposed on the other side of the portion of the active layer opposite to the bottom gate side. This has the advantage that the second electrode can be isolated more thoroughly from the top gate. The stability of the device is improved.
In the embodiment shown in fig. 6, for the schematic view of the scan line arrangement, we can independently arrange the top gate scan line and separate from the bottom gate, see the first column above, and this design is simple to implement. The top gate scan lines can also be independently arranged and separated from the bottom gate on both sides, see the second column, and the design has better stability. In other embodiments, as shown in the third column, the top gate may also be connected to the bottom gate by etching a third insulating layer via. Through the design of the method, the forms of the panel can be diversified, and finally, the richer product functions are obtained.
Referring to fig. 7, a schematic structural diagram of a top-emitting OLED display panel of the present invention is shown, and the following steps are further performed, corresponding to the a-f panels of fig. 7:
step I patterning the fourth insulating layer to form a via hole exposing the SD surface;
step II, coating the whole organic flat layer, and developing out an organic layer via hole at the fourth insulating layer via hole to expose the SD surface;
manufacturing a high-reflection metal anode on the Step III flat layer, patterning, and connecting a drain electrode through a via hole;
step IV, manufacturing a pixel definition layer, exposing and developing the pixel definition layer on the anode to form a via hole, and exposing the surface of the anode;
step V patterning a PS layer supporting the substrate and the packaging cover plate;
step VI. The organic luminescent layer is evaporated on the anode at the position of the through hole of the pixel definition layer, and the metal cathode is evaporated.
Finally, the manufacture of the oled display panel with the top light-emitting structure is completed.
It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solution, directly or indirectly, to other relevant technical fields, all of which are included in the scope of the invention.

Claims (4)

1. The thin film transistor is characterized by comprising a substrate and a bottom grid electrode arranged on the substrate, wherein an active layer is further arranged above the bottom grid electrode, the active layer comprises a part which is arranged in parallel with one side surface of the bottom grid electrode, and the other side of the part, opposite to the side surface of the bottom grid electrode, of the active layer is further provided with a top grid electrode;
the active layer is arranged above the substrate and below the bottom grid electrode, and the active layer is in contact with the first electrode;
the second electrode is arranged above the active layer and is in contact with the active layer;
a first insulating layer is arranged between the first electrode and the bottom grid electrode;
a second insulating layer is arranged between the bottom grid electrode and the active layer, and a third insulating layer is arranged between the active layer and the top grid electrode.
2. A method of manufacturing a thin film transistor, which is the thin film transistor according to claim 1, comprising the steps of patterning a bottom gate metal layer, disposing a second insulating layer mask on the bottom gate metal layer, patterning an active layer on the second insulating layer such that the active layer includes at least a portion disposed parallel to one side of the bottom gate, disposing a third insulating layer on the portion, and patterning a top gate on the third insulating layer such that the top gate is disposed on the other side of the portion of the active layer opposite to the side of the bottom gate.
3. The method of manufacturing a thin film transistor according to claim 2, further comprising the steps of providing a first electrode on the substrate, providing a first insulating layer on the first electrode, and providing a bottom gate metal layer on the first insulating layer; and after the second insulating layer mask is arranged, etching the second insulating layer and the first insulating layer to obtain a via hole, exposing the first electrode, and patterning the active layer on the second insulating layer to enable the active layer to be in contact with the first electrode.
4. The method of manufacturing a thin film transistor according to claim 2, further comprising the step of patterning a top gate electrode on the third insulating layer, specifically, providing a metal layer on the third insulating layer, patterning the metal layer to form the top gate electrode, and patterning the metal layer to form a second electrode, wherein the second electrode is in contact with the active layer.
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CN113838938A (en) * 2020-06-24 2021-12-24 京东方科技集团股份有限公司 Thin film transistor, manufacturing method thereof, array substrate and electronic device
CN112968061A (en) * 2021-02-03 2021-06-15 京东方科技集团股份有限公司 Thin film transistor, display substrate, preparation method of display substrate and display device
CN113345967B (en) * 2021-05-21 2022-09-09 Tcl华星光电技术有限公司 Thin film transistor and LED backboard
CN114122145B (en) * 2021-11-15 2023-11-28 武汉华星光电半导体显示技术有限公司 Thin film transistor, electronic device, preparation method of thin film transistor and display device

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