CN107832010A - Data storage device - Google Patents
Data storage device Download PDFInfo
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- CN107832010A CN107832010A CN201711055987.7A CN201711055987A CN107832010A CN 107832010 A CN107832010 A CN 107832010A CN 201711055987 A CN201711055987 A CN 201711055987A CN 107832010 A CN107832010 A CN 107832010A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Security & Cryptography (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Bus Control (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Information Transfer Systems (AREA)
- Image Processing (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
A kind of data storage device may include first memory plate and second memory plate, wherein the first memory plate and the second memory plate each include multiple memory chips.The data storage device may include arranged and configuration to be operably connected to the controller board of the first memory plate and the second memory plate, wherein described controller board includes high-speed interface and controller, the controller is arranged and configuration is to receive order from main frame using the high-speed interface and perform the order, wherein the first memory plate and the second memory plate each can be removed individually from the controller board.
Description
The application is the applying date on April 1st, 2010, Application No. 201080020506.9, entitled " data are deposited
The divisional application of the PCT applications for a patent for invention of storage device ".
CROSS REFERENCE TO RELATED refers to
Present application request on April 8th, 2009 to filing an application and entitled " data storage device (DATA
STORAGE DEVICE) " No. 61/167,709 United States provisional application and filed an application on June 17th, 2009 and title
For " segmentation and stripping (the PARTITIONING AND STRIPING IN A FLASH in flash memory data storage apparatus
MEMORY DATA STORAGE DEVICE) " the 61/187th, No. 835 United States provisional application rights and interests, both is with entirety
The mode of reference is incorporated herein.
Technical field
This explanation is related to a kind of data storage device.
Background technology
Data storage device can be used to carry out data storage.Data storage device can be used together to provide with computing device
State the data storage needs of computing device.In some instances, it may be desirable to mass data is stored on data storage device.This
Outside, it may be desirable to be performed quickly from the data storage device and read data and the life to data storage device write-in data
Order.
The content of the invention
This document describes a kind of data storage device including one or more memory plates, wherein the memory
Each of plate includes multiple flash memory chips.The data storage device operationally connects including the memory plate
The controller board being connected to.The data storage device can be configured to be communicated using interface with main frame to be connect from the main frame
Receive order and handle these orders using the flash memory chip.For example, the main frame is transmittable and the control
Device plate processed can receive the order to be read using the flash memory chip, write, copy and wipe data block.
In an exemplary embodiment, the controller includes field programmable gate array (FPGA) controller and institute
It can be high-speed interface to state the interface between main frame and the controller board, such as (for example) periphery component interconnection is at a high speed
(PCIe) interface.In this way, the data storage device may include high storage volume and can be configured to realize the main frame
The high-performance and high speed of data transmission between the flash memory chip.
In an exemplary embodiment, the data storage device can be configured with two memory plates, its
Described in each of memory plate include multiple flash memory chips.Including the controller board and two memory plates
The data storage device can be configured in the form of disc driver so that the data storage device is assemblied in computing device
On plate in driver slot.For example, the data storage device can be configured be assemblied on the plate of server in driver slot with
Data storage capacity is provided for the server.The data storage device can be configured and can substitute so that it can hold
Change places and remove and be inserted on the plate of different computing devices in driver slot from the computing device.
In addition, the data storage device can be modularization so that memory plate can disconnect and by other with controller board
Memory plate is replaced, wherein other memory plates may also comprise multiple flash memory chips.Control on controller board
Device processed can be to be configurable to recognize one of memory plate or one or more of disconnected and replaced by other memory plates.It is described
Controller can be configured to recognize swapping out and can handling between main frame and other memory plates for this type of memory plate
Order.In this way, even if one of memory plate or one or more of no longer available, controller board can be also continuing with.
Disabled memory plate can disconnect and can be replaced by another memory plate with controller board, while still use same controller board
And the same components on the controller board.
In an exemplary embodiment, the data storage device can be to be configurable to dispose different types of quick flashing
Memory chip.For example, the controller on controller board can be configured to recognize different types of fast on memory plate
Flash memory chip simultaneously operates together.For example, the controller can be FPGA controller, and it is configured to identification not
The flash memory chip of same type, including (for example) single level-cell (SLC) flash memory chip, more level
Unit (MLC) flash memory chip, NAND quick-flash memory chip, NOR flash memory chip and other types of quick flashing
Memory chip.The controller can be configured to recognize the flash memory core from different flash memory chip retailers
Piece.The controller can be configured to recognize the different types of flash memory chip and by based on memory plate
The type of flash memory chip is translated performs the order using the flash memory chip from the order of main frame.
Therefore, because the type of flash memory chip, it is not necessary to main frame come translate it is described order or transmission different command.It is described
Controller can be configured with for the certain types of flash memory chip by the command translation cost from main frame
Machine order.
In this way, the same controller board with same controller can with different types of flash memory chip
Memory plate be used together.For example, first memory plate and second memory plate may be connected to controller board and described
Each of plate may include by the SLC NAND quick-flash memory chips of retailer's manufacture.The first memory plate and
The second memory plate can disconnect and be replaced by two other memory plates, wherein other memory plates are included by difference
The MLC NAND quick-flash memory chips of retailer's manufacture.The controller can be configured automatically to recognize other storages
Flash memory chip on device plate and performed using the flash memory chip on other memory plates from main frame
Order.In this way, according to the application program on main frame characteristic and according to described in required for the application program on main frame
The feature of data storage device, the different flash memory cores that the data storage device may customize and be configured with memory plate
Piece.
In other exemplary embodiments, each of described memory plate may include except flash memory chip with
Outer storage arrangement.For example, each of described memory plate may include multiple dynamic random access memory
(DRAM) chip.In a manner of above for the identical described by flash memory chip, the data storage device can be can
Configure to dispose different types of dram chip.For example, the controller on controller board can be configured to recognize memory
Different types of dram chip on plate simultaneously operates together.One memory plate of dram chip can be from data storage device
Remove and replaced by the memory plate with different types of dram chip.The controller can be by based on memory plate
The type of dram chip is translated performs the order using different types of dram chip from the order of main frame.Other
In exemplary embodiment, the memory plate may include other types of storage arrangement, including (for example) phase
Transition storage (PCM) chip and other types of storage arrangement.
In another exemplary embodiment, the controller on controller board can be configured to recognize a memory
The storage arrangement of a type on plate simultaneously operates together, and is deposited simultaneously with different types of on another memory plate
The biconditional operation of reservoir device one.For example, one of described memory plate may include flash memory chip and another storage
Device plate may include dram chip.
In an exemplary embodiment, the data storage device can be to be configurable to disposal to have different voltages
Flash memory chip.For example, the controller on controller board can be configured to recognize having on memory plate
The flash memory chip of different voltages simultaneously operates together.For example, the controller can sense the flash
The voltage of device chip and by control circuit power be configured for should needed for voltage.For example, the controller can be that FPGA is controlled
Device processed, the voltage for the flash memory chip that the FPGA controller is configured to sense that on memory plate and is felt based on described
Voltage is surveyed to be configured to the power module on controller board to supply appropriate voltage to the flash memory chip.The controller
It may be configured to sense the voltage of the flash memory chip and the flash memory chip on it need not necessarily need to be based on memory plate
Order of the voltage translation from the main frame in the case of the order is performed using the flash memory chip.
In this way, the same controller board with same controller can be from the flash memory chip with different voltages
Memory plate be used together.For example, first memory plate and second memory plate may be connected to the controller board and
Each of described plate may include the flash memory chip operated with first voltage.The first memory plate and described
Two memory plates can disconnect and be replaced by two other memory plates, wherein other memory plates include grasping with second voltage
The flash memory chip of work, wherein the second voltage is different from the first voltage.The controller can be configured with：From
The second voltage of the flash memory chip on other memory plates is sensed dynamicly；The power module is matched somebody with somebody
It is set to and is operated with the second voltage；And come from using the flash memory chip on other memory plates to perform
The order of main frame.In this way, according to the application program on main frame characteristic and according to needed for the application program on main frame
The feature for the data storage device wanted, the data storage device is customizable and is configured with other memory plates
Different flash memory chips.
Use single controller plate (it has the single controller on the plate separated with the flash memory chip)
Realize the flexibility for configuring the data storage device.For example, using single controller plate, (it has the warp on the plate
Configuration has the flash memory of different voltages to recognize different types of flash memory chip and together operation and/or identification
Memory chip and the single controller operated together) different flash memory chip technologies are made it possible for design
State data storage device.In addition, the type by the application program interfaced with the data storage device that can be on Intrusion Detection based on host is come
Selection specific flash memory chip technology simultaneously uses on memory plate.Further, since flash memory chip technology can change
Become, same controller board and controller can be by the memory plates that swaps out and flash memory chips one different from memory plate
With use.In this way, the controller board with the controller and other components can be considered as and is configurable to receive memory
The general purpose controller plate and controller of a variety of different types of flash memory chips on plate.
According to a general aspect, data storage device may include first memory plate and second memory plate, wherein institute
State first memory plate and the second memory plate each and include multiple memory chips.The data storage device can wrap
Arranged and configuration is included to be operably connected to the controller board of the first memory plate and the second memory plate, its
Described in controller board include high-speed interface and controller, the controller is arranged and configuration with using the high-speed interface from
Main frame receives order and performs the order, wherein the first memory plate and the second memory plate each can be independent
Ground removes from the controller board.The data storage device can be embodied as computer program product.
Embodiment may include one of following characteristics or one or more of.For example, the controller can be scene
Programmable gate array (FPGA) controller.The memory chip may include flash memory chip.The flash memory core
Piece may include single level-cell (SLC) NAND quick-flash memory chip and/or multi-level-cell (MLC) NAND quick-flash memory core
Piece.The high-speed interface may include PCI-e interfaces.In an exemplary embodiment, the flash memory chip can wrap
NAND quick-flash memory chip is included, the high-speed interface can be PCI-e interfaces and the controller can be field-programmable gate array
Arrange (FPGA).
The first memory plate, the second memory plate and the controller board can be arranged and configured to be assemblied in
In the drive bay of server.The first memory plate can be operably connected to the controller board top side and
The second memory plate can be the bottom side for being operably connected to the controller board.
In an exemplary embodiment, the memory chip may include dynamic random access memory (DRAM) core
Piece.In another exemplary embodiment, the memory chip includes phase transition storage (PCM) chip.
The first memory plate and the second memory plate can be modular board, and its is arranged and is configured to be removed
And by including multiple memory chips another memory plate replace.The controller may include power module and can be arranged
And configuration with：Control the command process to multiple memory chips with different voltages；Automatically recognize first storage
The voltage of device plate and the memory chip on the second memory plate；The power module is configured to the storage
The recognized voltage operation of device chip；Received and ordered from the main frame using the interface；And use the storage core
Piece performs the order.
The controller can it is arranged and configuration with：Control the command process to a variety of different types of memory chips；
Automatically recognize the type of the first memory plate and the memory chip on the second memory plate；Using described
Interface is received from the main frame and ordered；And the order is performed using the memory chip.
The controller may include multiple passages, wherein each of described passage and one in the memory chip
Each of person or one or more of associated and described memory chip are associated with one of the passage.The control
Device may include the channel controller for each of the passage.
In another general aspect, a kind of computing device may include main frame and data storage device.The data storage dress
Putting may include：First memory plate；Second memory plate, wherein the first memory plate and the second memory plate are each
Person includes multiple memory chips；And controller board, its is arranged and configures to be operably connected to the first memory
Plate and the second memory plate.The controller board may include：High-speed interface；And controller, its it is arranged and configure so that
Order is received from main frame with the high-speed interface and perform the order, wherein the first memory plate and second storage
Device plate each can be removed individually from the controller board.In some cases, the computing device can be embodied as computer
System or the part for being embodied as computer system.Embodiment may include one of feature discussed above and below or
It is one or more of.
In another general aspect, a kind of method for being used to assemble data storage device may include：By multiple storage cores
Piece is fixed to first memory plate；Multiple memory chips are fixed to second memory plate；High-speed interface and controller is attached
It is connected to controller board；The first memory plate is operably connected to the controller board；And by the second memory
Plate is operably connected to the controller board, wherein the first memory plate and the second memory plate each can be single
Solely removed from the controller board.
Embodiment may include one of following characteristics or one or more of.For example, methods described can be wrapped further
Include：Multiple memory chips are fixed to the 3rd memory plate；By in the first memory plate or the second memory plate
One of with the controller board disconnect；And the 3rd memory plate is operably connected to the controller board.By institute
First memory plate is stated to be operably connected to the controller board and the second memory plate is operably connected into institute
Stating controller board may include to form the driver support of the first memory plate, the second memory plate and the controller board
Frame form factor so that the drive bay form factor is configured to be assemblied in the drive bay of server.By institute
Stating first memory plate and being operably connected to the controller board may include the first memory plate being operably connected
To the top side of the controller board, and by the second memory plate be operably connected to the controller board may include by
The second memory plate is operably connected to the bottom side of the controller board.
In one embodiment, the memory chip may include dynamic random access memory (DRAM) chip.
In another embodiment, the memory chip may include phase transition storage (PCM) chip.In another embodiment, it is described
Memory chip may include flash memory chip.The quick flashing on the first memory plate and the second memory plate
Memory chip may include NAND quick-flash memory chip, and the high-speed interface can be PCI-e interfaces and the controller can be
Field programmable gate array (FPGA) controller.
In one embodiment, a kind of data storage device (100), it includes：Memory plate (104a), the storage
Device plate (104a) includes multiple NAND memory chips (118a), and the chip is the storage of single level-cell or multi-level-cell
Device chip；Controller board (102) is operatively coupled to the memory plate (104a), wherein the controller board (102) wraps
Field programmable gate array controller (410) is included, the field programmable gate array controller (410) is arranged and configures to control
The multiple NAND memory chip (118a) storage operation is made, and wherein described controller board (102) is in physics
On independently of the memory plate (104a) plate；Periphery component interconnection high-speed interface (108,408) is operatively coupled to institute
State controller board (102), the periphery component interconnection high-speed interface (108,408) is arranged and configuration with main frame (106) and
Interface is provided between the field programmable gate array controller (410) causes the field programmable gate array controller to pass through
The periphery component interconnection high-speed interface (108,408) and the main frame direct communication；And other memory plate (104b),
The other memory plate (104b) includes multiple NAND memory chips (118a), the other memory plate (104b)
The controller board (102) is operatively coupled to, wherein the controller board (102) and the other memory plate
(104b) is on themselves independent printed circuit board (PCB), and wherein described controller board (102) is disposed in bottom, and institute
State memory plate (104a) and the other memory plate (104b) is disposed in top；And wherein：The controller board
(102) and the NAND memory chip (118a, 118b) is arranged and configuration using multiple passages (112) to be communicated, described
Each passage of multiple passages (112) is configured as communicating with one or more NAND memory chips (118a, 118b), and institute
State field programmable gate array controller (410) be configured such that from the main frame (106) receive order can be by described existing
Field programmable gate array controller (410) while performed using each in the multiple passage (112).
In another embodiment, a kind of data storage device (100), it includes：First plate (104a), described first
Plate (104a) includes multiple NAND memory chips (118a)；Second plate (102), it is operatively coupled to first plate
(104a), wherein second plate (102) includes field programmable gate array controller (408), its is arranged and configures to control
Make the storage operation of the multiple NAND memory chip, and second plate (102) be physically independent from it is described
The plate of first plate (104a)；Periphery component interconnection high-speed interface (108,408) is operatively coupled to second plate (102),
Its arranged and configuration is caused with providing interface between main frame (106) and the field programmable gate array controller (408)
The field programmable gate array controller passes through the periphery component interconnection high-speed interface (108,408) and the main frame
(106) direct communication；And the 3rd other plate, the 3rd other plate is that have multiple NAND memory chips (118b)
Memory plate (104b), the 3rd other plate is operatively coupled to second plate (102), wherein second plate
(102) be its own printed circuit board (PCB), wherein second plate (102) is located at first plate (104a) and the 3rd plate
Between (104b), first plate and the 3rd plate are in the separate printed circuit boards of themselves；And wherein：The control
Device plate (102) processed and the NAND memory chip (118a, 118b) are arranged and configuration is with logical using multiple passages (112)
Letter, each passage of the multiple passage (112) are configured as leading to one or more NAND memory chips (118a, 118b)
Letter, and be configured such that can be by from the order that the main frame (106) receives for the field programmable gate array controller (410)
The field programmable gate array controller (410) while performed using each in the multiple passage (112).
The details of one or more embodiments is illustrated in the accompanying drawings and the description below.From it is described explanation and schema and
Further feature is will become apparent from from claims.
Brief description of the drawings
Fig. 1 is the exemplary block diagram of data storage device.
Fig. 2 is the exemplary perspective block diagram of the printed circuit board (PCB) of the data storage device.
Fig. 3 is the exemplary block diagram for the exemplary computing device being used together with Fig. 1 data storage device.
Fig. 4 is the exemplary block diagram of controller.
Fig. 5 is the exemplary flow chart of the exemplary assembling for the data storage device for illustrating Fig. 1.
Fig. 6 is the exemplary block diagram of the exemplary embodiment of Fig. 1 data storage device.
Fig. 7 is the exemplary flow chart of the example operational for the data storage device for illustrating Fig. 1.
Fig. 8 is the exemplary flow chart of the example operational for the data storage device for illustrating Fig. 1.
Embodiment
This document describes the equipment, system and technology for data storage.This data storage device may include can be with one
Or the controller board of controller that more than one different memory plate is used together, wherein each of described memory plate has
There are multiple flash memory chips.The interface on the controller board can be used to be led to main frame for the data storage device
Letter.In this way, the controller on the controller board can be configured to be received using the interface from the main frame
Order and perform these orders using the flash memory chip on the memory plate.
Fig. 1 is the block diagram of data storage device 100.Data storage device 100 may include controller board 102 and one or
More than one memory plate 104a and 104b.Data storage device 100 can be communicated via interface 108 with main frame 106.Interface
108 can be between main frame 106 and controller board 102.Controller board 102 may include controller 110, DRAM 111, multiple passages
112nd, power module 114 and memory module 116.Memory plate 104a and 104b may include each of described memory plate
On multiple flash memory chip 118a and 118b.Memory plate 104a and 104b may also include storage arrangement 120a and
120b。
In general, data storage device 100 can be configured with store data in flash memory chip 118a and
On 118b.Main frame 106 can write data into flash memory chip 118a and 118b and from flash memory chip 118a and
118b reads data, and causes the other operations that will be performed on flash memory chip 118a and 118b.Can be via control
Controller 110 on device plate 102 come handle and by controller 110 come control main frame 106 and flash memory chip 118a and
Digital independent and write-in and other operations between 118b.Controller 110 can receive order from main frame 106 and cause use to deposit
Flash memory chip 118a and 118b on reservoir plate 104a and 104b performs these orders.Main frame 106 and controller 110
Between communication can be via interface 108.Passage 112 can be used to enter with flash memory chip 118a and 118b in controller 110
Row communication.
Controller board 102 may include DRAM 111.DRAM 111 can be to be operatively coupled to controller 110 and can be used to
Storage information.For example, DRAM 111 can be used to store logical address to physical address map and bad block message.DRAM 111
It also can be configured for use as the buffer between main frame 106 and flash memory chip 118a and 118b.
In an exemplary embodiment, each of controller board 102 and memory plate 104a and 104b are
Physically single printed circuit board (PCB) (PCB).Memory plate 104a can be operably connected to the one of controller board 102PCB
On individual PCB.For example, memory plate 104a physics and/or can be electrically connected to controller board 102.Similarly, memory plate
104b can be and memory plate 104a PCB separated and can be to be operably connected to controller board 102PCB.For example, deposit
Reservoir plate 104b physics and/or can be electrically connected to controller board 102.Memory plate 104a and 104b each can individually with control
Device plate 102 processed disconnects and removed from controller board 102.For example, memory plate 104a can be disconnected from controller board 102 and by
Another memory plate (not showing) is replaced, wherein another memory plate is operably connected to controller board 102.It is real herein
In example, can be swapped out any one of memory plate 104a and 104b or both with other memory plates so that other storages
Device plate can be with same controller board 102 and the biconditional operation of controller 110 1.
In an exemplary embodiment, each of controller board 102 and memory plate 104a and 104b can
With disc driver form factor physical connection.The disc driver form factor may include different size, such as (citing comes
Say) 3.5 " disc driver form factor and 2.5 " disc driver form factors.
In an exemplary embodiment, each of controller board 102 and memory plate 104a and 104b can
Electrically connected using high-density balls grid array (BGA) connector.Other versions of BGA connectors can be used, including (act
For example) carefully ball grid array (FBGA) connector, ultra-fine ball grid array (UBGA) connector and micro ball grid array (MBGA) connection
Device.Other types of electrical connecting member can also be used.
In an exemplary embodiment, controller board 102 (it is the PCB of their own) can be physically located in storage
Between each of device plate 104a and 104b, memory plate 104a and 104b is on the single PCB of their own.Referring also to Fig. 2,
Data storage device 100 may include on the PCB of controller board 102 and the 3rd on a PCB on memory plate 104a, the 2nd PCB
Memory plate 104b.Memory plate 104a includes multiple flash memory chip 118a and memory plate 104b is including multiple fast
Flash memory chip 118b.Controller board 102 includes controller 110 and to the interface 108 of main frame (not showing) and other group
Part (is not shown).
In the illustrated examples of Fig. 2, memory plate 104a is operably connected to controller board 102 and positioned at control
On the side 220a of device plate 102 processed.For example, memory plate 104a may be connected to the top side 220a of controller board 102.Deposit
Reservoir plate 104b is operably connected to controller board 102 and on the second side 220b of controller board 102.For example,
Memory plate 104b may be connected to the bottom side 220b of controller board 102.
Other physics between memory plate 104a and 104b and controller board 102 and/or to electrically connect be possible.Fig. 2
Only illustrate an exemplary arrangements.For example, data storage device 100 may include two or more memory plate, such as
Three memory plates, four memory plates or four device plates stored above, wherein all memory plates are connected to single control
Device plate processed.In this way, data storage device can be configured still with disc driver form factor.In addition, memory plate can be
Other arrangements (such as (for example) controller board in top and memory card in bottom or controller board in bottom and memory
Be stuck in top) in be connected to controller board.
Data storage device 100 can be arranged and configured to be cooperated with computing device.In an exemplary embodiment,
Controller board 102 and memory plate 104a and 104b can be arranged and configured to be assemblied in the drive bay of computing device
It is interior.Reference picture 3, illustrate two exemplary computing devices, i.e. server 330 and server 340.Server 330 and 340 can
Arranged and configuration is serviced with providing various types of calculate.Server 330 and 340 may include main frame (for example, Fig. 1
Main frame 106), the main frame includes computer program product, and the computer program product has and causes server 330 and 340
In one or more processors provide calculate service instruction.The type of server may depend on the server
One or more application programs of operation.For example, server 330 and 340 can be apps server, web clothes
Business device, e-mail server, search server, crossfire media server, e-commerce server, FTP
(FTP) combination of server, other types of server or these servers.Server 330 can be configured in server rack
The frame installation server of interior operation.Server 340 can be configured to the separate server operated independently of server rack.I.e.
Making server 340, it also can be configured and operates and be operably connected together with other servers not in server rack
To other servers.Server 330 and 340 is intended to illustrate example computing device and other computing devices can be used, its
Include other types of server.
In an exemplary embodiment, Fig. 1 and Fig. 2 data storage device 100 can be sized to be assemblied in
With for the offer number of server 330 and 340 in the drive bay 335 of server 330 or the drive bay 345 of server 340
According to storage functionality.For example, data storage device 100 can be sized and be 3.5 " disc driver form factor with
It is assemblied in drive bay 335 and 345.Data storage device 100 may be additionally configured to other sizes.Data storage device 100
Interface 108 can be used operationally to be connected and communicate with server 330 and 340.In this way, main frame can be used interface 108 will
Order is delivered to controller board 102 and flash memory chip on memory plate 104a and 104b can be used in controller 110
118a and 118b performs the order.
Referring back to Fig. 1, interface 108 may include the high-speed interface between controller 110 and main frame 106.The high quick access
Rapid data between the achievable main frame 106 of mouth and flash memory chip 118a and 118b transmits.In an exemplary implementation
In scheme, the high-speed interface may include PCIe interface.For example, the PCIe interface can be PCIe x4 interfaces or PCIe
X8 interfaces.PCIe interface 108 may include the PCIe connector cable sub-assemblies of main frame 106.Can also be used other high-speed interfaces,
Connector and connector assembly.
In an exemplary embodiment, controller board 102 and the flash memory on memory plate 104a and 104b
Multiple passages 112 can be arranged and be configured to communication between chip 118a and 118b.Each of passage 112 can with one or
More than one flash memory chip 118a and 118b communications.Controller 110 can be configured and cause the life received from main frame 106
Order can by controller 110 using each of passage 112 simultaneously or least substantially at performing simultaneously.In this way, can be not
With multiple orders are performed simultaneously on passage 112, this can improve the handling capacity of data storage device 100.
In the example of fig. 1, the individual passage 112 in 20 (20) is illustrated.Complete solid line illustrates controller 110 with depositing
The individual passage in ten (10) between flash memory chip 118a on reservoir plate 104a.The solid line of mixing is controlled with illustrated in dashed lines explanation
The individual passage in ten (10) between flash memory chip 118b on device 110 and memory plate 104b processed.Say as illustrated in fig. 1
Bright, each of passage 112 can support multiple flash memory chips.For example, each of passage 112 can be supported
Up to 32 flash memory chips.In an exemplary embodiment, each of described 20 passages can be configured
To support 6 flash memory chips and communicate with.In this example, each of memory plate 104a and 104b will be each
From including 60 flash memory chips.According to flash memory chip 118a and 118b type and number, data storage 100
Device can be configured to store up to multiple data terabytes and including multiple data terabyte.
Controller 110 may include the group of microcontroller, FPGA controller, other types of controller or these controllers
Close.In an exemplary embodiment, controller 110 is microcontroller.Can be with the combination of hardware, software or hardware and software
To implement the microcontroller.For example, can be loaded from memory (for example, memory module 116) to the microcontroller
Computer program product, the computer program product include when executed the microcontroller being caused to hold in a certain manner
Capable instruction.The microcontroller can be configured to receive order from main frame 106 using interface 108 and perform the order.Lift
For example, the order may include to using flash memory chip 118a and 118b reading, write-in, copy and erasing data
The order of block and other orders.
In another exemplary embodiment, controller 110 is FPGA controller.Can with hardware, software or hardware with it is soft
The FPGA controller is implemented in the combination of part.For example, can be from memory (for example, memory module 116) to described
FPGA controller loading firmware, the firmware include to cause what the FPGA controller performed in a certain manner when executed
Instruction.The FPGA controller can be configured to receive order from main frame 106 using interface 108 and perform the order.Citing
For, the order may include to using flash memory chip 118a and 118b reading, write-in, copy and erasing data block
Order and other orders.
In an exemplary embodiment, FPGA controller can support multiple interfaces 108 with main frame 106.Citing comes
Say, FPGA controller can be configured to support multiple PCIe x4 or PCIe x8 interfaces with main frame 106.
Memory module 116 can be configured to store data, the data can be loaded into controller 110.For example,
Memory module 116 can be configured to store one or more images of FPGA controller, and wherein described image includes supplying
The firmware that the FPGA controller uses.Memory module 116 can be interfaced with main frame 106 to be communicated with main frame 106.Memory mould
Block 116 can directly be interfaced with main frame 106 and/or can interfaced with indirectly with main frame 106 via controller 110.For example, main frame
One or more images of firmware can be delivered to memory module 116 to be stored by 106.In an exemplary implementation
In scheme, memory module 116 includes Electrically Erasable Read Only Memory (EEPROM).Memory module 116 can also wrap
Include other types of memory module.
Power module 114 can be configured to receive electric power (Vin), with perform institute reception electric power any conversion and export it is defeated
Go out electric power (Vout).Power module 114 can receive electric power (Vin) from main frame 106 or from another source.Power module 114 can be by electricity
Power (Vout) is provided to the component on controller board 102 and controller board 102, including controller 110.Power module 114
Electric power (Vout) can be also provided to the component on memory plate 104a and 104b and memory plate 104a and 104b, wherein wrapping
Include flash memory chip 118a and 118b.
In an exemplary embodiment, power module 114 may include that one or more direct currents (DC) turn to DC
Parallel operation.DC to DC converters can be configured to receive electric power input (Vin) and be one or more by the electrical power conversion
Different voltage levels (Vout).For example, power module 114 can be configured to receive+12V (Vin) and turn the electric power
Be changed to 3.3v, 1.2v or 1.8v and by the electric power output (Vout) be fed to controller board 102 and memory plate 104a and
104b。
Memory plate 104a and 104b may be configured to handle different types of flash memory chip 118a and 118b.
In one exemplary embodiment, flash memory chip 118a and flash memory chip 118b can be the quick flashing of same type
Memory chip, sold including the identical voltage needed from power module 114 and from identical flash memory chip
Business.Term retailer is used interchangeably with manufacturer in this document in the whole text.
In another exemplary embodiment, the flash memory chip 118a on memory plate 104a can be and memory
The flash memory chip of types different flash memory chip 118b on plate 104b.For example, memory plate 104a
It may include SLC NAND quick-flash memories chip and memory plate 104b may include MLC NAND quick-flash memory chips.Another
In example, memory plate 104a may include flash memory chip and memory from a flash memory chip manufacturer
Plate 104b may include the flash memory chip from different flash memory chip manufacturers.With the fast of whole same types
It is suitable that flash memory chip or flexibility with different types of flash memory chip make it possible to data storage device 100
Close the different application that main frame 106 is used.
In another exemplary embodiment, memory plate 104a and 104b can include inhomogeneity on same memory plate
The flash memory chip of type.For example, memory plate 104a can include SLC NAND chips and MLC on same PCB
Both NAND chips.Similarly, memory plate 104b may include both SLC NAND chips and MLC NAND chips.With this side
Formula, data storage device 100 can be advantageously customized to meet the specification of main frame 106.
In another exemplary embodiment, memory plate 104a and 104b may include other types of storage arrangement,
Including corresponding nand flash memory chip.For example, memory plate 104a and 104b may include random access memory
(RAM), such as (for example) dynamic ram (DRAM) and static RAM (SRAM) and other types of RAM and other types of
Storage arrangement.In an exemplary embodiment, both memory plate 104a and 104b may include RAM.In another demonstration
In property embodiment, one of described memory plate may include RAM and another memory plate may include flash memory chip.
In addition, one of described memory plate may include both RAM and flash memory chip.
Memory module 120a and 120b on memory plate 104a and 104b can be stored respectively and flash memory
Chip 118a and 118b related information.In an exemplary embodiment, memory module 120a and 120b can be stored soon
The equipment energy characteristic of flash memory chip.Described device characteristic may include that the chip is SLC chips or MLC chips, the core
Piece is number, the number of block, the number of every piece of page, the number of every page of byte and described that NAND or NOR chips, chip select
The speed of chip.
In an exemplary embodiment, memory module 120a and 120b may include serial EEPROM.EEPROM can
Storage device characteristic.The flash memory chip compilation primary device characteristic of any given type can be directed to and described device can be used
Characteristic produces appropriate EEPROM images., then can be from when memory plate 104a and 104b are operably connected to controller board 102
EEPROM reads described device characteristic so that controller 110 can recognize the flash memory core that controller 110 is controlling automatically
Piece 118a and 118b type.In addition, described device can be used for certain types of flash memory chip 118a and 118b
Controller 110 is configured to suitable parameter by characteristic.
As discussed above, controller 110 may include FPGA controller.Reference picture 4, it illustrates FPGA controller
410 exemplary block diagram.FPGA controller can be configured to be operated in a manner of as described by the controller 110 above for Fig. 1.
FPGA controller 410 may include multiple passages 112 to be connected to multiple channel controllers of flash memory chip 418
450.Flash memory chip 418 is illustrated as being connected to multiple flash of each of channel controller 450
Device chip.Flash memory chip 418 represents Fig. 1 flash memory chip 118a and 118b, flash memory chip 118a
And 118b is on Fig. 1 single memory plate 104a and 104b.The single memory plate is not shown in the example in figure 4.
FPGA controller 410 may include PCIe interface module 408, two-way direct memory access (DMA) (DMA) controller 452, dynamic random
Access memory (DRAM) controller 454, command processor/queue 456 and information and configuration interface module 458.
Interface and main frame (for example, Fig. 1 main frame 106) transmission information can be used.In this example (Fig. 4), FPGA controls
Device 410 is included to the PCIe interface with main-machine communication and PCIe interface module 408.PCIe interface module 408 can it is arranged and
Main frame is ordered and sent commands to configuration to be received from main frame.PCIe interface module 408 can be in main frame and data storage device
Between data flow control is provided.PCIe interface module 408 may be such that can be in main frame and controller 410 and final flash memory
High-speed transferring data between chip 418.In an exemplary embodiment, PCIe interface and PCIe interface module 408 can wrap
Include 64 BITBUS networks.
Two-way dma controller 452 can be configured to be controlled with PCIe interface 408, command processor/queue 456 and passage
Each of device 450 interfaces with.Two-way dma controller 452 makes it possible to carry out between main frame and flash memory chip 418
Two-way direct memory access (DMA).
Dram controller 454 can be arranged and configured with the translation of control logic address to physical address.For example,
Dram controller 454 can assist command processor/queue 456 by the logical address that main frame uses to flash memory chip 418
In actual physical address (be just written to flash memory chip 418 or from flash memory chip 418 read data
It is related) translation.The logical address received from main frame can translate into the thing of the position in one of flash memory chip 418
Manage address.Similarly, the physical address of the position in one of flash memory chip 418 can translate into logical address and by
It is delivered to main frame.
Command processor/queue 456 can it is arranged and configuration with via PCIe interface module 408 from main frame receive order and
The execution of the order is controlled via channel controller 450.Command processor/queue 456 can maintain several pending lives
The queue of order.In this way, can perform simultaneously it is multiple order and can simultaneously or at least essence simultaneously use passage 112 in it is each
Person.
Command processor/queue 456 can be configured disorderly to handle the order of different passages 112 and keep ordering by passage
Order sequence.For example, command processor/queue 456 can be handled disorderly receives and is assigned to the life of different passages from main frame
Order.In this way, the channel busy can be kept.From can coming by the order of command processor/queue 456 from main frame reception order
Manage the order received from main frame to be handled on the same channel.In an exemplary embodiment, command processor/team
Row 456 can be configured the list of the order to maintain to receive from main frame in the oldest list classified first, to ensure the life
The timely execution of order.
Channel controller 450 can be arranged and configured to handle the order from command processor/queue 456.Passage control
Each of device 450 processed can be configured to handle the order of multiple flash memory chips 418.An exemplary implementation side
In case, each of channel controller 450 can be configured to handle up to 32 flash memory chips 418 (and including 32
Including individual flash memory chip 418) order.
Channel controller 450 can be configured to be handled at order with the order specified by command processor/queue 456
Manage the order of device/queue 456.The example of accessible order includes but is not limited to read quick flashing page, programming quick flashing page, copy soon
Dodge page, erasing flash block, the metadata for reading flash block, the bad block and reset flash memory core for mapping flash memory chip
Piece.
Information with configuration interface module 458 can it is arranged and configuration with memory module (for example, Fig. 1 memory mould
Block 116) interface with to receive the configuration information of FPGA controller 410.For example, information can be from institute with configuration interface module 458
State memory module and receive one or more images to provide firmware to FPGA controller 410.To described image and right
The modification of the firmware can provide controller 410 by main frame via information and configuration interface module 458.Via information and configuration
The modification that interface module 458 receives can be applied to any one of component of controller 410, including (for example) PCIe
Interface module 408, two-way dma controller 452, dram controller 454, command processor/queue 456 and channel controller 450.
Information may include one or more registers with configuration interface module 458, optionally can be repaiied by the instruction from main frame
Change one or more than one register.
FPGA controller 410 can be arranged and configured to combine host collaboration and processing order.FPGA controller 410 can be held
Row or at least auxiliary execution error correction, bad block management, logical/physical mapping, garbage collection, wear leveling and quick flashing
The related segmentation of memory chip 418 and low-level formatting.
Reference picture 5, it illustrates the process 500 for assembling data storage device.Process 500 may include will be multiple fast
Flash memory chip is installed to first memory plate 510 and multiple flash memory chips is installed into second memory plate 520.
For example, memory plate 104a and multiple flash memories can be fixed to referring also to Fig. 1, multiple flash memory chip 118a
Chip 118b can be fixed to memory plate 104b.Memory plate 104a and 104b can be flash memory chip 118a and 118b institutes
The printed circuit board (PCB) (PCB) being attached respectively to.The amount of each of memory plate 104a and 104b memory capacity is individually
And it jointly may depend on the type and number of flash memory chip 118a and 118b fixed to memory plate 104a and 104b
Mesh.Flash memory chip 118a and 118b may be disposed to one or more passages so that single passage is controllable to more
The command process of individual flash memory chip, as discussed above.
Flash memory chip 118a and 118b can be on the flash memory chip or memory plate 104a of same type
Flash memory chip may differ from flash memory chip on memory plate 104b.In addition, memory plate 104a and
104b may include the different number flash memory chips on each of described memory plate.For example, memory
Plate 104a may include 60 flash memory chips and memory plate 104b may include 80 flash memory chips, wherein storing
Flash memory chip on device plate 104a can be and the flash memory chip same type or difference on memory plate 104b
The flash memory chip of type.
Process 500 may include：High-speed interface and controller are attached to controller board 530；By the first memory plate
It is operably connected to the controller 540；And the second memory plate is operably connected to the controller board, its
Described in first memory plate and the second memory plate each can individually from the controller board remove 550.Citing
For, interface 108 can be high-speed interface and could attach to controller board 102 530.Controller 110 could attach to controller board
102.Controller board 102 can be the PCB attached by the high-speed interface and the controller.
Memory plate 104a can be that to be operably connected to controller board 102 540 and memory plate 104b can be operable
Ground is connected to the controller board 550.Memory plate 104a is separates and different memory plate and deposited with memory plate 104b
Each of reservoir plate 104a and 104b can be removed individually from controller board 102.Assembled controller board 102 and two deposit
Reservoir plate 104a and 104b can form data storage device 100 together.
In an exemplary embodiment, memory plate 104a and 104b can disconnect with controller board 102 and can be by two
Individual other memory plates are replaced, and described two other memory plates have the flash memory for being attached to other memory plates
Chip.Other flash memory plates may include with the flash memory chip 118a on memory plate 104a and 104b and
The flash memory chip of 118b same types or other flash memory plates may include different types of flash memory
Chip.Other flash memory plates may also comprise the flash memory core different from memory plate 104a and 104b number
Piece.
In an exemplary embodiment, assembled data storage device 100 (including it is connected to controller board 102
Memory plate 104a and 104b) the drive bay shape being configured to be assemblied in the drive bay of computing device can be formed
Factor.For example, reference picture 2 and Fig. 3, Fig. 2 data storage device 100 can be configured to be assemblied in the driving of computing device
In device bracket slot, such as the drive bay groove of the drive bay groove 335 of (for example) server 330 or server 340
345。
Reference picture 6, Fig. 1 data storage device 100 are illustrated as data storage device 600.Data storage device
600 may include controller board 102, and controller board 102 includes the PCIe interface 608, FPGA controller 610, DRAM with main frame 106
611st, DC/DC converters 614 and EEPROM 616.The data storage device may also include has flash memory chip respectively
618a and 618b memory plate 104a and 104b.In one embodiment, flash memory chip 618a and 618b are
NAND quick-flash memory chip.As in Fig. 1, multiple passages 112 can be used to control flash memory chip for FPGA controller 610
Each of 618a and 618b, plurality of passage 112 can control one of flash memory chip 618a and 618b or
It is one or more of.
Referring back to Fig. 1, controller 110 (controls as example, including Fig. 4 FPGA controller 410 and Fig. 6 FPGA
Device 610) can it is arranged and configuration with：Control at the order to a variety of different types of flash memory chip 118a and 118b
Reason；Automatically recognize the type of the flash memory chip 118a and 118b on flash memory plate 104a and 104b；And use
The different types of flash memory chip 118a and 118b performs received command.Controller 110 can be configured with logical
Cross and the command translation of different types of flash memory chip is handled into the order into the order of the machine flash memory chip.
Main frame is not needed to take into account the machine flash memory chip order, because controller takes Host Command and optionally by the master
Machine order translated into native flash memory chip order.For example, the reading order received from main frame can be in main frame not
Will the reading order translate into another order in the case of handled by controller 110 so that it can be from specific sale
Operated on the flash memory chip of business.
Reference picture 7, process 700 illustrate controller 110 and can be configured automatically to recognize different types of flash memory
Memory chip simultaneously operates together.Process 700 is included in reception electric power at controller board, wherein the controller board includes arriving
The interface and controller 710 of main frame.The controller may be configured to control a variety of different types of flash memory chips
Command process 710.For example, controller board 102 can receive electric power (Vin) at power module 114.In an exemplary reality
Apply in scheme, power module 114 may include one or more DC/DC converters (for example, Fig. 6 DC/DC converters
614).Controller board 102 may include interface 108 and controller 110.Controller 110 may be configured to control to a variety of inhomogeneities
The flash memory chip 118a and 118b of type command process.
Process 700 may include to multiple flash memory chips of the first memory plate inquiry fixed to first memory plate
One or more characteristics 720.In an exemplary embodiment, controller 110 can be configured with to memory mould
Flash memory chip 118a of the block 120a inquiries fixed to memory plate 104a equipment energy characteristic 720.Described device characteristic can
Including (for example) chip be SLC chips or MLC chips, the chip are NAND or NOR chips, chip selection
Number, the number of block, the number of every piece of page, the speed of the number of every page of byte and the chip.Memory module 120a can
Including serial EEPROM (for example, Fig. 6 EEPROM 620a).
In another exemplary embodiment, controller 110 can be configured directly to inquire about flash memory chip 118a.
For example, controller 110 can be configured to inquire about each of flash memory chip 118a ID pages of device to determine
Equipment energy characteristic.
Process 700 may include one or more characteristics based on the flash memory chip on first memory plate certainly
The type 730 of the flash memory chip is recognized dynamicly.For example, described device characteristic can be used to come from for controller 110
The type of the flash memory chip 118a on memory plate 104a is recognized dynamicly.Flash memory chip 118a can be SLC or
MLC device.Flash memory chip 118a can be NAND chip, NOR chips or other types of chip.Flash memory chip
118a may also come from any one of several different flash memory manufacturers.
Process 700 may include to receive order 740 from the main frame using the interface and use the flash memory core
Piece come perform it is described order 750.For example, controller 110 can be configured is ordered with being received using interface 108 from main frame 106
And the order is performed using flash memory chip 118a.In this way, controller 110 can be configured with automatically with appointing
The biconditional operation of flash memory chip one of what type.After the power-up of data storage device 100, the controller can determine assorted at once
The flash memory chip of type is on the memory plate and then starts with these biconditional operations of memory plate one to perform
The order received from main frame.
In an exemplary embodiment, controller 110 can be based on being confirmed as being present on the memory plate
One or more config updates of the type reception of flash memory chip.For example, controller 110 can determine that certain kinds
The flash memory chip of type is used for one of described memory plate above and this information can be reported back into main frame.Main frame
106 can be delivered to one or more config updates controller 110, the information and configuration that wherein controller 110 can be in Fig. 4
Received at interface module 458 and handle these renewals.
In an exemplary embodiment, controller 110 can be configured automatically to recognize on same memory plate
Different types of flash memory chip.For example, the half in the flash memory chip 118a on memory plate 104a
Can be that second half in the flash memory chip 118 on SLC NAND quick-flash memories chip and memory plate 104a can be
MLC NAND quick-flash memory chips.Controller 110 can be configured to perform these types even on same memory plate
Both flash memory chips order.
In another exemplary embodiment, when controller 110 can be configured to recognize two memory plates from control
Device plate 102 is removed and replaced by new memory plate, the new memory plate can with or can not have a different types of flash
Device chip.In this way, controller 110 realizes the great flexibility of customization data storage device 100 to meet the spy of main frame 106
Fixed application needs.Certain types of flash memory chip can be used, including different types of on same memory plate
Different types of chip on each of chip and/or memory plate, required for meeting the application-specific of main frame 106
Required characteristic.
Reference picture 8, example procedure 800 illustrate the controller and are configured to and the flash memory with different voltages
The biconditional operation of memory chip one.Process 800 may include at controller board receive electric power, wherein the controller board include interface and
The controller and controller includes power module.The controller is configured to multiple flash memories of the control with different voltages
The command process 810 of memory chip.For example, controller board 102 can be configured with from main frame 106 receive electric power (Vin) and
The controller board may include interface 108 and controller 110, and wherein controller 110 may include power module 114.Controller 110
It may be configured to control the command process to multiple flash memory chips with different voltages.For example, controller 110
It may be configured to control the flash memory chip operated with 1.2v/1.8v/3.3v or other voltages.
Process 800 includes determining the voltage 820 of the flash memory chip on first memory plate.For example, control
Device 110 can be configured with the signal level based on the pin on the connector between controller board 102 and memory plate 104a come
Sense the voltage of the flash memory chip.The signal level (for example, logically high and/or logic low packet) may indicate that
Voltage required for flash memory chip 118a.Process 800 includes power module being configured to flash memory chip
Determined voltage operation 830.For example, controller 110 can be configured with based in controller board 102 and memory plate 104a
Between connector on pin at the voltage that senses configure power module 114.In an exemplary embodiment, electric power
Module 114 includes one or more DC/DC converters (for example, Fig. 6 DC/DC converters 614).Can be by power module
114 are set as with described sensing voltage operation.
Process 800 receives order 840 from the main frame including the use of the interface and uses the flash memory chip
To perform the order 850.For example, controller 110 can be configured with using interface 108 from main frame 106 receive order and
The order is performed using flash memory chip 118a.In this way, memory plate 104a and 104b may include with phase
With the chip of voltage, wherein memory plate 104a and 104b is connected to controller board 102.Memory plate 104a and 104b can be with controls
Device plate 102 processed disconnects and replaced by other memory plates with the flash memory chip with different voltages.Controller 110
The different voltages that are configured to automatically to recognize required for the flash memory chip on other memory plates and by electric power
Module 114 is configured to operate with different voltage levels.
The embodiment of various technologies described herein can be with Fundamental Digital Circuit or with computer hardware, solid
Part, software or its combination are implemented.Embodiment can be embodied as computer program product, i.e. visibly be embodied in information carrier
In computer program (for example, being embodied in machine-readable storage device), with by data processing equipment (for example, programmable
Reason device, a computer or multiple computers) perform or control the operation of the data processing equipment.Can be with any type of programming
Language (comprising compiler language or interpretive language) writes computer program (for example, computer program as described above), and
The computer program can be disposed in any form, comprising be deployed as stand-alone program or be deployed as module, component, subroutine or
It is adapted to the other units used in a computing environment.Computer program can be deployed with a computer or positioned at one
It is distributed and at site or across multiple sites by being performed on multiple computers of interconnection of telecommunication network.
Method and step can be performed by one or more programmable processors of execution computer program, to pass through processing
Input data simultaneously produces output and carrys out perform function.Procedure can also be by dedicated logic circuit (for example, FPGA (field-programmables
Gate array) or ASIC (application specific integrated circuit)) perform, and equipment can be embodied as dedicated logic circuit.
For example, being suitably executed the processor of computer program includes both general and special microprocessors, Yi Jiren
Any one or more than one processor of the digital computer of which kind of class.In general, processor will from read-only storage or
Random access memory or both receives instruction and data.The element of computer may include at least one place for execute instruction
Manage device and for one or more of store instruction and data storage arrangement.In general, computer may also include use
In one or more mass storage devices (for example, disk, magneto-optic disk or CD) of data storage or through operatively coupling
Close and passed with transmitting data from one or more than one mass storage device reception data or to it or not only having received data
Send data.It is adapted to the information carrier comprising computer program instructions and data to include the nonvolatile memory of form of ownership, its
Include (for example)：Semiconductor memory system, such as EPROM, EEPROM and flash memory device；Disk, such as
Internal hard or removable disk；Magneto-optic disk；And CD-ROM and DVD-ROM CDs.The processor and memory can be by
Supplemented is incorporated into dedicated logic circuit.
Interacted to provide with user, embodiment may be implemented on computer, and the computer has for described
The display device (for example, cathode-ray tube (CRT) or liquid crystal display (LCD) monitor) of user's display information and the user
The keyboard and indicator device (for example, mouse or trace ball) of input can be provided by it to computer.It can also be used other kinds
The device of class interacts to provide with user；For example, there is provided the feedback to the user can be that any type of sense organ is anti-
Feedback, for example, visual feedback, audio feedback or touch feedback；And the input from the user can receive in any form, its
Include sound, voice or sense of touch.
Embodiment may be implemented in computing system (including aft-end assembly, for example, as data server；Or including centre
Part component, for example, apps server；Or including front end assemblies, for example, can come to hand over embodiment via it with user
Mutual graphical user interface or the client computer of Web browser) or such rear end, any group of middleware or front end assemblies
In conjunction.Component can be interconnected by any digital data communications form or media (for example, communication network).The example of communication network includes
LAN (LAN) and wide area network (WAN), such as internet.
Although having illustrated and having described some features of described embodiment herein, but the technology of art
Personnel can find out many modifications, replacement, change and equivalents now.It will be understood, therefore, that appended claims intend to contain
Cover all such modifications and changes fallen within the scope of the invention.
Claims (6)
1. a kind of data storage device (100), it includes：
Memory plate (104a), the memory plate (104a) include multiple NAND memory chips (118a), and the chip is
The memory chip of single level-cell or multi-level-cell；
Controller board (102) is operatively coupled to the memory plate (104a), wherein the controller board (102) is included now
Field programmable gate array controller (410), the field programmable gate array controller (410) is arranged and configuration is to control
Multiple NAND memory chips (118a) storage operation is stated, and wherein described controller board (102) is physically only
Stand on the memory plate (104a) plate；
Periphery component interconnection high-speed interface (108,408) is operatively coupled to the controller board (102), the peripheral assembly
Connected high-speed interface (108,408) is arranged and configuration is with main frame (106) and the field programmable gate array controller
(410) interface is provided between causes the field programmable gate array controller to pass through the periphery component interconnection high-speed interface
(108,408) with the main frame direct communication；And
Other memory plate (104b), the other memory plate (104b) include multiple NAND memory chips
(118a), the other memory plate (104b) is operatively coupled to the controller board (102), wherein the controller
Plate (102) and the other memory plate (104b) are on themselves independent printed circuit board (PCB), and wherein described control
Device plate (102) processed is disposed in bottom, and the memory plate (104a) and the other memory plate (104b) are arranged
At top；
And wherein：
The controller board (102) and the NAND memory chip (118a, 118b) are arranged and configuration is with using multiple logical
Road (112) communicates,
Each passage of the multiple passage (112) is configured as and one or more NAND memory chips (118a, 118b)
Communication, and
The field programmable gate array controller (410) is configured such that can be by from the order that the main frame (106) receives
The field programmable gate array controller (410) while performed using each in the multiple passage (112).
2. data storage device (100) according to claim 1, wherein the periphery component interconnection high-speed interface (108,
408) periphery component interconnection high speed X4 interfaces are included, or (PCIe) interface includes peripheral group to wherein described periphery component interconnection at a high speed
Part connected high-speed (PCIe) X8 interfaces.
3. data storage device (100) according to claim 1, wherein the controller (102) is arranged and configuration with
The class of the memory chip on the memory plate (104a) is automatically determined when the data storage device (100) powers up
Type.
4. a kind of data storage device (100), it includes：
First plate (104a), first plate (104a) include multiple NAND memory chips (118a)；
Second plate (102), it is operatively coupled to first plate (104a), wherein second plate (102) includes scene
Programmable gate array controller (408), its is arranged and configures to control the memory of the multiple NAND memory chip to grasp
Make, and second plate (102) is the plate for being physically independent from first plate (104a)；
Periphery component interconnection high-speed interface (108,408) is operatively coupled to second plate (102), its arranged and configuration
Cause the field-programmable to provide interface between main frame (106) and the field programmable gate array controller (408)
Gate array controller passes through the periphery component interconnection high-speed interface (108,408) and the main frame (106) direct communication；And
The 3rd other plate, the 3rd other plate is the memory plate for having multiple NAND memory chips (118b)
(104b), the 3rd other plate is operatively coupled to second plate (102), wherein second plate (102) is it
The printed circuit board (PCB) of oneself, wherein second plate (102) be located at first plate (104a) and the 3rd plate (104b) it
Between, first plate and the 3rd plate are in the separate printed circuit boards of themselves；
And wherein：
The controller board (102) and the NAND memory chip (118a, 118b) are arranged and configuration is with using multiple logical
Road (112) communicates,
Each passage of the multiple passage (112) is configured as and one or more NAND memory chips (118a, 118b)
Communication, and
The field programmable gate array controller (410) is configured such that can be by from the order that the main frame (106) receives
The field programmable gate array controller (410) while performed using each in the multiple passage (112).
5. data storage device (100) according to claim 4, wherein the periphery component interconnection high-speed interface (108,
408) periphery component interconnection high speed X4 interfaces are included, or wherein described periphery component interconnection high-speed interface includes periphery component interconnection
High speed X8 interfaces.
6. the data storage device (100) according to one of claim 4 or 5, wherein the NAND memory chip is single
The memory chip of level-cell or multi-level-cell.
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