CN107133192A - High speed loader and pulse counter circuit in a kind of SoC systems - Google Patents
High speed loader and pulse counter circuit in a kind of SoC systems Download PDFInfo
- Publication number
- CN107133192A CN107133192A CN201710328288.9A CN201710328288A CN107133192A CN 107133192 A CN107133192 A CN 107133192A CN 201710328288 A CN201710328288 A CN 201710328288A CN 107133192 A CN107133192 A CN 107133192A
- Authority
- CN
- China
- Prior art keywords
- high speed
- register
- interrupt
- pulse counter
- event
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses the high speed loader in a kind of SoC systems and pulse counter circuit, including high speed input pin, trigger buffering, event input transition detection device, Clock dividers, timer, the fifo queue FIFO1 for storing high speed incoming event temporal information, fifo queue FIFO2, pulse counter and internal interrupt processing module for the step-by-step counting number in stored record setting cycle time.The present invention realizes reading and processing to the temporal information of outside high speed input pin by the interrupt function of the processor core in SoC systems, and realize in setup time to input pulse counting number and reading, it is small with area occupied, it is few using resource, the advantages of cost-effective.
Description
Technical field
The present invention relates to the on-chip system SoC fields in microelectronics technology and large scale integrated circuit, especially mainly
It is related to applied to the record high speed incoming event temporal information realized based on interrupt mechanism in SoC systems and continuously to configuration
Cycle time in pulse carry out tally function IP modular circuits.
Background technology
Often there is high speed loader to record high speed incoming event temporal information function in single-chip microcomputer, and in some hardware
In circuit system, often require that to certain pulse signal progress pulse number counting all the way in setting time.Existing technology is often
Realized in PCB hardware circuits by function of the MCU, and as integrated circuit collection increases complicated with circuit design function on a large scale
Degree is improved, and can be realized by SoC on-chip systems and be carried out time record to the event of high speed input and realize setting cycle time
Interior input pulse tally function；And by realizing that there is circuit area reduction, cost-effective, convenience easily to use in SoC systems
Etc. characteristic.
For example in patent《A kind of wireless pulses synchronous sampling method》, authorize public number：In the texts of CN 104730483A mono-,
Propose a kind of method that check pulse is lost；This paper scheme of the invention implementation method is different from the patent, mainly realizes to SoC systems
Certain external terminal of system continuously carries out pulse number counting, and the design is the circuit applied to SoC system regions.
In paper《Detection method research of the pulse signal in target seeker test》, author's (Zeng Qingzhong, what Ho Geok Choo), proposition
Devise internal comprising anti-phase scaling circuit, optical coupling isolation circuit, shaping buffering electricity in a kind of pulse-scaling circuit, circuit
The part of road 3 is constituted.The method of the paper is not suitable for being applied to realizing in SoC systems, different from the step-by-step counting of the design proposition
Circuit.
In paper《Inertial navigation component multi-pulse counting system design》(author：Zheng Yi, Zhang Zhi's text) in propose to set using USB
Standby and FPGA carries out continuous counters to 24 road pulse signals, and using more than resource and circuit is complicated and circuit cost is high, it can not
Apply in SoC systems, its implementation is different with the scheme that the design is proposed.
Find not proposing also that input at a high speed is realized in design in SoC systems in existing document by consulting and contrasting
The circuit arrangement of function and step-by-step counting function.It can be applied to set forth herein one kind in SoC systems, by SoC systems
The interrupt response mechanism of processor core is realized to be recorded to the temporal information of the high speed incoming event of SoC some or several pins,
And realize step-by-step counting function in cycle setup time；Pass through the interrupt function realization pair of the processor core in SoC systems
The reading and processing of the temporal information of outside high speed input pin, and realize in setup time to input pulse counting number and reading
Take.It has area occupied small, few using resource, the characteristic such as cost-effective.
The content of the invention
It is used to record the time that a certain external event occurs a kind of system suitable for SoC of present invention design, realizes record
High speed incoming event；And it can realize that the continuous pulse to the input pin in the cycle time of setting carries out counting work(
Energy.
In order to solve the above technical problems, the present invention provides high speed loader and pulse counter electricity in a kind of SoC systems
Road.
High speed loader and pulse counter circuit in a kind of SoC systems, it is characterized in that,
Including high speed input pin, trigger buffering, event input transition detection device, Clock dividers, timer, it is used for
Store the fifo queue FIFO1 of high speed incoming event temporal information, set the pulse in cycle time for stored record
Count fifo queue FIFO2, pulse counter and the internal interrupt processing module of number；
High speed input pin is to be connected to SoC top layers to be used for the input of external event signal；
Trigger buffering enters row buffering and filtering to the signal inputted by high speed input pin；
Event inputs transition detection device, to the event detection of outside hopping edge；
Clock dividers are divided to clock；
The clock cycle that timer is exported using Clock dividers, as the operation clock cycle, is high speed loader and step-by-step counting
Temporal information benchmark is provided inside device；
It is used to access high speed incoming event hair for storing the fifo queue FIFO1 of high speed incoming event temporal information
The raw time；Fifo queue FIFO1 enable of writing detects event control generation by event input transition detection device, and controls
System writes current timer moment value to fifo queue FIFO1；
Pulse counter, is recorded to the pulse number of the high speed input pin in the cycle time section of configuration；
The fifo queue FIFO2 of the step-by-step counting number in cycle time is set for stored record, for accessing
The pulse number of input pin in period configuration cycle；When pulse counter sends counting end mark, control simultaneously
The pulse number of record is write into fifo queue FIFO2；
Internal interrupt processing module is used for interrupt requests and interrupt clear.
Also include the register for needing to configure, including：Timing control register, trap mode configuration register, timer
Time value register, logout temporal information register, the full status register of FIFO1 skies, FIFO1 reset empty register,
Timer overflows interrupt flag register, event detection interrupt flag register, timer and overflows interrupt clear register, configuration
Time cycle in step-by-step counting terminate interrupt flag register, the full status register of FIFO2 skies, need count pulse number
Time cycle configuration register, step-by-step counting starting enable and end interrupt enable register, reflection cycle time in arteries and veins
Punching counts number register and FIFO2 reseting registers.
Event inputs transition detection device by CAPP and CAPN configurations in trap mode configuration register to outside high
The level change type of fast input pin carries out sample record.
When there is external event generation, the event detection interrupt flag bit in event detection interrupt flag register is set to
Logic 1 simultaneously produces an interrupt requests；When the processor core in SoC systems turns to interrupt service routine, serviced by interrupting
This interrupt identification of program reset；
When the microprocessor in SoC receives the value that interrupt signal reads logout temporal information register, it can be read
The time value at moment occurs for corresponding incoming event, reads the time information data stored in a fifo queue FIFO1 just
Send out one.
Clock dividers are divided according to the value for the position that internal work clock division coefficient is controlled in timing control register
Frequently.
After the position of control counter/timer operation of timing control register is enabled, timer opens operation, and
The internal time information benchmark of high speed loader and pulse counter is all provided by timer.
After it is 1 to configure the initial signal in step-by-step counting starting enable and the OIER terminated, being loaded into needs
The value of the time cycle configuration register of count pulse number is wanted, and is loaded into the initial value of now timer simultaneously, works as timer
Timing to timer initial value+need the value of time cycle of count pulse number when, send end mark；If enabled
In the case of step-by-step counting end interrupt, the end interrupt signal of step-by-step counting full time configuration cycle is drawn high, and delivers to SoC systems
Processor in system.
When internal interrupt processing module is that timer count value overflows interrupt signal, event detection interrupt signal, configuration
Between the tunnel of interrupt signal three after step-by-step counting terminates in the cycle interrupt mutually or send interrupt requests to the interruption of SoC systems after logic
Controller module；Internal interrupt processing module receives processor core in SoC systems to high speed loader and pulse counter
Interrupt clear signal after interrupt requests response, and remove corresponding interrupt requests.
High speed loader and pulse counter are integrated in SoC systems as a general IP module to be used, and is at a high speed
The register address space of SoC systems on the internal register distribution piece of loader and pulse counter；Pass through the piece of SoC systems
The internal register of upper bus and EBI, configuration and read-write high speed loader and pulse counter.
Compared with prior art, beneficial effect of the present invention：
1st, can be as the general purpose I P module in SoC systems, mainly applied in SoC systems, transplantability is high, versatility
By force.
2nd, it can be integrated in SoC systems, area occupied is small, save circuit cost, using resource-constrained, simple easily to realize.
3rd, apply in integrated circuit and SoC system regions, the document that can be consulted at present has not found proposition and applied in SoC
The high speed loader and pulse counter in field.
4th, indoor design can store certain capture events moment temporal information and pulsimeter is several in memory cycle time
Several fifo modules, prevents CPU from can not timely respond to interrupt the value for the event time information for overriding storage or in cycle time
The value of the pulse number of pin input.
If the 5, only required when realizing step-by-step counting function, without enabling interruption that each detecting event sends to SoC systems
The processor of system, it is that step-by-step counting function can be achieved to take less processor control resource.
Brief description of the drawings
Fig. 1 high speeds loader and pulse counter system block diagram；
Fig. 2 events input transition detection device circuit block diagram；
Fig. 3 pulse counter structured flowcharts；
Fig. 4 interruption processing module circuit simplified schematic diagrams.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention
Technical scheme, and can not be limited the scope of the invention with this.
Technical solution of the present invention is further illustrated below in conjunction with the accompanying drawings, if demand multipath high-speed loader and pulsimeter
Number device circuit can be by being multiplexed high speed loader and pulse counter IP circuit realirations in SoC systems.
The high speed loader and pulse counter circuit of design can be integrated in SoC systems as a general IP module
In use.Needed in circuit design for SoC on the high speed loader of design and the internal register distribution piece of pulse counter
The register address space of system；By the on-chip bus and EBI of SoC systems, the microprocessor in SoC can be correct
Configuration and the internal register of read-write high speed loader and pulse counter, and by the interrupt control unit in SoC systems high
The processor core that the interrupt signal of fast loader and pulse counter is delivered in the processor core of SoC systems, SoC systems passes through phase
Answer interrupt requests for transmitting of interrupt routine processing etc..
The high speed loader of design and the system architecture of pulse counter circuit mainly include high speed loader pin, triggering
Device buffering, event input transition detection device, Clock dividers, timer, for storing high speed incoming event temporal information
FIFO1, the FIFO2 for the step-by-step counting number in stored record setting cycle time, pulse counter, internal interrupt processing
Module etc..High speed loader pin is mainly the input pin of external event signal；Trigger buffering is mainly used for outside
Input pin signal carries out burr filtering and buffering；Event input transition detection device mainly (including negative is jumped to outside hopping edge
It is change, positive transition, double along saltus step) event detection；Clock dividers are according to the divide ratio configured inside timing mode register
The clock division selection output of 1,2,4,8 coefficients is realized in selection；Timer is mainly the clock for dividing out with Clock dividers
For time of day counting and timing function；Fifo queue FIFO1 mainly completes the temporal information progress to event generation time
Storage；Fifo queue FIFO2 mainly completes to read the pulse number of external terminal in storage setting cycle time；Pulsimeter
Number device mainly completes the counting of the pulse number of the external terminal in setting time；Internal interrupt processing module is mainly completed at a high speed
The interrupt requests and interrupt clear function of loader and pulse counter circuit.
The high speed loader and pulse counter of design need some main registers of configuration mainly to include：Timing control is posted
Storage, trap mode configuration register, timer time value register, logout temporal information register, the full shape of FIFO1 skies
State register, FIFO1 reset empty register, timer overflow interrupt flag register, event detection interrupt flag register,
Timer overflows interrupt clear register, the interrupt flag register that step-by-step counting terminates in the time cycle of configuration, inside
FIFO2 skies expire status register (deposit and count number), need the time cycle configuration register of count pulse number (should configure big
In 1 numerical value), step-by-step counting starting enable and end interrupt enable register, reflection cycle time in step-by-step counting number
Register, inside FIFO2 reseting registers (depositing counting number).
The high speed loader and pulse counter circuit system block diagram wherein designed is as shown in figure 1, main circuit function is
Realize and the temporal information of high speed incoming event is recorded, in addition also by enabling arteries and veins of the control configuration unlatching to input pin
Rush the logic function that number is counted.Circuit indoor design mainly divides high speed incoming event temporal information to record and incoming event
Pulse number count two large divisions's function, high speed loader be mainly complete external input signal along event capture and
Generation moment temporal information is recorded, and pulse counter is mainly the tally function for completing pulse number in time configuration cycle.
It mainly includes high speed input pin, trigger buffering, event input transition detection device, Clock dividers, timing
Device, the FIFO1 for storing high speed incoming event temporal information, the pulsimeter set for stored record in cycle time are several
Several FIFO2, pulse counter, internal interrupt processing module etc..
The major function of each module and internal main circuit structure are as follows：
High speed input pin is to be directly connected to SoC top layers and can directly input the pin of signal；
Trigger buffering is that input signal enters row buffering and filtering burr by this trigger；
Event inputs transition detection device circuit diagram as shown in Fig. 2 passing through the CAPP in trap mode configuration register
Sample record is carried out to the level change type of outside high speed input pin with CAPN configurations, incoming event is divided into：Low level
To high level (positive edge), high level to low level (negative edge) or any change (positive edge or negative edge).When event occurs,
Event detection interrupt flag bit in event detection interrupt flag register is set to logic 1 and produces an interrupt requests.When
When processor core in SoC turns to interrupt service routine, this interrupt identification is removed by interrupt service routine.When micro- in SoC
The corresponding incoming event generation moment can be read in the value that the interrupt signal that processor receives reads logout temporal information register
Time value, read the time information data that stores in a FIFO1 and just send out one.
The conventional Clock dividers of Clock dividers, timer and current digital circuit, timer circuit structure are similar,
This is repeated no more, and Clock dividers are main according to the position that internal work clock division coefficient is controlled in timing control register
Value is divided；The clock cycle that timer is exported using Clock dividers as the operation clock cycle, when timing control register
After the position enable for controlling internal counter/timer operation, timer internal opens operation, and high speed loader and pulsimeter
The internal time information benchmark of number device is all provided by the timer of indoor design.
For store the FIFO1 of high speed incoming event temporal information be mainly used to access high speed incoming event occurs when
Between；FIFO1 enable (we) of writing detects event control generation by event input transition detection device, and controls to write current timing
Device moment value is to FIFO1.
Pulse counter structured flowchart is as shown in figure 3, high speed input pipe in the main complete cycle time section being organized in pairs
The pulse number of pin is recorded；Starting letter in configuration register step-by-step counting starting and the OIER terminated
Number be that after 1, inside is loaded into the value for the time cycle configuration register for needing count pulse number, and it is simultaneously internal be loaded into it is now electric
The initial value of road timer internal, when the initial value+need the time cycle of count pulse number of timer timing to timer
Value when, send end mark；If in the case of enabling pulse counts end interrupt, when a configuration cycle is expired in step-by-step counting
Between at the end of, interrupt signal is drawn high, the processor delivered in SoC systems.In pulse counting process, while to configuration cycle
The event frequency of detection is counted in time, that is, completes the step-by-step counting function situation in setup time, when end mark
When will occurs, the pulse number of counting is stored in FIFO2.
When the FIFO2 for setting the step-by-step counting number in cycle time for stored record is mainly used to the access configuration cycle
Between input pin in section pulse number；When pulse counter sends counting end mark, while controlling write-in record
Pulse number is into FIFO2.
Internal interrupt processing module circuit simplified schematic diagram is as shown in figure 4, mainly timer internal count value overflows interruption
Signal, event detection interrupt signal, the tunnel of interrupt signal three after step-by-step counting terminates in cycle setup time are interrupted mutually or logic
Interrupt requests are sent afterwards to the interrupt control unit module of SoC systems；Interruption processing module reception processing device inside other circuit
Check the interrupt clear signal after the interrupt requests response of high speed loader and pulse counter and remove corresponding interrupt requests.
The main register detailed content of the configuration wherein needed is listed as follows：
(1) timing control register
The timing control register of table 1
(2) trap mode configuration register
The trap mode configuration register of table 2
(3) timer time value register
The value of the counter/timer of table 3
| Bit field | Access type | Function is described |
| 31-0 | Read | Reflect timer internal current time time value |
(4) logout temporal information register
The logout temporal information register of table 4
| Bit field | Access type | Function is described |
| 31-0 | Read | Register reflects that the value of the 32 bit timing devices at moment occurs along saltus step for event |
When the event of input occurs along during saltus step, catching in the value deposit FIFO1 of timer, when processor core receives this
During interruption, logout temporal information register is read, interrupt signal is also processed and dragged down.
(5) the full status register of FIFO1 skies
The full status register of table 5FIFO1 skies
| Bit field | Access type | Function is described |
| 31-12 | - | Retain |
| 1 | Read | Internal FIFO1 full scales will |
| 0 | Read | Internal FIFO1 skies mark |
Two 32X32 of circuit indoor design fifo queue register FIFO1, FIFO1 is for storing event
Temporal information.If processor core can at most record 32 events in the case where not reading away, if writing FIFO1 all over, reading
Before information, the event information further occurred is not re-recorded.Pass through FIFO1 empty full scale will, it can be verified that the data in FIFO1
Validity.(6) FIFO1, which resets, empties register
Table 6FIFO1, which resets, empties register
| Bit field | Access type | Function is described |
| 31-1 | - | Retain |
| 0 | Write | 0：FIFO1 normal works；1：Reset FIFO1 register queues. |
(7) timer overflows interrupt flag register
The timer of table 7 overflows interrupt flag register
(8) event detection interrupt flag register
The event detection interrupt flag register of table 8
(9) timer overflows interrupt clear register
Write any value and remove counter overflow interruption to this register；Write-only register.
(10) interrupt flag register that step-by-step counting terminates in the time cycle of configuration
The step-by-step counting of table 9 terminate after interrupt identification
(11) the full status register of FIFO2 skies (depositing counting number)
The full status register of the inside FIFO2 of table 10 skies
The 32X32 of step-by-step counting number fifo queue register FIFO2 is read in another access, is matched somebody with somebody for recording
Put the pulse number of cycle time inside counting.If can at most record 32 data in the case of not reading away information, in FIFO2 meters
Under full state, if do not read, the pulse number that FIFO2 is recorded below can be lost, by FIFO2 empty full scale will, can be demonstrate,proved
Data validity in real FIFO2.
(12) the time cycle configuration register of count pulse number is needed
Table 11 needs the time cycle of count pulse number
| Bit field | Access type | Function is described |
| 31-0 | R/W | Time configuration cycle of step-by-step counting number |
(13) step-by-step counting starting is enabled and end interrupt enables register
The step-by-step counting number of table 12 is originated and end interrupt enables register
(14) the step-by-step counting number register in reflection cycle time
The step-by-step counting number register of table 13
| Bit field | Access type | Function is described |
| 31-0 | Read | Reflect step-by-step counting numerical value in time configuration cycle |
When pulse counter, which is calculated, completes the pulse number received in time configuration cycle, a meter after calculating terminates
In the value deposit FIFO2 of the count pulse number of calculation.
After the pulse number in time configuration cycle has been calculated, in the case of permission/enable is interrupted, when the place in SoC
When reason device core receives interruption, the value of step-by-step counting number register is read, interrupt signal is also processed and dragged down.
(15) FIFO2 reseting registers (depositing counting number)
The inside FIFO2 reseting registers of table 14
| Bit field | Access type | Function is described |
| 31-1 | - | Retain |
| 0 | Write | 0：FIFO normal works；1：Reset fifo register queue. |
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these improve and deformed
Also it should be regarded as protection scope of the present invention.
Claims (9)
1. high speed loader and pulse counter circuit in a kind of SoC systems, it is characterized in that,
Including high speed input pin, trigger buffering, event input transition detection device, Clock dividers, timer, for storing
The fifo queue FIFO1 of high speed incoming event temporal information, for stored record set cycle time in step-by-step counting
Fifo queue FIFO2, pulse counter and the internal interrupt processing module of number；
High speed input pin is to be connected to SoC top layers to be used for the input of external event signal；
Trigger buffering enters row buffering and filtering to the signal inputted by high speed input pin；
Event inputs transition detection device, to the event detection of outside hopping edge；
Clock dividers are divided to clock；
The clock cycle that timer is exported using Clock dividers, as the operation clock cycle, is in high speed loader and pulse counter
Portion provides temporal information benchmark；
It is used to access the generation of high speed incoming event for storing the fifo queue FIFO1 of high speed incoming event temporal information
Time；Fifo queue FIFO1 enable of writing detects event control generation by event input transition detection device, and controls to write
Enter current timer moment value to fifo queue FIFO1；
Pulse counter, is recorded to the pulse number of the high speed input pin in the cycle time section of configuration；
The fifo queue FIFO2 of the step-by-step counting number in cycle time is set for stored record, for access configuration
The pulse number of input pin in cycle time section；When pulse counter sends counting end mark, while controlling write-in
The pulse number of record is into fifo queue FIFO2；
Internal interrupt processing module is used for interrupt requests and interrupt clear.
2. high speed loader and pulse counter circuit in a kind of SoC systems according to claim 1, it is characterized in that,
Also include the register for needing to configure, including：Timing control register, trap mode configuration register, timer time
Value register, logout temporal information register, the full status register of FIFO1 skies, FIFO1 reset and empty register, timing
Device overflow interrupt flag register, event detection interrupt flag register, timer overflow interrupt clear register, configuration when
Between step-by-step counting terminates in the cycle interrupt flag register, the full status register of FIFO2 skies, need count pulse number when
Between period assignment register, step-by-step counting starting enable and end interrupt enable register, reflection cycle time in pulsimeter
Several several registers and FIFO2 reseting registers.
3. high speed loader and pulse counter circuit in a kind of SoC systems according to claim 2, it is characterized in that,
Event input transition detection device is defeated to outside high speed by CAPP and CAPN configurations in trap mode configuration register
The level change type for entering pin carries out sample record.
4. high speed loader and pulse counter circuit in a kind of SoC systems according to claim 3, it is characterized in that,
When there is external event generation, the event detection interrupt flag bit in event detection interrupt flag register is set to logic
1 and produce an interrupt requests；When the processor core in SoC systems turns to interrupt service routine, pass through interrupt service routine
Remove this interrupt identification；
When the microprocessor in SoC receives the value that interrupt signal reads logout temporal information register, it can be read corresponding
The time value at moment occurs for incoming event, reads the time information data stored in a fifo queue FIFO1 and just sends out
One.
5. high speed loader and pulse counter circuit in a kind of SoC systems according to claim 2, it is characterized in that,
Clock dividers are divided according to the value for the position that internal work clock division coefficient is controlled in timing control register.
6. high speed loader and pulse counter circuit in a kind of SoC systems according to claim 2, it is characterized in that,
After the position of control counter/timer operation of timing control register is enabled, timer opens operation, and inputs at a high speed
The internal time information benchmark of device and pulse counter is all provided by timer.
7. high speed loader and pulse counter circuit in a kind of SoC systems according to claim 2, it is characterized in that,
After it is 1 to configure the initial signal in step-by-step counting starting enable and the OIER terminated, loading needs to count arteries and veins
The value of the time cycle configuration register of number is rushed, and is loaded into the initial value of now timer simultaneously, when timer timing is to calmly
When device initial value+need the value of time cycle of count pulse number when, send end mark；If counted in enabling pulse
In the case of end interrupt, the end interrupt signal of step-by-step counting full time configuration cycle is drawn high, the place delivered in SoC systems
Manage device.
8. high speed loader and pulse counter circuit in a kind of SoC systems according to claim 2, it is characterized in that,
Internal interrupt processing module is that timer count value overflows interrupt signal, event detection interrupt signal, in the time cycle of configuration
Interrupt mutually or send interrupt requests to the interrupt control unit mould of SoC systems after logic in the tunnel of interrupt signal three after step-by-step counting terminates
Block；Internal interrupt processing module receives interrupt requests of the processor core in SoC systems to high speed loader and pulse counter
Interrupt clear signal after response, and remove corresponding interrupt requests.
9. the high speed loader and pulse counter circuit in a kind of SoC systems according to any of the above claim, its
It is characterized in that high speed loader and pulse counter are integrated in SoC systems as a general IP module and used, and are that high speed is defeated
Enter the register address space of SoC systems on the internal register distribution piece of device and pulse counter；On piece by SoC systems
The internal register of bus and EBI, configuration and read-write high speed loader and pulse counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710328288.9A CN107133192A (en) | 2017-05-11 | 2017-05-11 | High speed loader and pulse counter circuit in a kind of SoC systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710328288.9A CN107133192A (en) | 2017-05-11 | 2017-05-11 | High speed loader and pulse counter circuit in a kind of SoC systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107133192A true CN107133192A (en) | 2017-09-05 |
Family
ID=59732790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710328288.9A Pending CN107133192A (en) | 2017-05-11 | 2017-05-11 | High speed loader and pulse counter circuit in a kind of SoC systems |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107133192A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108555906A (en) * | 2018-04-09 | 2018-09-21 | 重庆东渝中能实业有限公司 | Control method, device and the robot of robot |
| CN109698696A (en) * | 2017-10-24 | 2019-04-30 | 比亚迪股份有限公司 | Clock division method, apparatus, system, system on chip and storage medium |
| CN109831205A (en) * | 2019-01-16 | 2019-05-31 | 厦门忻德信息技术有限公司 | A kind of pulse counting method based on SoC |
| CN110189776A (en) * | 2018-02-23 | 2019-08-30 | 爱思开海力士有限公司 | Read overtime manager and the storage system including reading overtime manager |
| CN112650616A (en) * | 2021-01-05 | 2021-04-13 | 上海擎昆信息科技有限公司 | Interrupt detection method, device and system |
| CN116559844A (en) * | 2023-05-18 | 2023-08-08 | 杭州宇称电子技术有限公司 | Photon time recording ranging circuit, control method and application thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070082817A (en) * | 2006-02-18 | 2007-08-22 | 삼성전자주식회사 | Asynchronous fifo using valid bit |
| CN102176199A (en) * | 2011-01-28 | 2011-09-07 | 中国科学院西安光学精密机械研究所 | True random number generation method and device |
| CN105117200A (en) * | 2015-06-30 | 2015-12-02 | 广西科技大学 | Counter IP core connected with 16-bit microprocessor application system, and counter counting control realization method thereof |
| CN105760330A (en) * | 2016-02-22 | 2016-07-13 | 中国兵器工业集团第二四研究所苏州研发中心 | Multichannel frequency acquisition circuit with APB interface |
-
2017
- 2017-05-11 CN CN201710328288.9A patent/CN107133192A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070082817A (en) * | 2006-02-18 | 2007-08-22 | 삼성전자주식회사 | Asynchronous fifo using valid bit |
| CN102176199A (en) * | 2011-01-28 | 2011-09-07 | 中国科学院西安光学精密机械研究所 | True random number generation method and device |
| CN105117200A (en) * | 2015-06-30 | 2015-12-02 | 广西科技大学 | Counter IP core connected with 16-bit microprocessor application system, and counter counting control realization method thereof |
| CN105760330A (en) * | 2016-02-22 | 2016-07-13 | 中国兵器工业集团第二四研究所苏州研发中心 | Multichannel frequency acquisition circuit with APB interface |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698696A (en) * | 2017-10-24 | 2019-04-30 | 比亚迪股份有限公司 | Clock division method, apparatus, system, system on chip and storage medium |
| CN110189776A (en) * | 2018-02-23 | 2019-08-30 | 爱思开海力士有限公司 | Read overtime manager and the storage system including reading overtime manager |
| CN110189776B (en) * | 2018-02-23 | 2023-02-24 | 爱思开海力士有限公司 | Read timeout manager and memory system including the same |
| CN108555906A (en) * | 2018-04-09 | 2018-09-21 | 重庆东渝中能实业有限公司 | Control method, device and the robot of robot |
| CN109831205A (en) * | 2019-01-16 | 2019-05-31 | 厦门忻德信息技术有限公司 | A kind of pulse counting method based on SoC |
| CN112650616A (en) * | 2021-01-05 | 2021-04-13 | 上海擎昆信息科技有限公司 | Interrupt detection method, device and system |
| CN112650616B (en) * | 2021-01-05 | 2024-07-05 | 上海擎昆信息科技有限公司 | Interrupt detection method, device and system |
| CN116559844A (en) * | 2023-05-18 | 2023-08-08 | 杭州宇称电子技术有限公司 | Photon time recording ranging circuit, control method and application thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107133192A (en) | High speed loader and pulse counter circuit in a kind of SoC systems | |
| EP2807567B1 (en) | Systems and methods for dynamic priority control | |
| CN104321758B (en) | Arbitrating memory access via a shared memory fabric | |
| CN104102150B (en) | sensor polling unit for microprocessor integration | |
| GB2224419A (en) | Apparatus for queuing requests and replies on a pipelined packet bus | |
| US20120226841A1 (en) | Read stacking for data processor interface | |
| CN101799321A (en) | Intelligent vibration monitor system | |
| CN103870245B (en) | Tracking a relative arrival order of events being stored in multiple queues using a counter | |
| US20160196231A1 (en) | System and method for bus bandwidth management in a system on a chip | |
| CN106372008A (en) | Data caching method and device | |
| CN116089343A (en) | AXI-based data storage method, device, storage medium and equipment | |
| EP1865415A1 (en) | Methods and system for providing low latency and scalable interrupt collection | |
| CN113900975B (en) | Synchronous FIFO | |
| CN110399219B (en) | Memory access method, DMC and storage medium | |
| US20240244406A1 (en) | Device, system and method for synchronizing of data from multiple sensors | |
| CN106776374A (en) | A kind of efficient data way to play for time based on FPGA | |
| EP2133797B1 (en) | Dma transfer device and method | |
| JP5239769B2 (en) | Request order control system, request order control method, and request order control program | |
| CN101667448B (en) | Memory access control device and relevant control method thereof | |
| CN104407367B (en) | Improve the apparatus and method of satellite navigation terminal receiver baseband signal disposal ability | |
| CN110688238B (en) | Method and device for realizing queue of separated storage | |
| EP1393180B1 (en) | Method and apparatus for gathering queue performance data | |
| CN207835492U (en) | A kind of Double buffer carrier wave demodulation system | |
| CN101118533A (en) | Algorithm entity verification system and method | |
| CN106445842B (en) | A kind of data buffer and data cache method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170905 |