CN105788636A - EMMC controller based on parallel multichannel structure - Google Patents
EMMC controller based on parallel multichannel structure Download PDFInfo
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- G11C16/00—Erasable programmable read-only memories
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- G11C16/10—Programming or data input circuits
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Abstract
The invention relates to an eMMC controller based on a parallel multichannel structure. The eMMC controller comprises an ahb bus configuration register module ahb_rgf, at least two ahb bus data transmission modules ahb_mst and single-channel control modules Channel of which the quantity is as same as that of ahb_mst, wherein a CPU is used for configuring a channel transmission mode, transmission command, transmission unit and transmission quantity through ahb_rgf for operation on the eMMC controller in Software; ahb_mst is responsible for reading and writing data between the interior of the eMMC controller and a System bus; Channel is responsible for finishing assembling and disassembling of protocol formats of command information and data information and finishing command and data interaction between the eMMC controller and an eMMC part. The controller can flexibly switch the single-channel/multi-channel work mode of the eMMC controller according to different application scenes.
Description
Technical field
The present invention relates to a kind of eMMC controller based on parallel multi-channel structure, belong to microelectronics technology.
Background technology
The storage product such as current USB flash disk, SSD solid state hard disc, mostly adopt NANDFLASH as non-volatile memory medium, by the drive software that NAND FLASH controller design in master control is corresponding, control NAND FLASH controller interface circuit and produce associative operation order, complete the operations such as the reading to NANDFLASH, write, erasing.But, along with the continuous lifting of NANDFLASH manufacturing process process, bring the lifting of NANDFLASH performance, for instance show that page read times reduces, programming time reduces, the aspect such as functional interleaving in sheet；Simultaneously as each NANDFLASH develops the reason that performance differs, communication protocol is inconsistent, relevant hardware and driver are required for the product according to every company and technical characteristic re-starts design, add the research and development of products cycle.
Therefore, a kind of embedded multi-media card (EmbeddedMultiMediaCard is called for short eMMC) is widely used in the movable equipment such as mobile phone, panel computer.EMMC adopts unified MMC standard interface, and high density NANDFLASH and MMCcontroller is encapsulated in a bga chip.For FLASH characteristic, interiors of products has contained FLASH management technique, the technology such as including error detector and correction, abrasion equilibrium, bad block management, power down protection.User has only to design corresponding eMMC controller and driver, can complete the management for data storage.But, along with eMMC uses the expansion of scope, single channel transmission performance can not meet the requirement of high bandwidth storage system.
Summary of the invention
The present invention is in order to overcome the deficiency of above technology, provide a kind of eMMC controller based on parallel multi-channel structure, this eMMC controller can according to different application scenarios, switch the single channel/multiple channel operation pattern of eMMC controller flexibly, ensure motility and the high bandwidth of eMMC controller: transmit under operator scheme at single channel, each passage completes different orders, and eMMC controller has very strong motility；Under channel transmission operator scheme, each passage completes identical order, and eMMC controller can reach maximum transmission speed.
The present invention overcomes its technical problem be the technical scheme is that
A kind of eMMC controller based on parallel multi-channel structure, including ahb bus configuration register module ahb_rgf, at least 2 ahb bus data transfer module ahb_mst and the single channel control module Channel equal with ahb_mst quantity；Described ahb_rgf is connected with drive software Software by system bus Systembus, and channel transfer pattern, transmission order, unit of transfer, transmission quantity will be configured in Software by CPU by the operation of eMMC controller by ahb_rgf；Described each ahb_mst is connected with memorizer memory by system bus Systembus, and ahb_mst has been responsible for that eMMC controller is internal and the read and write operation of data between system bus Systembus；One end of described each Channel connects with ahb_rgf and corresponding ahb_mst, the other end is connected with corresponding outside eMMC device, described eMMC device is equal with the quantity of Channel, Channel has been responsible for the encapsulation of the protocol format of command information, data message and has disassembled, and completes the order between eMMC controller and eMMC device and data interaction.
According to currently preferred, described ahb_mst, Channel and eMMC device are 4, ahb_mst includes ahb_mst0, ahb_mst1, ahb_mst2 and ahb_mst3, Channel includes Channel0, Channel1, Channel2 and Channel3, and eMMC device includes eMMC0, eMMC1, eMMC2 and eMMC3；nullOne end of ahb_rgf is connected on Systembus、The other end and Channel0、Channel1、One end of Channel2 and Channel3 connects respectively，Channel0、Channel1、One end of Channel2 and Channel3 also respectively with ahb_mst0、ahb_mst1、One end correspondence of ahb_mst2 and ahb_mst3 connects，ahb_mst0、ahb_mst1、The other end of ahb_mst2 and ahb_mst3 is connected on Systembus，Channel0、Channel1、The other end of Channel2 and Channel3 respectively with eMMC0、eMMC1、EMMC2 and eMMC3 correspondence connects.
According to currently preferred, when operator scheme is single channel transmission, in eMMC controller, logical address 0 is corresponding with eMMC device physics storage address 0, in eMMC controller, logical address 1 is corresponding with eMMC device physics storage address 1, in eMMC controller, logical address 2 is corresponding with eMMC device physics storage address 2, and in eMMC controller, logical address 3 is corresponding with eMMC device physics storage address 3；Assume that four passages enable simultaneously, and each passage 4 eMMC devices of mounting, then four passage corresponding tetra-districts of P0, P1, P2, P3 respectively, described P0 district includes eMMC0_0, eMMC0_1, eMMC0_2 and eMMC0_3, P1 district includes eMMC1_0, eMMC1_1, eMMC1_2 and eMMC1_3, P2 district includes eMMC2_0, eMMC2_1, eMMC2_2 and eMMC2_3, and P3 district includes eMMC3_0, eMMC3_1, eMMC3_2 and eMMC3_3, and mode cumulative in order completes the extension of memory capacity.
According to currently preferred, when operator scheme is channel transmission, in eMMC controller, logical address 0 is corresponding with eMMC device 0_0 physical storage address 0, in eMMC controller, logical address 1 is corresponding with eMMC device 1_0 physical storage address 0, in eMMC controller, logical address 2 is corresponding with eMMC device 2_0 physical storage address 0, and in eMMC controller, logical address 3 is corresponding with eMMC device 3_0 physical storage address 0；Assume that four passages enable simultaneously, and each passage 4 eMMC devices of mounting, then four passage corresponding tetra-districts of P0, P1, P2, P3 respectively, described P0 district includes eMMC0_0, eMMC1_0, eMMC2_0 and eMMC3_0, P1 district includes eMMC0_1, eMMC1_1, eMMC2_1 and eMMC3_1, P2 district includes eMMC0_2, eMMC1_2, eMMC2_2 and eMMC3_2, P3 district includes eMMC0_3, eMMC1_3, eMMC2_3 and eMMC3_3, completes the extension of memory capacity according to the mode of number of channels × 4.
The invention has the beneficial effects as follows:
1, the present invention can according to different application scenarios, switch the single channel/multiple channel operation pattern of eMMC controller flexibly, ensure motility and the high bandwidth of eMMC controller: transmitting under operator scheme at single channel, each passage completes different orders, and eMMC controller has very strong motility；Under channel transmission operator scheme, each passage completes identical order, and eMMC controller can reach maximum transmission speed.
2, eMMC array extension is simple, transmits under operator scheme at single channel, and mode cumulative in order completes the extension of memory capacity；Under channel transmission operator scheme, complete the extension of memory capacity according to the mode of the number of mounting eMMC device in number of channels × each passage, it is ensured that eMMC controller optimum performance.
3, under channel transmission operator scheme, it may be achieved maximized Coutinuous store bandwidth, ensure that the load balancing between each eMMC device, it is adaptable to the occasion that stability, memory capacity and bandwidth requirement is higher simultaneously.
Accompanying drawing explanation
Fig. 1 is the present invention structural representation based on the eMMC controller of parallel multi-channel structure.
Fig. 2 is the structural representation of data stream under single channel operator scheme of the present invention.
Fig. 3 is that the present invention is based on eMMC logic array architecture schematic diagram under single channel operator scheme.
Fig. 4 is the structural representation of data stream under multi-channel operation pattern of the present invention.
Fig. 5 is that the present invention is based on eMMC logic array architecture schematic diagram under multi-channel operation pattern.
Detailed description of the invention
It is better understood from the present invention for the ease of those skilled in the art, below in conjunction with the drawings and specific embodiments, the present invention is described in further details, following be merely illustrative of not limiting protection scope of the present invention.
The present embodiment is for four passages, as it is shown in figure 1, based on the eMMC controller of parallel multi-channel structure, including ahb bus configuration register module ahb_rgf, 4 ahb bus data transfer module ahb_mst and 4 single channel control module Channel.Described ahb_mst includes ahb_mst0, ahb_mst1, ahb_mst2 and ahb_mst3；Described Channel includes Channel0, Channel1, Channel2 and Channel3；Also including 4 eMMC devices accordingly, described eMMC device includes eMMC0, eMMC1, eMMC2 and eMMC3.
nullOne end of ahb_rgf is connected with drive software Software by system bus Systembus、The other end and Channel0、Channel1、One end of Channel2 and Channel3 connects respectively，Channel0、Channel1、One end of Channel2 and Channel3 also respectively with ahb_mst0、ahb_mst1、One end correspondence of ahb_mst2 and ahb_mst3 connects，ahb_mst0、ahb_mst1、The other end of ahb_mst2 and ahb_mst3 is connected on Systembus and is connected with memorizer memory by Systembus，Channel0、Channel1、The other end of Channel2 and Channel3 respectively with eMMC0、eMMC1、EMMC2 and eMMC3 correspondence connects.
The eMMC controller of the present embodiment occurs with the form of system bus main equipment in master control system, channel transfer pattern, transmission order, unit of transfer, transmission quantity will be configured in Software by CPU by the operation of eMMC controller by ahb_rgf, after order completes, eMMC controller can produce corresponding interrupting information, and the interrupt flag bit in depositor is carried out set.Described ahb bus data transfer module ahb_mst has been responsible for that eMMC controller is internal and the read and write operation of data between system bus Systembus.Described single channel control module Channel has been responsible for the encapsulation of the protocol format of command information, data message and has disassembled, and completes the order between eMMC controller and eMMC device and data interaction.
As shown in Figure 2, transmit under operator scheme at single channel, user is visible by four passages in eMMC controller, the corresponding channel transfer pattern of respective passage, transmission order, unit of transfer, transmission quantity depositor can be configured by user by ahb bus configuration register module, these four passages are operated respectively, each passage in eMMC controller can complete different orders, so transmitting under operator scheme at single channel, eMMC controller has very strong motility.
When operator scheme is single channel transmission, the logical relation that in eMMC controller, logical address stores address mapping to eMMC device physics can adopt the relation mapped one by one, as shown in Figure 3.At software respective, namely in eMMC controller, logical address 0 is corresponding with eMMC device physics storage address 0, in eMMC controller, logical address 1 is corresponding with eMMC device physics storage address 1, in eMMC controller, logical address 2 is corresponding with eMMC device physics storage address 2, and in eMMC controller, logical address 3 is corresponding with eMMC device physics storage address 3.nullFor the memory capacity of single eMMC device for 8GB，Assume that four passages enable simultaneously，And each passage 4 eMMC devices of mounting (mount 4 devices and can ensure that eMMC controller optimum performance，When a passage mounts eMMC number of devices more than 4，Then can produce the unnecessary waiting time inside eMMC controller)，Then software free memory is about 128GB，Four passage corresponding P0 respectively、P1、P2、Tetra-districts of P3，Described P0 district includes eMMC0_0、eMMC0_1、EMMC0_2 and eMMC0_3，P1 district includes eMMC1_0、eMMC1_1、EMMC1_2 and eMMC1_3，P2 district includes eMMC2_0、eMMC2_1、EMMC2_2 and eMMC2_3，P3 district includes eMMC3_0、eMMC3_1、EMMC3_2 and eMMC3_3，Sequential access memory space eMMC0_0、eMMC0_1、eMMC0_2、eMMC0_3、eMMC1_0、eMMC1_1、eMMC1_2、eMMC1_3、eMMC2_0、eMMC2_1、eMMC2_2、eMMC2_3、eMMC3_0、eMMC3_1、EMMC3_2 and eMMC3_3，Mode cumulative in order completes the increase of memory capacity，Read effective bandwidth and can reach 150MB/s、Write effective bandwidth and can reach 70MB/s，Described reading effective bandwidth and to write these two data of effective bandwidth be the single pass actual performance parameter provided on eMMC device producer handbook.
As shown in Figure 4, under channel transmission operator scheme, user is not all visible by four passages in eMMC controller, the channel transfer pattern of four passages, transmission order, unit of transfer, transmission quantity depositor, accesssize parameter, jumpsize parameter can be configured by user by ahb bus configuration register module unification, these four passages are operated simultaneously, each passage in eMMC controller completes identical order, so under channel transmission operator scheme, eMMC controller can reach maximum transmission speed.
When operator scheme is channel transmission, in eMMC controller, logical address stores, to eMMC device physics, the logical relation that address maps, as shown in Figure 5.From software respective, namely in eMMC controller, logical address 0 is corresponding with eMMC device 0_0 physical storage address 0, in eMMC controller, logical address 1 is corresponding with eMMC device 1_0 physical storage address 0, in eMMC controller, logical address 2 is corresponding with eMMC device 2_0 physical storage address 0, and in eMMC controller, logical address 3 is corresponding with eMMC device 3_0 physical storage address 0.nullFor the memory capacity of single eMMC device for 8GB，Assume that four passages enable simultaneously，And each passage 4 eMMC devices of mounting，Then software free memory is about 128GB，Four passage corresponding P0 respectively、P1、P2、Tetra-districts of P3，Described P0 district includes eMMC0_0、eMMC1_0、EMMC2_0 and eMMC3_0，P1 district includes eMMC0_1、eMMC1_1、EMMC2_1 and eMMC3_1，P2 district includes eMMC0_2、eMMC1_2、EMMC2_2 and eMMC3_2，P3 district includes eMMC0_3、eMMC1_3、EMMC2_3 and eMMC3_3，The increase of memory capacity is completed according to the mode of number of channels × 4，Read effective bandwidth and can reach 600MB/s、Write effective bandwidth and can reach 280MB/s.
Above only describes the ultimate principle of the present invention and preferred implementation, those skilled in the art can make many changes and improvements according to foregoing description, and these changes and improvements should belong to protection scope of the present invention.
Claims (4)
1. the eMMC controller based on parallel multi-channel structure, it is characterised in that include ahb bus configuration register module ahb_rgf, at least 2 ahb bus data transfer module ahb_mst and the single channel control module Channel equal with ahb_mst quantity；
Described ahb_rgf is connected with drive software Software by system bus Systembus, and channel transfer pattern, transmission order, unit of transfer, transmission quantity will be configured in Software by CPU by the operation of eMMC controller by ahb_rgf；
Described each ahb_mst is connected with memorizer memory by system bus Systembus, and ahb_mst has been responsible for that eMMC controller is internal and the read and write operation of data between system bus Systembus；
One end of described each Channel connects with ahb_rgf and corresponding ahb_mst, the other end is connected with corresponding outside eMMC device, described eMMC device is equal with the quantity of Channel, Channel has been responsible for the encapsulation of the protocol format of command information, data message and has disassembled, and completes the order between eMMC controller and eMMC device and data interaction.
2. eMMC controller according to claim 1, it is characterized in that, described ahb_mst, Channel and eMMC device are 4, ahb_mst includes ahb_mst0, ahb_mst1, ahb_mst2 and ahb_mst3, Channel includes Channel0, Channel1, Channel2 and Channel3, and eMMC device includes eMMC0, eMMC1, eMMC2 and eMMC3；nullOne end of ahb_rgf is connected on Systembus、The other end and Channel0、Channel1、One end of Channel2 and Channel3 connects respectively，Channel0、Channel1、One end of Channel2 and Channel3 also respectively with ahb_mst0、ahb_mst1、One end correspondence of ahb_mst2 and ahb_mst3 connects，ahb_mst0、ahb_mst1、The other end of ahb_mst2 and ahb_mst3 is connected on Systembus，Channel0、Channel1、The other end of Channel2 and Channel3 respectively with eMMC0、eMMC1、EMMC2 and eMMC3 correspondence connects.
3. eMMC controller according to claim 2, it is characterized in that, when operator scheme is single channel transmission, in eMMC controller, logical address 0 is corresponding with eMMC device physics storage address 0, in eMMC controller, logical address 1 is corresponding with eMMC device physics storage address 1, in eMMC controller, logical address 2 is corresponding with eMMC device physics storage address 2, and in eMMC controller, logical address 3 is corresponding with eMMC device physics storage address 3；Assume that four passages enable simultaneously, and each passage 4 eMMC devices of mounting, then four passage corresponding tetra-districts of P0, P1, P2, P3 respectively, described P0 district includes eMMC0_0, eMMC0_1, eMMC0_2 and eMMC0_3, P1 district includes eMMC1_0, eMMC1_1, eMMC1_2 and eMMC1_3, P2 district includes eMMC2_0, eMMC2_1, eMMC2_2 and eMMC2_3, and P3 district includes eMMC3_0, eMMC3_1, eMMC3_2 and eMMC3_3, and mode cumulative in order completes the extension of memory capacity.
4. eMMC controller according to claim 2, it is characterized in that, when operator scheme is channel transmission, in eMMC controller, logical address 0 is corresponding with eMMC device 0_0 physical storage address 0, in eMMC controller, logical address 1 is corresponding with eMMC device 1_0 physical storage address 0, in eMMC controller, logical address 2 is corresponding with eMMC device 2_0 physical storage address 0, and in eMMC controller, logical address 3 is corresponding with eMMC device 3_0 physical storage address 0；Assume that four passages enable simultaneously, and each passage 4 eMMC devices of mounting, then four passage corresponding tetra-districts of P0, P1, P2, P3 respectively, described P0 district includes eMMC0_0, eMMC1_0, eMMC2_0 and eMMC3_0, P1 district includes eMMC0_1, eMMC1_1, eMMC2_1 and eMMC3_1, P2 district includes eMMC0_2, eMMC1_2, eMMC2_2 and eMMC3_2, P3 district includes eMMC0_3, eMMC1_3, eMMC2_3 and eMMC3_3, completes the extension of memory capacity according to the mode of number of channels × 4.
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Application publication date: 20160720 |