CN105448896B - Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space - Google Patents
Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space Download PDFInfo
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- CN105448896B CN105448896B CN201410438974.8A CN201410438974A CN105448896B CN 105448896 B CN105448896 B CN 105448896B CN 201410438974 A CN201410438974 A CN 201410438974A CN 105448896 B CN105448896 B CN 105448896B
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Abstract
The present invention relates to electronic technology fields, and in particular to a kind of encapsulating structure.Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space, including packaging body, is used for chip package, the packaging body is equipped with for the pad with external connection, wherein, capacitor cell is set on the pad of setting position, connects backing metal on the pad of remaining position.The present invention connects capacitor cell on the pad of the setting position of chip, to replace the capacitor in external circuit, in the case where not increasing encapsulating structure process complexity, simplifies periphery circuit design and provide convenience for the practical application of client, meet the requirement of low-power consumption high integration.
Description
Technical field
The present invention relates to electronic technology fields, and in particular to a kind of encapsulating structure.
Background technique
Integrated antenna package not only acts as bonding point in IC chip and the external effect being electrically connected, also for
IC chip provides a reliable and stable working environment, plays mechanical or environmental protection work to IC chip
With, thus the function that IC chip can bring into normal play, and guarantee it with high stability and reliability.Chip application
In, the capacitor in peripheral circuit can usually occupy excessive printed circuit board space, also increase the application cost of chip, and incite somebody to action
Capacitor in peripheral circuit, which is set on chip, can also sacrifice excessive chip area, and there is presently no a kind of ideal modes pair
Capacitor is laid out.
Summary of the invention
The object of the present invention is to provide it is a kind of reduction off-chip capacitive hold occupied space integrated encapsulation structure, solve with
Upper technical problem.
Technical problem solved by the invention can be realized using following technical scheme:
Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space, including packaging body, is used for chip package, the encapsulation
Body is equipped with for the pad with external connection, wherein capacitor cell is set on the pad of setting position, remaining position
Backing metal is connected on the pad.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, the capacitor cell and the metal gasket
The height of block is identical.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, the backing metal and the inductance list
Member is connect by soldered ball with circuit board.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, and the capacitor cell includes the first metal
Pole plate, the second metal polar plate；
Second metal polar plate is oppositely arranged with first metal polar plate, and first metal polar plate connects the weldering
The lower surface of disk, second metal polar plate connects the soldered ball.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, first metal polar plate and described the
Capacitor dielectric is filled between two metal polar plates.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, and the chip includes substrate, the weldering
Disk is distributed in the lower surface of the substrate in array format.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, the packaging body using ceramic material or
Plastics are made.
The utility model has the advantages that due to using the technology described above, the present invention connects capacitor on the pad of the setting position of chip
Unit, to replace the capacitor in external circuit to simplify peripheral circuit in the case where not increasing encapsulating structure process complexity
It designs and is that the practical application of client is provided convenience, meet the requirement of low-power consumption high integration.
Detailed description of the invention
Fig. 1 is integrated encapsulation structure main view of the invention；
Fig. 2 is the sectional view along A-A of Fig. 1；
Fig. 3 is the enlarged drawing that capacitor cell is arranged at pad of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
Referring to Fig.1, Fig. 2, Fig. 3 reduce the integrated encapsulation structure that off-chip capacitive holds occupied space, including packaging body 1, are used for
Chip package, packaging body 1 are equipped with for the pad with external connection, wherein capacitor cell is arranged on the pad of setting position
3, backing metal 2 is connected on the pad of remaining position.
The present invention connects capacitor cell on the pad of the setting position of chip, to replace the capacitor in external circuit,
In the case where not increasing encapsulating structure process complexity, simplifies periphery circuit design and provided just for the practical application of client
Benefit meets the requirement of low-power consumption high integration.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, the height of capacitor cell 3 and backing metal 2
It spends identical.Flatness and reliability when guaranteeing that chip 1 is connect with circuit board reduce the insecure defect of the connection such as rosin joint.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, and backing metal 2 and capacitor cell 3 pass through
Soldered ball 4 is connect with circuit board.When soldered ball 4 connect chip 1 with circuit board, pin can be very short, shortens the transmission of signal
Path reduces lead-in inductance, resistance, thus can improve the performance of circuit.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, and capacitor cell 3 includes the first metal pole
Plate 31, the second metal polar plate 32；
Second metal polar plate 32 is oppositely arranged with the first metal polar plate 31, and the first metal polar plate 31 connects pad, the second gold medal
The lower surface for belonging to pole plate 32 connects soldered ball 4.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, the second metal polar plate 32 and the first metal
Pole plate 31 is arranged in parallel after being oppositely arranged with chip.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, the first metal polar plate 31 and the second metal
Capacitor dielectric is filled between pole plate 32.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, and chip includes substrate 5, and pad is in array
Formal distribution is in the lower surface of substrate 5.
Reduction off-chip capacitive of the invention holds the integrated encapsulation structure of occupied space, and packaging body 1 can use ceramic material
Manufactured packaging body 1.Packaging body 1 made of ceramic material has greater flexibility in terms of external form and function, has simultaneously
Better heat dissipation performance.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (4)
1. reducing the integrated encapsulation structure that off-chip capacitive holds occupied space, including packaging body, it to be used for chip package, the packaging body
It is equipped with for the pad with external connection, which is characterized in that capacitor cell is set on the pad of setting position to replace
Capacitor in external circuit connects backing metal on the pad of remaining position；The capacitor cell and the backing metal
Height it is identical；
The capacitor cell includes the first metal polar plate, the second metal polar plate；
Second metal substrate is oppositely arranged with first metal polar plate, and first metal polar plate connects the pad,
The lower surface of second metal polar plate connects soldered ball, and electricity is filled between first metal polar plate and second metal polar plate
Hold medium.
2. the integrated encapsulation structure according to claim 1 for reducing off-chip capacitive and holding occupied space, which is characterized in that described
Backing metal and the capacity cell are connect by soldered ball with the circuit board.
3. the integrated encapsulation structure according to claim 1 for reducing off-chip capacitive and holding occupied space, which is characterized in that described
Chip includes substrate, and the pad is distributed in the lower surface of the substrate in array format.
4. the integrated encapsulation structure according to claim 1 for reducing off-chip capacitive and holding occupied space, which is characterized in that described
Packaging body is made of ceramic material or plastics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438974.8A CN105448896B (en) | 2014-08-29 | 2014-08-29 | Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438974.8A CN105448896B (en) | 2014-08-29 | 2014-08-29 | Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105448896A CN105448896A (en) | 2016-03-30 |
| CN105448896B true CN105448896B (en) | 2018-12-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410438974.8A Active CN105448896B (en) | 2014-08-29 | 2014-08-29 | Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105448896B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369913A (en) * | 2001-02-15 | 2002-09-18 | 矽统科技股份有限公司 | Ball arra ypackage for redcing electric stray signals |
| CN1732570A (en) * | 2002-12-31 | 2006-02-08 | 英特尔公司 | Multilayer capacitor with multiple plates per layer |
| CN101271874A (en) * | 2008-05-12 | 2008-09-24 | 日月光半导体制造股份有限公司 | Semiconductor element with noise suppressing function and its manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5027431B2 (en) * | 2006-03-15 | 2012-09-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2014
- 2014-08-29 CN CN201410438974.8A patent/CN105448896B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369913A (en) * | 2001-02-15 | 2002-09-18 | 矽统科技股份有限公司 | Ball arra ypackage for redcing electric stray signals |
| CN1732570A (en) * | 2002-12-31 | 2006-02-08 | 英特尔公司 | Multilayer capacitor with multiple plates per layer |
| CN101271874A (en) * | 2008-05-12 | 2008-09-24 | 日月光半导体制造股份有限公司 | Semiconductor element with noise suppressing function and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105448896A (en) | 2016-03-30 |
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