CN104952705A - Double pattern and manufacture method of semiconductor device structure - Google Patents
Double pattern and manufacture method of semiconductor device structure Download PDFInfo
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- CN104952705A CN104952705A CN201410114647.7A CN201410114647A CN104952705A CN 104952705 A CN104952705 A CN 104952705A CN 201410114647 A CN201410114647 A CN 201410114647A CN 104952705 A CN104952705 A CN 104952705A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a double pattern and a manufacture method of a semiconductor device structure. The double pattern includes a first mask having at least two rows of bar-shaped image arrays arranged in a spaced manner, each bar-shaped image array includes a plurality of bar-shaped images arranged at intervals and end parts of the bar-shaped images are corresponding to-be-cut areas; and a second mask provided with a cutting window between adjacent bar-shaped image arrays of the first mask, wherein the cutting window covers the end parts of the bar-shaped images in the two rows of the bar-shaped image arrays at the same time. According to the invention, by adopting the cutting window with comparatively large width for covering the end parts of the bar-shaped images in the two rows of the bar-shaped image arrays at the same time, synchronous cutting of the two flat cable ends can be performed. The distance between the two flat cables ends can be reduced effectively compared with that in a method adopting two cutting windows with comparatively smaller widths for cutting the flat cable ends, so that the circuit integration is improved.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to the manufacture method of a kind of double-pattern and semiconductor device structure.
Background technology
Along with the continuous progress of semiconductor technology, the function of device is gradually become strong, and the thing followed is growing with each passing day of semiconductor manufacturing difficulty.At present, on 32nm and following technology node thereof, be applied to the photoetching process of key level, resolution index needed for it has exceeded the limit capacity of existing optical lithography platform, industry have employed multiple technologies scheme and solves this technical problem, and according to ITRS route map, Dual graphing technology (Double Patterning Technology is called for short DPT), extreme ultraviolet line technology (EUV), electronics art are directly write technical schemes such as (EBL) and have all been expressed great expectations by industry.
Wherein, Dual graphing technology (DPT) is decomposed by a set of highdensity circuitous pattern be split as two covers or overlap the lower circuit diagram of closeness more, then they is printed on target wafer.Double-pattern exposure has multiple different implementation method, but basic step is all first print the figure of half, development, etching; Then spin coating one deck photoresist again, then print second half figure, finally utilize hard mask or selective etch to complete whole photoetching process.
Grid live width is one of major parameter of semiconductor device.Reduce live width can improve integrated level and reduce device size.The photoetching process making little live width grid can produce line end and shrink (line-end shortening).Grid live width is less, and line end shrinks more serious.Traditional method carries out optical approach effect correction (optical proximity correction, OPC) on the photomask to correct line end contraction.When line end shrinks too serious, the correction of required optical approach effect correction is too large, to such an extent as to adjacent two line end figures form overlap on the photomask, cause optical proximity correction method to lose efficacy.In this case, increase by step of just having to line end cutting technique (line-end cut).Gate line end cutting technique is after the grid lines forming overlapping line end, and it is the technical processs transferred to by target pattern by series of steps such as aligning, exposures on substrate that the line end cutting photoetching increased by utilizing cutting mask and line end cutting etching technics cut off overlapping adjacent two line end photoetching.But along with the development of ic manufacturing technology, the characteristic size of semiconductor device is more and more less, individual layer exposes the requirement that can not meet resolution, and double-deck exposure can solve the requirement of resolution.
As shown in Fig. 1 ~ Fig. 2, the cutting window that existing a kind of line end cutting technique all adopts width less realizes, but, for adjacent two row's grid line ends 101, adopt the cutting window 102 realization cutting that two width are less, distance between two cutting windows 102 is subject to as impacts such as exposure or technique live widths, the precision must with a larger distance guarantee exposure and etching between two cutting windows 102, so, distance between two adjacent row's grid line ends 101 is subject to the restriction of the spacing of cutting window 102, the increase that its distance also must adapt to, thus the serious integrated level reducing circuit.
Therefore, provide a kind of can effectively to cut grid line end and the method that can improve circuit level is necessary.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide the manufacture method of a kind of double-pattern and semiconductor device structure, for solving the problem causing circuit level seriously to reduce due to the restriction of the spacing of cutting window in prior art.
For achieving the above object and other relevant objects, the invention provides a kind of double-pattern, comprising:
First mask, have at least two row's flagpole pattern arrays of arrangement of being separated by, each row's flagpole pattern array comprises multiple spaced flagpole pattern, and respectively the end of this flagpole pattern corresponds to region to be cut;
Second mask, it has cutting window between adjacent two row's flagpole pattern arrays of the first mask, and this cutting window is covered in the end of each flagpole pattern in described two row's flagpole pattern arrays simultaneously.
As a kind of preferred version of double-pattern of the present invention, in described first mask, the multiple flagpole patterns in adjacent two row's flagpole pattern arrays are dislocation arrangement.
As a kind of preferred version of double-pattern of the present invention, described first mask and the second mask comprise transparency carrier and patterned light shield layer.
The present invention also provides a kind of manufacture method of the semiconductor device structure based on double-pattern, comprises the following steps:
1) surface coverage is provided to have the Semiconductor substrate of structure sheaf;
2) the first litho pattern is formed by described first mask in described structure sheaf surface, by this first litho pattern, described structure sheaf is etched at least two row's list structure arrays with arrangement of being separated by, and each list structure array comprises multiple spaced list structure;
3) described first litho pattern is removed;
4) form the second litho pattern by described second mask, the end etching of each list structure in adjacent described two row's list structure arrays is removed by this second litho pattern simultaneously.
As a kind of preferred version of the manufacture method of semiconductor device structure of the present invention, described structure sheaf is one or more the lamination in dielectric layer, polysilicon layer, metal level.
As a kind of preferred version of the manufacture method of semiconductor device structure of the present invention, the multiple list structures in adjacent two row's list structure arrays are dislocation arrangement.
As a kind of preferred version of the manufacture method of semiconductor device structure of the present invention, step 2) described first litho pattern is patterned photoresist oxidant layer.
As a kind of preferred version of the manufacture method of semiconductor device structure of the present invention, step 2) described first litho pattern is the composite bed of patterned hard mask layer and photoresist oxidant layer composition.
As a kind of preferred version of the manufacture method of semiconductor device structure of the present invention, the second litho pattern described in step 4) is patterned photoresist oxidant layer.
As a kind of preferred version of the manufacture method of semiconductor device structure of the present invention, the second litho pattern described in step 4) is the composite bed of patterned hard mask layer and photoresist oxidant layer composition.
As mentioned above, the invention provides the manufacture method of a kind of double-pattern and semiconductor device structure, described double-pattern comprises: the first mask, there are at least two row's flagpole pattern arrays of arrangement of being separated by, each row's flagpole pattern array comprises multiple spaced flagpole pattern, and respectively the end of this flagpole pattern corresponds to region to be cut; And second mask, it has cutting window between adjacent two row's flagpole pattern arrays of the first mask, and this cutting window is covered in the end of each flagpole pattern in described two row's flagpole pattern arrays simultaneously.The cutting window that the present invention adopts width larger is covered in the end of each flagpole pattern in described two row's flagpole pattern arrays simultaneously, for cutting two winding displacement ends simultaneously, compared to existing employing two little width cutting window respectively concerning the method that two winding displacement end-grain cutting are cut, the distance between two winding displacement ends can be effectively reduced, thus improve the integrated level of circuit.
Accompanying drawing explanation
Fig. 1 ~ Fig. 2 is shown as the structural representation of a kind of double-pattern for line end cutting of the prior art.
Fig. 3 ~ Fig. 4 is shown as the structural representation of double-pattern of the present invention.
Fig. 5 is shown as the manufacture method steps flow chart schematic diagram of the semiconductor device structure based on double-pattern of the present invention.
Element numbers explanation
201 flagpole patterns
202 cutting windows
203 active areas
S11 ~ S14 step 1) ~ step 4)
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 3 ~ 5.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Fig. 3 ~ Fig. 4, the present embodiment provides a kind of double-pattern, comprising:
First mask, have at least two row's flagpole pattern 201 arrays of arrangement of being separated by, each row's flagpole pattern 201 array comprises multiple spaced flagpole pattern 201, and respectively the end of this flagpole pattern 201 corresponds to region to be cut;
Second mask, it has cutting window 202 between adjacent two row's flagpole pattern 201 arrays of the first mask, and this cutting window 202 is covered in the end of each flagpole pattern 201 in described two row's flagpole pattern 201 arrays simultaneously.
Exemplarily, as shown in Figure 3, in described first mask, the multiple flagpole patterns 201 in adjacent two row's flagpole pattern 201 arrays are dislocation arrangement.In general, described first mask is for making the structure such as metal level, dielectric layer, polysilicon gate of strip, and in the present embodiment, described first mask is for making the polysilicon gate of strip, be active area 203 below described polysilicon gate, it is formed by operation above.In the production process of reality, the multiple strip polysilicon gates adopting described first mask to be formed can be dislocation arrangement, at this moment, can produce a lot of polysilicon line end, and due to reasons such as exposures, these line ends often has serious contraction, therefore, increase by step of having to line end cutting technique.
Described second mask, as shown in Figure 4, it has cutting window 202 between adjacent two row's flagpole pattern 201 arrays of the first mask, and this cutting window 202 is covered in the end of each flagpole pattern 201 in described two row's flagpole pattern 201 arrays simultaneously, described second mask is used for cutting the end of the strip polysilicon gate of employing first mask fabrication simultaneously, compared to existing employing two little width cutting window respectively concerning the method that two winding displacement end-grain cutting are cut, the distance between two winding displacement ends can be effectively reduced, thus greatly improve the integrated level of circuit.
Exemplarily, described first mask and the second mask comprise transparency carrier and patterned light shield layer.In described first mask, described light shield layer has at least two row's flagpole pattern 201 arrays of arrangement of being separated by, and each row's flagpole pattern 201 array comprises multiple spaced flagpole pattern 201, and respectively the end of this flagpole pattern 201 corresponds to region to be cut.In described second mask, described light shield layer has cutting window 202 between adjacent two row's flagpole pattern 201 arrays of the first mask, and this cutting window 202 is covered in the end of each flagpole pattern 201 in described two row's flagpole pattern 201 arrays simultaneously.
As shown in Figure 5, the present embodiment also provides a kind of manufacture method of the semiconductor device structure based on double-pattern, comprises the following steps:
First carry out step 1) S11, provide surface coverage to have the Semiconductor substrate of structure sheaf.
Exemplarily, described Semiconductor substrate can be silicon substrate, silicon carbide substrates, germanium silicon substrate or III-V compounds of group substrate etc.Described structure sheaf is one or more the lamination in dielectric layer, polysilicon layer, metal level, and in the present embodiment, described structure sheaf is the lamination of polysilicon layer and dielectric layer.
Then carry out step 2) S12, the first litho pattern is formed in described structure sheaf surface by described first mask, by this first litho pattern, described structure sheaf is etched at least two row's list structure arrays with arrangement of being separated by, and each list structure array comprises multiple spaced list structure.
In the present embodiment, described list structure is the lamination of polysilicon layer and dielectric layer.
Exemplarily, described first litho pattern is patterned photoresist oxidant layer.Or described first litho pattern is the composite bed of patterned hard mask layer and photoresist oxidant layer composition.In the present embodiment, described first litho pattern is patterned photoresist oxidant layer.Particularly, comprise the following steps:
Step 2-1), form photoresist oxidant layer in described structure sheaf surface;
Step 2-2), adopt described first mask to expose described photoresist oxidant layer, develop and curing process, form the first litho pattern;
Step 2-3), by this first litho pattern, described structure sheaf is etched at least two row's list structure arrays with arrangement of being separated by, and each list structure array comprises multiple spaced list structure.Exemplarily, the multiple list structures in described adjacent two row's list structure arrays are dislocation arrangement.Due to reasons such as exposures, these line ends often have serious contraction, therefore, and increase by step of having to line end cutting technique.
Then carry out step 3) S13, remove described first litho pattern.
Finally carry out step 4) S14, form the second litho pattern by described second mask, the end etching of each list structure in adjacent described two row's list structure arrays is removed by this second litho pattern simultaneously.
Exemplarily, described second litho pattern is patterned photoresist oxidant layer.Or described second litho pattern is the composite bed of patterned hard mask layer and photoresist oxidant layer composition.In the present embodiment, described second litho pattern is patterned photoresist oxidant layer.Particularly, comprise the following steps:
Step 4-1), in by step 2) structure sheaf after etching and semiconductor substrate surface form photoresist oxidant layer;
Step 4-2), adopt described second mask to expose described photoresist oxidant layer, develop and curing process, form the second litho pattern;
Step 4-3), the end etching of each list structure in adjacent two row's list structure arrays is removed by this second litho pattern simultaneously.Adopt same cutting window to remove two winding displacement ends simultaneously, compared to existing employing two little width cutting window respectively concerning the method that two winding displacement end-grain cutting are cut, the distance between two winding displacement ends can be effectively reduced, thus improve the integrated level of circuit.
As mentioned above, the invention provides the manufacture method of a kind of double-pattern and semiconductor device structure, described double-pattern comprises: the first mask, there are at least two row's flagpole pattern 201 arrays of arrangement of being separated by, each row's flagpole pattern 201 array comprises multiple spaced flagpole pattern 201, and respectively the end of this flagpole pattern 201 corresponds to region to be cut; And second mask, it has cutting window 202 between adjacent two row's flagpole pattern 201 arrays of the first mask, and this cutting window 202 is covered in the end of each flagpole pattern 201 in described two row's flagpole pattern 201 arrays simultaneously.The cutting window 202 that the present invention adopts width larger is covered in the end of each flagpole pattern 201 in described two row's flagpole pattern 201 arrays simultaneously, for cutting two winding displacement ends simultaneously, compared to existing employing two little width cutting window respectively concerning the method that two winding displacement end-grain cutting are cut, the distance between two winding displacement ends can be effectively reduced, thus improve the integrated level of circuit.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a double-pattern, is characterized in that, comprising:
First mask, have at least two row's flagpole pattern arrays of arrangement of being separated by, each row's flagpole pattern array comprises multiple spaced flagpole pattern, and respectively the end of this flagpole pattern corresponds to region to be cut; And
Second mask, it has cutting window between adjacent two row's flagpole pattern arrays of the first mask, and this cutting window is covered in the end of each flagpole pattern in described two row's flagpole pattern arrays simultaneously.
2. double-pattern according to claim 1, is characterized in that: in described first mask, and the multiple flagpole patterns in adjacent two row's flagpole pattern arrays are dislocation arrangement.
3. double-pattern according to claim 1, is characterized in that: described first mask and the second mask comprise transparency carrier and patterned light shield layer.
4., based on a manufacture method for the semiconductor device structure of the double-pattern described in claims 1 to 3 any one, it is characterized in that, comprise the following steps:
1) surface coverage is provided to have the Semiconductor substrate of structure sheaf;
2) the first litho pattern is formed by described first mask in described structure sheaf surface, by this first litho pattern, described structure sheaf is etched at least two row's list structure arrays with arrangement of being separated by, and each list structure array comprises multiple spaced list structure;
3) described first litho pattern is removed;
4) form the second litho pattern by described second mask, the end etching of each list structure in adjacent two row's list structure arrays is removed by this second litho pattern simultaneously.
5. the manufacture method of semiconductor device structure according to claim 4, is characterized in that: described structure sheaf is one or more the lamination in dielectric layer, polysilicon layer, metal level.
6. the manufacture method of semiconductor device structure according to claim 4, is characterized in that: the multiple list structures in adjacent two row's list structure arrays are dislocation arrangement.
7. the manufacture method of semiconductor device structure according to claim 4, is characterized in that: step 2) described first litho pattern is patterned photoresist oxidant layer.
8. the manufacture method of semiconductor device structure according to claim 4, is characterized in that: step 2) described first litho pattern be patterned hard mask layer and photoresist oxidant layer composition composite bed.
9. the manufacture method of semiconductor device structure according to claim 4, is characterized in that: the second litho pattern described in step 4) is patterned photoresist oxidant layer.
10. the manufacture method of semiconductor device structure according to claim 4, is characterized in that: the second litho pattern described in step 4) is the composite bed of patterned hard mask layer and photoresist oxidant layer composition.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410114647.7A CN104952705A (en) | 2014-03-26 | 2014-03-26 | Double pattern and manufacture method of semiconductor device structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410114647.7A CN104952705A (en) | 2014-03-26 | 2014-03-26 | Double pattern and manufacture method of semiconductor device structure |
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| CN104952705A true CN104952705A (en) | 2015-09-30 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107169185A (en) * | 2017-05-09 | 2017-09-15 | 大连理工大学 | A kind of double-pattern domain color matching method based on window |
| CN107578986A (en) * | 2016-07-04 | 2018-01-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof and the measuring method of photoetching skew |
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| CN101752315A (en) * | 2008-12-19 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Method for manufacturing integrated circuit structure |
| CN103441067A (en) * | 2013-08-16 | 2013-12-11 | 上海华力微电子有限公司 | Dual pattern forming method applied to grid line end cutting |
| CN103474336A (en) * | 2013-09-22 | 2013-12-25 | 上海华力微电子有限公司 | Method for manufacturing high-evenness grid electrode lines |
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2014
- 2014-03-26 CN CN201410114647.7A patent/CN104952705A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752315A (en) * | 2008-12-19 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Method for manufacturing integrated circuit structure |
| CN103441067A (en) * | 2013-08-16 | 2013-12-11 | 上海华力微电子有限公司 | Dual pattern forming method applied to grid line end cutting |
| CN103474336A (en) * | 2013-09-22 | 2013-12-25 | 上海华力微电子有限公司 | Method for manufacturing high-evenness grid electrode lines |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107578986A (en) * | 2016-07-04 | 2018-01-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof and the measuring method of photoetching skew |
| CN107169185A (en) * | 2017-05-09 | 2017-09-15 | 大连理工大学 | A kind of double-pattern domain color matching method based on window |
| CN107169185B (en) * | 2017-05-09 | 2019-08-09 | 大连理工大学 | A kind of double-pattern domain color matching method based on window |
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Application publication date: 20150930 |