CN103579361A - Metal-oxide semiconductor thin film transistor and manufacturing method thereof - Google Patents
Metal-oxide semiconductor thin film transistor and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 210
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 209
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 208
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000010409 thin film Substances 0.000 title abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000002161 passivation Methods 0.000 claims abstract description 21
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 27
- 229910052760 oxygen Inorganic materials 0.000 claims description 27
- 239000001301 oxygen Substances 0.000 claims description 27
- 239000012212 insulator Substances 0.000 claims description 25
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 194
- 230000008569 process Effects 0.000 abstract description 14
- 230000006378 damage Effects 0.000 abstract description 12
- 239000011241 protective layer Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 239000010408 film Substances 0.000 description 40
- 238000010586 diagram Methods 0.000 description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000011787 zinc oxide Substances 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 235000019593 adhesiveness Nutrition 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000013081 microcrystal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000019771 cognition Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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Abstract
A metal-oxide semiconductor thin film transistor comprises a substrate, a grid electrode, a grid electrode insulation layer, a source electrode, a drain electrode and a metal-oxide semiconductor layer. The grid electrode insulation layer is arranged on the substrate and covers the grid electrode on the substrate. The source electrode and the drain electrode are arranged on the grid electrode insulation layer in a separated mode, and are provided with a first overlap region and a second overlap region respectively with the grid electrode. The metal-oxide semiconductor layer covers the source electrode and the drain electrode and is in contact with the source electrode and the drain electrode, the metal-oxide semiconductor layer is provided with a third overlap region and a fourth overlap region with the source electrode and the drain electrode respectively, the area of the third overlap region is larger than that of the first overlap area, and the area of the fourth overlap region is larger than that of the second overlap area. The metal-oxide semiconductor thin film transistor can effectively solve the problem that the metal-oxide semiconductor layer is stripped from the source electrode and the drain electrode, and meanwhile damage to the metal-oxide semiconductor layer in the process of forming a passivation protective layer can be avoided. The invention further relates to a manufacturing method of the metal-oxide semiconductor thin film transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, and particularly relate to a kind of metal oxide semiconductor films transistor and manufacture method thereof.
Background technology
The material of semiconductor channel layer that is used at present the thin-film transistor (thin film transistor, TFT) of flat panel display is mainly silicon materials, comprises amorphous silicon (a-Si:H), polysilicon, microcrystal silicon etc.Yet amorphous silicon film transistor has photaesthesia, mobility is low and the shortcoming such as poor stability; Although polycrystalline SiTFT has higher mobility, because the impact of crystal boundary causes its electricity lack of homogeneity, and polysilicon preparation temperature is high, cost is high and be difficult to large area crystallization, has limited its application in flat panel display; It is large that microcrystal silicon is prepared difficulty, and crystal grain control technology difficulty is high, is not easy to realize large area scale volume production.
Known some metal oxide has characteristic of semiconductor at present, tungsten oxide for example, tin oxide, indium oxide, zinc oxide, indium gallium zinc oxide (indium gallium zinc oxide, IGZO) etc., utilize the transparent semiconductor layer that such metal oxide forms as channel layer materials, to form the thin-film transistor of metal-oxide semiconductor (MOS), compare with the thin-film transistor that contains silicon, it is higher that metal oxide semiconductor films transistor has electron mobility, preparation temperature is low, to advantages such as visible transparent, thereby more and more come into one's own, there is the development trend that substitutes the thin-film transistor of preparing by traditional silicon technique.Te Do ground, IGZO TFT was because electron mobility is high in recent years, good stability, the advantage such as preparation technology is simple, becomes the focus of metal current oxide semiconductor thin-film transistor research and development.
The structure of IGZO TFT mainly contains the back of the body channel-etch type (back channel etch type), etching barrier type (etch stop type) and coplanar type (coplanar type) three types.Back of the body channel-etch type IGZO TFT technological process is simple, but due to the few protective layer of IGZO break, when forming source-drain electrode, is easy to IGZO layer to damage, thereby affects the performance of IGZO TFT, therefore current this structure of less use.Etch stop layer on the IGZO layer of etching barrier type IGZO TFT can protect IGZO layer not to be destroyed when forming source-drain electrode, thereby improves the performance of IGZO TFT.But, the making of etching barrier type IGZO TFT need to increase a photoetching process to form etch stop layer, increase the complexity of the fabrication processing of IGZO TFT, and because the material of etch stop layer is generally SiNx or SiOx, at using plasma, strengthen chemical vapour deposition technique (plasma enhanced chemical vapor deposition, PECVD) form in the process of etch stop layer, plasma easily damages IGZO layer, thereby affects the performance of IGZO TFT.Coplanar type IGZO TFT is current main flow structure, coplanar type IGZO TFT compares with back of the body channel-etch type IGZO TFT, because IGZO layer is on source-drain electrode, can avoid the destruction to IGZO layer in forming source-drain electrode technique, compare and lacked photoetching process one time with etching barrier type IGZO TFT simultaneously, and the equipment compatibility of preparing amorphous silicon (a-Si) TFT with current main flow is good, can reduce the input of equipment, reduce production costs.
But; the shortcoming of coplanar type IGZO TFT is that (peeling) easily appears peeling off in the local IGZO layer contacting with source-drain electrode at IGZO layer; and in the process of follow-up formation passivation protection layer, the IGZO layer on source-drain electrode is damaged and destroys, thereby affect the performance of IGZO TFT.Fig. 1 is the layout structure schematic diagram of existing coplanar type IGZO TFT.Fig. 2 is that the coplanar type IGZO TFT shown in Fig. 1 is along the sectional structure schematic diagram of II-II line.Please with reference to Fig. 1 and Fig. 2, the grid 110 of coplanar type IGZO TFT100 is formed on substrate 101, gate insulator 120 is formed on substrate 101 and cover gate 110, source electrode 132, draining 134 is formed on gate insulator 120 separatedly, IGZO layer 140 is formed at source electrode 132, drain on 134, is connected in source electrode 132, drains between 134 and is positioned at the top of grid 110.Because the area of IGZO layer 140 thinner thickness and IGZO layer 140 and source electrode 132, drain 134 contact area 105a, 150b is less, therefore, IGZO layer 140 and source electrode 132,134 the adhesiveness of draining are poor, by optical cover process, forming in the process of IGZO layer 140, easily when removing photoresist, cause IGZO layer 140 from source-drain electrode 132,134 situations about peeling off drain.On the other hand; because IGZO layer 140 is formed at source electrode 132, drains on 134; on IGZO layer 140, can strengthen chemical vapour deposition technique formation passivation protection layer 150 by using plasma; for the ease of showing the structure of metal oxide semiconductor films transistor 100; in Fig. 1, do not draw passivation protection layer 150, only in Fig. 2, draw.In forming the process of passivation protection layer 150, plasma cognition reacts with the oxygen in IGZO layer 140, IGZO layer 140 is caused to damage and fracture, thereby affect the semiconducting behavior of IGZO layer 140.No matter be peeling off of IGZO layer 140, or the damage and fracture of IGZO layer 140 all can have a strong impact on the performance of coplanar type IGZO TFT100.
Summary of the invention
The object of the invention is to; a kind of metal oxide semiconductor films transistor is provided; effectively to solve the problem of peeling off of metal oxide semiconductor layer and source electrode and drain electrode, also can effectively avoid the damage to metal oxide semiconductor layer in forming passivation protection layer process simultaneously.
It is a kind of for the manufacture of the transistorized manufacture method of above-mentioned metal oxide semiconductor films that the present invention also provides.
It is to adopt following technical scheme to realize that the present invention solves its technical problem.
A transistor, it comprises substrate, grid, gate insulator, source electrode and drain electrode and metal oxide semiconductor layer.Grid is positioned in substrate.Gate insulator is positioned in substrate and cover gate.What source electrode and drain electrode were separated is positioned on gate insulator, and source electrode and grid have the first overlay region, and drain electrode has the second overlay region with grid.Metal oxide semiconductor layer covers source electrode and contacts with drain electrode with drain electrode and with source electrode, and metal oxide semiconductor layer and source electrode have triple-overlapped district, metal oxide semiconductor layer and drain electrode have the 4th overlay region, the area in triple-overlapped district is greater than the area of the first overlay region, and the area of the 4th overlay region is greater than the area of the second overlay region.
In preferred embodiment of the present invention, the length direction of above-mentioned source electrode and drain electrode is perpendicular to the long side and the grid juxtaposition that extend along grid length direction of grid.Metal oxide semiconductor layer comprises first, second portion and third part, and second portion is connected between first and third part.First covers the first overlay region completely and along the length direction of source electrode, extends beyond this long side of grid, and third part covers the second overlay region completely and along the length direction of drain electrode, extends beyond this long side of grid.
In preferred embodiment of the present invention, above-mentioned metal oxide semiconductor layer comprises the first metal oxide semiconductor layer and the second metal oxide semiconductor layer.The first metal oxide semiconductor layer is positioned at source electrode and above and with source electrode contacts with drain electrode with drain electrode.The second metal oxide semiconductor layer is positioned on the first metal oxide semiconductor layer.
In preferred embodiment of the present invention, the oxygen content of above-mentioned the second metal oxide semiconductor layer is greater than the oxygen content of the first metal oxide semiconductor layer.
In preferred embodiment of the present invention, above-mentioned metal oxide semiconductor films transistor also comprises passivation protection layer, and passivation protection layer covers the second metal oxide semiconductor layer.
A transistorized manufacture method, it comprises the following steps.First, in substrate, form grid.Then, in substrate, form gate insulator, and cover gate.Afterwards, form source electrode and drain electrode on gate insulator, source electrode and drain electrode are separate, and have the first overlay region and the second overlay region with grid respectively.Then, in source electrode and drain electrode, form metal oxide semiconductor layer, metal oxide semiconductor layer contacts with drain electrode with source electrode, and there is triple-overlapped district and the 4th overlay region with source electrode and drain electrode respectively, the area in triple-overlapped district is greater than the area of the first overlay region, and the area of the 4th overlay region is greater than the area of the second overlay region.
In preferred embodiment of the present invention, the length direction of above-mentioned source electrode and drain electrode is perpendicular to the long side and the grid juxtaposition that extend along grid length direction of grid.Metal oxide semiconductor layer comprises first, second portion and third part, and second portion is connected between first and third part.First covers the first overlay region completely and along the length direction of source electrode, extends beyond this long side of grid, and third part covers the second overlay region completely and along the length direction of drain electrode, extends beyond this long side of grid.
In preferred embodiment of the present invention, in above-mentioned source electrode and drain electrode, form metal oxide semiconductor layer, first in source electrode and drain electrode, form the first metal oxide semiconductor layer, the first metal oxide semiconductor layer is electrically connected to source electrode and drain electrode.Then, at the first metal oxide semiconductor layer, form the second metal oxide semiconductor layer.
In preferred embodiment of the present invention, the oxygen content of above-mentioned the second metal oxide semiconductor layer is greater than the oxygen content of the first metal oxide semiconductor layer.
In preferred embodiment of the present invention, above-mentioned manufacture method also comprises that using plasma strengthens chemical vapour deposition technique and on the second metal oxide semiconductor layer, forms passivation protection layer.
Metal oxide semiconductor films transistor of the present invention, metal-oxide semiconductor (MOS) is formed on source electrode and drain electrode is upper, can avoid causing the damage and fracture to metal oxide semiconductor layer when forming source electrode and drain electrode.In addition, source electrode and drain electrode have the first overlay region and the second overlay region with grid respectively, metal oxide semiconductor layer has triple-overlapped district and the 4th overlay region with source electrode and drain electrode respectively, the area in Qie triple-overlapped district is greater than the area of the first overlay region, and the area of the 4th overlay region is greater than the area of the second overlay region.The triple-overlapped district of metal oxide semiconductor layer and source electrode and drain electrode and the 4th overlay region have larger area, thinner metal oxide semiconductor layer and source electrode and drain electrode contact area are increased, therefore metal oxide semiconductor layer is difficult for peeling off from source electrode and drain electrode, thereby effectively solved the problem of peeling off of metal oxide semiconductor layer, to obtain well behaved metal oxide semiconductor films transistor.
In addition, the transistorized metal oxide semiconductor layer of metal oxide semiconductor films of the present invention can comprise the first metal oxide semiconductor layer and the second metal oxide semiconductor layer, and the oxygen content of the second metal oxide semiconductor layer is greater than the oxygen content of the first metal oxide semiconductor layer, because the second metal oxide semiconductor layer oxygen content is more than needed, at using plasma, strengthen chemical vapour deposition technique forms in the process of passivation protection layer on metal oxide semiconductor layer, the damage and fracture that the second metal oxide semiconductor layer can stop plasma to cause the first metal oxide semiconductor layer, thereby obtain well behaved metal oxide semiconductor films transistor.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, for technique scheme of the present invention and other objects, features and advantages can be become apparent, and preferred embodiment cited below particularly, and coordinate appended graphicly, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the layout structure schematic diagram of existing coplanar type IGZO TFT.
Fig. 2 is that the coplanar type IGZO TFT shown in Fig. 1 is along the sectional structure schematic diagram of II-II line.
Fig. 3 is the transistorized layout structure schematic diagram of the metal oxide semiconductor films of first embodiment of the invention.
Fig. 4 is the transistorized sectional structure schematic diagram along IV-IV line of the metal oxide semiconductor films of the first embodiment of the invention shown in Fig. 3.
Fig. 5 is the transistorized layout structure schematic diagram of the metal oxide semiconductor films of second embodiment of the invention.
Fig. 6 is the transistorized sectional structure schematic diagram along VI-VI line of the metal oxide semiconductor films of the second embodiment of the invention shown in Fig. 5.
Embodiment
For further setting forth the present invention, reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, embodiment, structure, feature and effect thereof to proposing according to the present invention, be described in detail as follows:
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known and present in the following detailed description coordinating with reference to graphic preferred embodiment.By the explanation of embodiment, when can be to reach technological means and the effect that predetermined object takes to be able to more deeply and concrete understanding to the present invention, yet appended graphic being only to provide with reference to the use with explanation be not used for the present invention to be limited.
Fig. 3 is the transistorized layout structure schematic diagram of the metal oxide semiconductor films of first embodiment of the invention.Fig. 4 is the transistorized sectional structure schematic diagram along IV-IV line of the metal oxide semiconductor films of the first embodiment of the invention shown in Fig. 3.See also Fig. 3 and Fig. 4, in the present embodiment, metal oxide semiconductor films transistor 200 is coplanar type structure, and it mainly comprises substrate 210, grid 220, gate insulator 230, source electrode 242 and drains 244 and metal oxide semiconductor layer 250.
In the present embodiment, grid 220 is positioned in substrate 210, is located at the surface of substrate 210, and grid 220 is roughly strip, and has relative long side 220a, the 220b extending along grid length direction.Gate insulator 230 is positioned in substrate 210, is located at surface the cover gate 220 of substrate 210.In the present embodiment, gate insulator 230 is double-decker, comprises silicon nitride layer 232 and is positioned at the silicon oxide layer 234 on silicon nitride layer 232, but not as limit, be understandable that, in other embodiments, gate insulator 230 can be also single layer structure or other sandwich constructions.
What source electrode 242 and drain electrode 244 were separated is arranged on gate insulator 230, and is positioned at grid 220 tops.The length bearing of trend of source electrode 242 and drain electrode 244 is substantially vertical with the long side 220a, the 220b that extend along grid 220 length directions of grid 220, so that source electrode 242 and drain electrode 244 are square crossing with grid 220 respectively, overlaps.Therefore, in the present embodiment, the first overlay region 201a that grid 220 and source electrode 242 overlap to form, grid 220 and drain electrode 244 the second overlay region 201b that overlap to form.
Metal oxide semiconductor layer 250 is for example indium gallium zinc oxide (IGZO) layer.Metal oxide semiconductor layer 250 covers source electrodes 242, drain 244 and gate insulator 230.Metal oxide semiconductor layer 250 is connected in source electrode 242 and drains between 244, and above source electrode 242 and the grid 220 that drains between 244, and with source electrode 242 and drain electrode 244 direct overlapping contacts.And source electrode 242 and the metal oxide semiconductor layer 250 that drains between 244 be with from source electrode 242 and the part of grid pole insulating barrier 230 exposing between 244 that drains contact.
In the present embodiment, metal oxide semiconductor layer 250 comprises first 251, second portion 252 and third part 253.Second portion 252 is connected between first 251 and third part 253.The first 251 of metal oxide semiconductor layer 250 is positioned at the top of source electrode 242, cover the first overlay region 201a completely, and with the length direction along source electrode 242, cover most source electrode 242 along the long side 220a, the 220b that extend along grid 220 length directions that the length direction of source electrode 242 extends beyond grid 220, thereby form the triple-overlapped district 202a of metal oxide semiconductor layer 250 and source electrode 242.The third part 253 of metal oxide semiconductor layer 250 is positioned at the top of drain electrode 244, cover the second overlay region 201b completely, and the length direction of edge drain electrode 244 extends beyond the long side 220a, the 220b that along grid 220 length directions, extend of grid 220, with the length direction along drain electrode 244, cover most drain electrode 244, thereby form the 4th overlay region 202b of metal oxide semiconductor layer 250 and drain electrode 244.In addition, the second portion 252 of metal oxide semiconductor layer 250 is the source electrode 242 above grid 220 and the passage area 203 that drains between 244, and with from source electrode 242 and the gate insulator 230 exposing between 244 that drains contact.In the present embodiment, the area of ， triple-overlapped district 202a is greater than the area of the first overlay region 201a, and the area of the 4th overlay region 202b is greater than the area of the second overlay region 201b.Because metal oxide semiconductor layer 250 has larger area with triple-overlapped district 202a and the 4th overlay region 202b of source electrode 242 and drain electrode 244, thinner metal oxide semiconductor layer 250 and source electrode 242 and drain electrode 244 contacts area are increased, metal oxide semiconductor layer 250 is better with source electrode 242 and drain electrode 244 adhesivenesses, in follow-up processing procedure, be not easy to cause that metal oxide semiconductor layer 250 peels off from source electrode 242 and drain electrode 244.Therefore metal oxide semiconductor layer 250 is difficult for peeling off from source electrode 242 and drain electrode 244, so that metal oxide semiconductor films transistor 200 has good performance.In addition, the transverse width of the first 251 of metal oxide semiconductor layer 250 is preferably greater than the transverse width of source electrode 242, and the transverse width of the third part 253 of metal oxide semiconductor layer 250 is preferably greater than the transverse width of drain electrode 244.
In addition,, in the present embodiment, metal oxide semiconductor films transistor 200 also comprises passivation protection layer 260.For the ease of showing the structure of metal oxide semiconductor films transistor 200, in Fig. 3, do not draw passivation protection layer 260, only in Fig. 4, draw.Passivation protection layer 260 can be for example silicon nitride layer or silicon oxide layer.Passivation protection layer 260 is positioned on metal oxide semiconductor layer 250 and covering metal oxide semiconductor layer 250, in order to protect metal oxide semiconductor layer 250.
The manufacture method of metal oxide semiconductor films transistor 200 will be illustrated below.About grid 220, source electrode 242 and drain 244, metal oxide semiconductor layer 250 all can realize by well-known processes such as deposition film forming and etched patterns.The manufacture method of metal oxide semiconductor films transistor 200 comprises the following steps.
First, in substrate 210, form grid 220.
Then, in substrate 210, form gate insulator 230, and cover gate 220.
Afterwards, on gate insulator 230, form source electrode 242 and drain electrode 244, source electrode 242 and drain electrode 244 are separate, the length direction of source electrode 242 and drain electrode 244 is substantially vertical with long side 220a, the 220b of grid 220, so that source electrode 242 and drain electrode 244 are square crossing with grid 220 respectively, overlaps.Therefore, source electrode 242 has the first overlay region 201a with grid 220, drains 244 to have the second overlay region 201b with grid 220.
Then, in source electrode 242 and drain electrode 244, form layers of metal oxide materials patterning formation metal oxide semiconductor layer 250.Metal oxide semiconductor layer 250 is above grid 220 and is connected in source electrode 242 and drains between 244 and contact with drain electrode 244 with source electrode 242.Metal oxide semiconductor layer 250 comprises first 251, second portion 252 and third part 253.Second portion 252 is connected between first 251 and third part 253.The first 251 of metal oxide semiconductor layer 250 is positioned at the top of source electrode 242, cover the first overlay region 201a completely, and with the length direction along source electrode 242, cover most source electrode 242 along long side 220a, the 220b that the length direction of source electrode 242 extends beyond grid 220, thereby form the triple-overlapped district 202a of metal oxide semiconductor layer 250 and source electrode 242.The third part 253 of metal oxide semiconductor layer 250 is positioned at the top of drain electrode 244, cover the second overlay region 201b completely, and the long side 220a, the 220b that extend along grid 220 length directions that extend beyond grid 220 along drain electrode 244 length direction be with the length direction along drain electrode 244 and cover most drain electrode 244, thereby form the 4th overlay region 202b of metal oxide semiconductor layer 250 and drain electrode 244.In addition, the second portion 252 of metal oxide semiconductor layer 250 is the source electrode 242 above grid 220 and the passage area 203 that drains between 244, and with from source electrode 242, contact with drain electrode 244 gate insulators that expose 230.In the present embodiment, the area of ， triple-overlapped district 202a is greater than the area of the first overlay region 201a, and the area of the 4th overlay region 202b is greater than the area of the second overlay region 201b.Because metal oxide semiconductor layer 250 has larger area with triple-overlapped district 202a and the 4th overlay region 202b of source electrode 242 and drain electrode 244, thinner metal oxide semiconductor layer 250 and source electrode 242 and drain electrode 244 contacts area are increased, therefore metal oxide semiconductor layer 250 is difficult for peeling off from source electrode 242 and drain electrode 244, so that metal oxide semiconductor films transistor 200 has good performance.In addition, the transverse width of the first 251 of metal oxide semiconductor layer 250 is preferably greater than the transverse width of source electrode 242, and the transverse width of the third part 253 of metal oxide semiconductor layer 250 is preferably greater than the transverse width of drain electrode 244.
In addition, the manufacture method of metal oxide semiconductor films transistor 200 also further comprises that using plasma strengthens chemical vapour deposition technique and on metal oxide semiconductor layer 250, forms passivation protection layer 260.
Fig. 5 is the transistorized layout structure schematic diagram of the metal oxide semiconductor films of second embodiment of the invention.Fig. 6 is the transistorized sectional structure schematic diagram along VI-VI line of the metal oxide semiconductor films of the second embodiment of the invention shown in Fig. 5.See also Fig. 5 and Fig. 6, in the present embodiment, metal oxide semiconductor films transistor 300 is also coplanar type structure, itself and metal oxide semiconductor films transistor 200 are roughly the same, the difference of the two is, the metal oxide semiconductor layer 350 of metal oxide semiconductor films transistor 300 is double-layer structure, and metal oxide semiconductor layer 350 comprises the first metal oxide semiconductor layer 352 and the second metal oxide semiconductor layer 354.Except metal oxide semiconductor layer 350, each structure of all the other of metal oxide semiconductor films transistor 300 is all identical with corresponding each structure of metal oxide semiconductor films transistor 200 and adopt identical label, does not repeat them here.
In the present embodiment, the first metal oxide semiconductor layer 352 and the second oxide semiconductor layer 354 are all for example indium gallium zinc oxide (IGZO) layers, but the oxygen content of the second metal oxide semiconductor layer 354 is greater than the oxygen content of the first metal oxide semiconductor layer 352.So-called oxygen content refers in metal oxide semiconductor layer 350 molal quantity of oxygen atom in every mole of IGZO.For example, it is x that the second metal oxide semiconductor layer 354 is defined as in IGZOx the molal quantity of oxygen atom in every mole of IGZO, it is y that the first metal oxide semiconductor layer 352 is defined as in IGZOy the molal quantity of oxygen atom in every mole of IGZO, wherein, and 0<y<x.Like this; when the formation of using plasma enhancing chemical vapour deposition technique covers one deck passivation protection layer 260 on metal oxide semiconductor layer 350; because the oxygen content of the second metal oxide semiconductor layer 354 is greater than the oxygen content of the first metal oxide semiconductor layer 352; in other words because the oxygen content of the second metal oxide semiconductor layer 354 is more than needed; oxygen more than needed in the second metal oxide semiconductor layer 354 can be used for and plasma reaction, stops the damage and fracture of plasma to the first metal oxide semiconductor layer 352 simultaneously.
The manufacture method of metal oxide semiconductor films transistor 300 will be illustrated below.About grid 220, source electrode 242 and drain 244, metal oxide semiconductor layer 350 all can realize by well-known processes such as deposition film forming and etched patterns.The manufacture method of metal oxide semiconductor films transistor 300 comprises the following steps.
First, in substrate 210, form grid 220.
Then, in substrate 210, form gate insulator 230, and cover gate 220.
Afterwards, on gate insulator 230, form source electrode 242 and drain electrode 244, source electrode 242 and drain electrode 244 are separate, the length direction of source electrode 242 and drain electrode 244 is substantially vertical with long side 220a, the 220b of grid 220, so that source electrode 242 and drain electrode 244 are square crossing with grid 220 respectively, overlaps.Therefore, source electrode 242 has the first overlay region 201a with grid 220, drains 244 to have the second overlay region 201b with grid 220.
Then, in source electrode 242 and drain electrode 244, form successively the first layers of metal oxide materials and the second layers of metal oxide materials patterning and form metal oxide semiconductor layer 350.Metal oxide semiconductor layer 350 is above grid 220 and is electrically connected on source electrode 242 and drains between 244.Formed metal oxide semiconductor layer 350 comprises the first metal oxide semiconductor layer 352 and is positioned at the second metal oxide semiconductor layer 354 on the first metal oxide semiconductor layer 352.The oxygen content of the second metal oxide semiconductor layer 354 is greater than the oxygen content of the first metal oxide semiconductor layer 352.Same, the metal oxide semiconductor layer 350 of patterning comprises the 350a of first, second portion 350b and third part 350c.Second portion 350b is connected between the 350a of first and third part 350c.The 350a of first of metal oxide semiconductor layer 350 is positioned at the top of source electrode 242, cover the first overlay region 201a completely, and along the length direction of source electrode 242, extend beyond the long side 220a, the 220b that along grid 220 length directions, extend of grid 220, with the length direction along source electrode 242, cover most source electrode 242, thereby form triple-overlapped district 302a.The third part 350c of metal oxide semiconductor layer 350 is positioned at the top of drain electrode 244, cover the second overlay region 201b completely, and with the length direction along drain electrode 244, cover most drain electrode 242 along the long side 220a, the 220b that extend along grid 220 length directions that drain electrode 244 length direction extends beyond grid 220, thereby form the 4th overlay region 302b.In addition, the second portion 350b of metal oxide semiconductor layer 350 is the source electrode 242 above grid 220 and the passage area 203 that drains between 244, and with from source electrode 242, contact with drain electrode 244 gate insulators that expose 230.In the present embodiment, the area of ， triple-overlapped district 302a is greater than the area of the first overlay region 201a, and the area of the 4th overlay region 302b is greater than the area of the second overlay region 201b.Because metal oxide semiconductor layer 350 has larger area with triple-overlapped district 302a and the 4th overlay region 302b of source electrode 242 and drain electrode 244, thinner metal oxide semiconductor layer 350 and source electrode 242 and drain electrode 244 contacts area are increased, therefore metal oxide semiconductor layer 350 is difficult for peeling off from source electrode 242 and drain electrode 244, so that metal oxide semiconductor films transistor 300 has good performance.In addition, the transverse width of the 350a of first of metal oxide semiconductor layer 350 is preferably greater than the transverse width of source electrode 242, and the transverse width of the third part 350c of metal oxide semiconductor layer 350 is preferably greater than the horizontal width of drain electrode 244.
In addition, the manufacture method of metal oxide semiconductor films transistor 300 also further comprises that using plasma strengthens chemical vapour deposition technique and on metal oxide semiconductor layer 250, forms passivation protection layer 260.Because the oxygen content of the second metal oxide semiconductor layer 354 is greater than the oxygen content of the first metal oxide semiconductor layer 352; in other words because the oxygen content of the second metal oxide semiconductor layer 354 is more than needed; at using plasma, strengthen chemical vapour deposition technique forms in the process of passivation protection layer 260 on metal oxide semiconductor layer 350; oxygen more than needed in the second metal oxide semiconductor layer 354 can be used for and plasma reaction, stops the damage and fracture of plasma to the first metal oxide semiconductor layer 352 simultaneously.After passivation protection layer 260 forms; in the second metal oxide semiconductor layer 354, remaining oxygen still can maintain the semiconducting behavior of the second metal oxide semiconductor layer 354; further; by follow-up technique; make the oxygen balance of the second metal oxide semiconductor layer 354 and the first metal oxide semiconductor layer 352, thereby make metal oxide semiconductor layer 350 keep good semiconducting behavior.Therefore, the damage and fracture that the second metal oxide semiconductor layer 354 can stop plasma to cause metal oxide semiconductor layer 350, so that metal oxide semiconductor films transistor 200 has good performance.
The above, only embodiments of the invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with embodiment, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be not depart from technical solution of the present invention content, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a metal oxide semiconductor films transistor, is characterized in that, it comprises:
Substrate;
Grid, is positioned in this substrate;
Gate insulator, is positioned in this substrate and covers this grid;
Source electrode and drain electrode, being positioned on this gate insulator of separation, this source electrode and this grid have the first overlay region, and this drain electrode and this grid have the second overlay region; And
Metal oxide semiconductor layer, covering this source electrode contacts with this drain electrode with this drain electrode and with this source electrode, and this metal oxide semiconductor layer and this source electrode have triple-overlapped district, this metal oxide semiconductor layer and this drain electrode have the 4th overlay region, the area in Gai triple-overlapped district is greater than the area of this first overlay region, and the area of the 4th overlay region is greater than the area of this second overlay region.
2. metal oxide semiconductor films transistor according to claim 1, it is characterized in that, this source electrode and this drain electrode are perpendicular to the long side and this grid juxtaposition that extend along grid length direction of this grid, this metal oxide semiconductor layer comprises first, second portion and third part, this second portion is connected between this first and this third part, this first covers this first overlay region completely and along the length direction of this source electrode, extends beyond this long side of this grid, this third part covers this second overlay region completely and along the length direction of this drain electrode, extends beyond this long side of this grid.
3. metal oxide semiconductor films transistor according to claim 1, is characterized in that, this metal oxide semiconductor layer comprises:
The first metal oxide semiconductor layer, is positioned at this source electrode and goes up and contact with this drain electrode with this source electrode with this drain electrode; And
The second metal oxide semiconductor layer, is positioned on this first metal oxide semiconductor layer.
4. metal oxide semiconductor films transistor according to claim 3, is characterized in that, the oxygen content of this second metal oxide semiconductor layer is greater than the oxygen content of this first metal oxide semiconductor layer.
5. metal oxide semiconductor films transistor according to claim 4, is characterized in that, this metal oxide semiconductor films transistor also comprises passivation protection layer, covers this second metal oxide semiconductor layer.
6. the transistorized manufacture method of metal oxide semiconductor films, is characterized in that, it comprises:
In substrate, form grid;
In substrate, form gate insulator, and cover this grid;
On this gate insulator, form source electrode and drain electrode, this source electrode and this drain electrode are separate, and this source electrode and this grid have the first overlay region, and this drain electrode and this grid have the second overlay region; And
In this source electrode and this drain electrode, form metal oxide semiconductor layer, this metal oxide semiconductor layer contacts with this drain electrode with this source electrode, and there is triple-overlapped district with this source electrode, there is the 4th overlay region with this drain electrode, the area in Gai triple-overlapped district is greater than the area of this first overlay region, and the area of the 4th overlay region is greater than the area of this second overlay region.
7. method is made in manufacture according to claim 6, it is characterized in that, this source electrode and this drain electrode form on this gate insulator perpendicular to the long side and this grid juxtaposition that extend along grid length direction of this grid, and this metal oxide semiconductor layer forming comprises first, second portion and be connected to this first and this second portion between third part, this first covers this first overlay region completely and along the length direction of this source electrode, extends beyond this long side of this grid, this third part covers this second overlay region completely and along the length direction of this drain electrode, extends beyond this long side of this grid.
8. method is made in manufacture according to claim 6, it is characterized in that, upper this metal oxide semiconductor layer that forms of this source electrode and this drain electrode comprises:
In this source electrode and this drain electrode, form this first metal oxide semiconductor layer, this first metal oxide semiconductor layer is electrically connected to this source electrode and this drain electrode; And
On this first metal oxide semiconductor layer, form the second metal oxide semiconductor layer.
9. manufacture method according to claim 8, is characterized in that, the oxygen content of this second metal oxide semiconductor layer is greater than the oxygen content of this first metal oxide semiconductor layer.
10. manufacture method according to claim 9, is characterized in that, this manufacture method also comprises that using plasma strengthens chemical vapour deposition technique and form passivation protection layer on this second metal oxide semiconductor layer.
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