CN102760759A - Semiconductor power device - Google Patents
Semiconductor power device Download PDFInfo
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- CN102760759A CN102760759A CN2012100737894A CN201210073789A CN102760759A CN 102760759 A CN102760759 A CN 102760759A CN 2012100737894 A CN2012100737894 A CN 2012100737894A CN 201210073789 A CN201210073789 A CN 201210073789A CN 102760759 A CN102760759 A CN 102760759A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 179
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims description 51
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 7
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims description 3
- ILRRQNADMUWWFW-UHFFFAOYSA-K aluminium phosphate Chemical compound O1[Al]2OP1(=O)O2 ILRRQNADMUWWFW-UHFFFAOYSA-K 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 2
- 238000005036 potential barrier Methods 0.000 description 11
- 230000000903 blocking effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910003811 SiGeC Inorganic materials 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 206010011469 Crying Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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- H01L29/402—
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- H01L29/7395—
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- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a semiconductor power device. The semiconductor power device comprises a first conduction type first semiconductor layer, a first conduction type second semiconductor layer, a second conduction type first well region, a second conduction type second well region, a first conduction type first source region, a first conduction type second source region, a first insulating layer, a polycrystalline silicon layer, a second insulating layer, a first metal layer, a second conduction type third semiconductor layer and a second metal layer, wherein the first conduction type second semiconductor layer is positioned on the surface of the first conduction type first semiconductor layer; the second conduction type first well region and the second conduction type second well region are arranged in the first conduction type second semiconductor layer; the first conduction type first source region and the first conduction type second source region are respectively arranged in partial regions of the second conduction type first well region and the second conduction type second well region; the first insulating layer partially covers the source regions and the well regions; the polycrystalline silicon layer is arranged on the first insulating layer; the second insulating layer covers the polycrystalline silicon layer and partial source regions; the first metal layer covers the source regions, the well regions and the second insulating layers; the second conduction type third semiconductor layer is arranged on the back surface of the first conduction type first semiconductor layer; the second metal layer is arranged on the back surface of the second conduction type third semiconductor layer; and the forbidden band width of the first conduction type second semiconductor layer is wider than that of the first conduction type first semiconductor layer. The semiconductor power device can effectively inhibit the contradiction between on-state loss and voltage endurance.
Description
Technical field
The invention belongs to semiconductor applications, relate in particular to a kind of semiconductor power device.
Background technology
High frequency, height is withstand voltage, low-loss is semiconductor power device always important performance are pursued, and semiconductor power device has combined ambipolar and advantage MOS type power device, between aspects such as frequency, withstand voltage, loss, have obtained well compromise.The continuous development of power electronics industry, also increasingly high to the performance requirement of semiconductor power device.In order to reduce the on-state voltage drop of semiconductor power device, thereby reduce on-state loss, introduce a kind of structure of crying the barrier layer; N raceway groove IGBT as shown in Figure 1 comprises barrier layer 103, drift region 104; Well region 102 and 112, the doping content on said barrier layer 103 is higher than the doping content of drift region 104, because the difference of doping content; Many sons between barrier layer 103 and drift region 104 diffuse to form a potential barrier, and this potential barrier has barrier effect to few son of barrier layer 103 stored, thereby few son is not easy to be collected by anti-trap partially-drift region knot; Improved near the carrier concentration of device surface; The electricity that has strengthened near surface is led modulating action, has effectively reduced on-state voltage drop, thereby reduces on-state loss.The way that should lack sub-barrier layer generally is on the entire device surface or the impurity identical with drift layer is spread in selectable zone, forms the doped region of certain thickness higher concentration.
Yet there is defective in the method on this traditional fabrication barrier layer.Particularly, because this barrier layer is to utilize the higher relatively doped region of near surface to form, when device is in cut-off state; Anti-inclined to one side trap-drift region knot depletion layer extends, and theoretical according to the pn knot, doping content is high more; Be unfavorable for the extension of depletion layer more, thereby reduced the withstand voltage of device.A kind of existing solution is for adopting the spacing dwindle unit's bag, and is withstand voltage thereby the distance of dwindling well region guarantees, then concerning entire device; Will certainly increase the quantity of unit's bag, thus the negative effect that brings two aspects: and on the one hand, unit's bag quantity increases; Mean that the ratio that the well region area accounts for increases; Thereby the area of collecting minority carrier increases, and has reduced electricity and has led modulating action, has weakened the effect on barrier layer; On the other hand, the increase of unit's bag quantity causes that gully density increases, and the size of gully density is directly proportional with the short circuit current size, increases gully density and means that short circuit current increases, and the self-current limiting capacity of device weakens like this, has reduced the robustness of device.
Summary of the invention
The present invention provides a kind of novel semi-conductor power device for solving in the prior art technical problem of contradiction between the device on-state loss and device withstand voltage.
The objective of the invention is to realize through following technical scheme:
A kind of semiconductor power device; Comprise first conduction type, first semiconductor layer; Be positioned at first conduction type, second semiconductor layer of first conduction type, first semiconductor layer surface; Be arranged at second conduction type, first well region in first conduction type, second semiconductor layer, and second conduction type, second well region that separates with said second conduction type, first well region; Be arranged at first conduction type, first source region in the said second conduction type first well region subregion, and be arranged at first conduction type, second source region in the said second conduction type second well region subregion; Be arranged at first insulating barrier that on first conduction type, second semiconductor layer and has partly covered first source region, second source region, first well region and second well region; Be arranged at the polysilicon layer on first insulating barrier; Be arranged on first conduction type, second semiconductor layer and covered second insulating barrier in polysilicon layer and part first source region and second source region; Be arranged on first conduction type, second semiconductor layer and covered the first metal layer of first source region, second source region, first well region, second well region and second insulating barrier; Be arranged at second conduction type the 3rd semiconductor layer at first conduction type, the first semiconductor layer back side; And second metal level that covers second conduction type the 3rd semiconductor layer back side, the energy gap of said first conduction type, second semiconductor layer is greater than the energy gap of first conduction type, first semiconductor layer.
Semiconductor power device provided by the invention, the energy gap of said first conduction type, second semiconductor layer is greater than the energy gap of first conduction type, first semiconductor layer, like this; Identical or the second semiconductor layer doped concentration slightly hour in doping content; Many sub energy levels almost maintain an equal level, and there is bending in the energy level of few son, and this is bent to form the potential barrier of a few son; When the semiconductor power device conducting; This potential barrier has inhibition near the few son that trap, spreads from the drift region, thereby can suppress the become a partner collection of few son of trap-drift region effectively, has improved the carrier concentration of semiconductor power device near surface; Reduce on-state loss, guaranteed the withstand voltage unaffected of device simultaneously again.
Description of drawings
Fig. 1 is the n raceway groove IGBT structural representation that prior art provides.
Fig. 2 is the n raceway groove IGBT structural representation that first embodiment of the invention provides.
Fig. 3 is the n raceway groove IGBT structural representation that second embodiment of the invention provides.
Fig. 4 is n raceway groove IGBT barrier layer and the drift region first band structure sketch map in the embodiment of the invention.
Fig. 5 is n raceway groove IGBT barrier layer and the drift region second band structure sketch map in the embodiment of the invention.
Fig. 6 is p raceway groove IGBT barrier layer and the drift region first band structure sketch map in the embodiment of the invention.
Fig. 7 is p raceway groove IGBT barrier layer and the drift region second band structure sketch map in the embodiment of the invention.
Embodiment
Clearer for technical problem, technical scheme and beneficial effect that the present invention is solved, below in conjunction with accompanying drawing and embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
A kind of semiconductor power device; Comprise first conduction type, first semiconductor layer; Be positioned at first conduction type, second semiconductor layer of first conduction type, first semiconductor layer surface; Be arranged at second conduction type, first well region in first conduction type, second semiconductor layer, and second conduction type, second well region that separates with said second conduction type, first well region; Be arranged at first conduction type, first source region in the said second conduction type first well region subregion, and be arranged at first conduction type, second source region in the said second conduction type second well region subregion; Be arranged at first insulating barrier that on first conduction type, second semiconductor layer and has partly covered first source region, second source region, first well region and second well region; Be arranged at the polysilicon layer on first insulating barrier; Be arranged on first conduction type, second semiconductor layer and covered second insulating barrier in polysilicon layer and part first source region and second source region; Be arranged on first conduction type, second semiconductor layer and covered the first metal layer of first source region, second source region, first well region, second well region and second insulating barrier; Be arranged at second conduction type the 3rd semiconductor layer at first conduction type, the first semiconductor layer back side; And second metal level that covers second conduction type the 3rd semiconductor layer back side, the energy gap of said first conduction type, second semiconductor layer is greater than the energy gap of first conduction type, first semiconductor layer.
Semiconductor power device provided by the invention, the energy gap of said first conduction type, second semiconductor layer is greater than the energy gap of first conduction type, first semiconductor layer, like this; Identical or the second semiconductor layer doped concentration slightly hour in doping content; Many sub energy levels almost maintain an equal level, and there is bending in the energy level of few son, and this is bent to form the potential barrier of a few son; When the semiconductor power device conducting; This potential barrier has inhibition near the few son that trap, spreads from the drift region, thereby can suppress the become a partner collection of few son of trap-drift region effectively, has improved the carrier concentration of semiconductor power device near surface; Reduce on-state loss, guaranteed the withstand voltage unaffected of device simultaneously again.
As first kind of concrete semiconductor power device embodiment; Please refer to shown in Figure 2; This semiconductor power device comprises first conduction type, first semiconductor layer 204; Be positioned at first conduction type, second semiconductor layer 203 on first conduction type, first semiconductor layer 204 surface, be arranged at second conduction type, first well region 2021 in first conduction type, second semiconductor layer 203, and second conduction type, second well region 2022 that separates with said second conduction type, first well region 2021; Be arranged at first conduction type, first source region 2011 in said second conduction type, first well region 2021 subregions, and be arranged at first conduction type, second source region 2012 in said second conduction type, second well region 2022 subregions; Be arranged on first conduction type, second semiconductor layer 203 and part has covered first insulating barrier 207 of first source region 2011, second source region 2012, first well region 2021 and second well region 2022; Said first conduction type, second semiconductor layer 203 is surrounded on first well region 2021 and second well region 2022; And first conduction type, first semiconductor layer 204 is contacted with first insulating barrier 207; Promptly first conduction type, first semiconductor layer 204 is separated into two parts with first conduction type, second semiconductor layer 203; First well region 2021 is arranged in a part of first conduction type, second semiconductor layer 203, and second well region 2022 is arranged in another part of first conduction type, second semiconductor layer 203; Be arranged at the polysilicon layer 209 on first insulating barrier 207; Be arranged on first conduction type, second semiconductor layer 203 and covered polysilicon layer 209 and second insulating barrier 211 in part first source region 2011 and second source region 2012; Be arranged on first conduction type, second semiconductor layer 203 and covered the first metal layer 208 of first source region 2011, second source region 2012, first well region 2021, second well region 2022 and second insulating barrier 211; Be arranged at second conduction type the 3rd semiconductor layer 206 at first conduction type, first semiconductor layer, 204 back sides; And second metal level 210 that covers second conduction type the 3rd semiconductor layer, 206 back sides, the energy gap of said first conduction type, second semiconductor layer 203 is greater than the energy gap of first conduction type, first semiconductor layer 204.Wherein, Said second conduction type the 3rd semiconductor layer 206 is as the collector electrode of semiconductor power device in the present embodiment; Said first conduction type, first semiconductor layer 204 is as the drift region; Said first conduction type, second semiconductor layer 203 is as the barrier layer, and said the first metal layer 208 is as emitter, and said polysilicon layer 209 is as gate pole.
As second kind of concrete semiconductor power device embodiment; Please refer to shown in Figure 3; This semiconductor power device comprises first conduction type, first semiconductor layer 304; Be positioned at first conduction type, second semiconductor layer 303 on first conduction type, first semiconductor layer 304 surface, be arranged at second conduction type, first well region 3021 in first conduction type, second semiconductor layer 303, and second conduction type, second well region 3022 that separates with said second conduction type, first well region 3021; Be arranged at first conduction type, first source region 3011 in said second conduction type, first well region 3021 subregions, and be arranged at first conduction type, second source region 3012 in said second conduction type, second well region 3022 subregions; Be arranged on first conduction type, second semiconductor layer 303 and part has covered first insulating barrier 307 of first source region 3011, second source region 3012, first well region 3021 and second well region 3022; Said first conduction type, second semiconductor layer 303 is surrounded on first well region 3021 and second well region 3022, and first conduction type, first semiconductor layer 304 and first insulating barrier 307 are separated; Be arranged at the polysilicon layer 309 on first insulating barrier 307; Be arranged on first conduction type, second semiconductor layer 303 and covered polysilicon layer 309 and second insulating barrier 311 in part first source region 3011 and second source region 3012; Be arranged on first conduction type, second semiconductor layer 303 and covered the first metal layer 308 of first source region 3011, second source region 3012, first well region 3021, second well region 3022 and second insulating barrier 311; Be arranged at second conduction type the 3rd semiconductor layer 306 at first conduction type, first semiconductor layer, 304 back sides; And second metal level 310 that covers second conduction type the 3rd semiconductor layer, 306 back sides, the energy gap of said first conduction type, second semiconductor layer 303 is greater than the energy gap of first conduction type, first semiconductor layer 304.Wherein, Said second conduction type the 3rd semiconductor layer 306 is as the collector electrode of semiconductor power device in the present embodiment; Said first conduction type, first semiconductor layer 304 is as the drift region; Said first conduction type, second semiconductor layer 303 is as the barrier layer, and said the first metal layer 308 is as emitter, and said polysilicon layer 309 is as gate pole.
As concrete execution mode, the doping content of said first conduction type, second semiconductor layer is smaller or equal to the doping content of first conduction type, first semiconductor layer; As concrete embodiment, the material of said doping is a phosphorus.Particularly, under first conduction type, second semiconductor layer (barrier layer) situation identical with first conduction type, first semiconductor layer (drift region) both sides doping content:
For n raceway groove IGBT, please refer to formation like Fig. 4 and band structure sketch map shown in Figure 5; Wherein, said Ev is a valence band, and Ef is a Fermi level, and Ec is a conduction band.In situation shown in Figure 4; The conduction band of said barrier layer and drift region almost maintains an equal level; The top of valence band on barrier layer then is lower than the drift region, and like this, the electronics of conduction band can flow to the drift region from the barrier layer at an easy rate; And the few sub-hole of drift region must be crossed a potential barrier and could be got in the barrier layer; So this hole blocking layer can flow to first conduction type, second semiconductor layer (barrier layer) from first conduction type, first semiconductor layer (drift region) by blocking hole, collected by well region-drift region knot thereby suppressed few sub-hole effectively, strengthened the minority carrier density of IGBT near surface; Reduce conduction voltage drop, thereby reduced the on-state loss of semiconductor power device.For situation shown in Figure 5, be higher than at the bottom of the conduction band on barrier layer at the bottom of the conduction band of drift region, Fermi level maintains an equal level, but electronics still has the trend that trends towards to the drift region diffusion, helps strengthening electronic current during conducting; Simultaneously; The top of valence band on barrier layer is lower than the drift region equally; Form the potential barrier in hole, suppress few sub-hole and collected by well region-drift region knot, improved the minority carrier density of IGBT near surface effectively from the drift region to barrier layer diffusion; Reduce conduction voltage drop, thereby reduced the on-state loss of semiconductor power device.The difference that energy gap is inconsistent, energy level itself exists causes because this potential barrier in hole is; Be not because the charge carrier diffusion that doped in concentrations profiled causes produces; Therefore, do not need the doping content of hole blocking layer to be higher than the drift region, thereby can not reduce the withstand voltage of device; On the contrary, because the semi-conducting material energy gap of this hole blocking layer is bigger than the semi-conducting material energy gap of drift region, its breakdown electric field is corresponding also big, thereby withstand voltage high all the better.For situation shown in Figure 5, the doping content of hole blocking layer also can be lower than the drift region, thereby also help improving the withstand voltage of device.
For p raceway groove IGBT, please refer to formation like Fig. 6 and band structure sketch map shown in Figure 7; Wherein, said Ev is a valence band, and Ef is a Fermi level, and Ec is a conduction band.IGBT is the same with the n raceway groove, and in situation shown in Figure 6, because the valence band on barrier layer and both sides, drift region is fair relatively, the hole can be easy to move to the drift region from few sub-barrier layer.For electronics; Be higher than the drift region at the bottom of the conduction band on few sub-barrier layer; Therefore the electronics of drift region must be crossed certain potential barrier and could get into few sub-barrier layer; Be the electron affinity energy of the electron affinity energy of said first conduction type, second semiconductor layer less than first conduction type, first semiconductor layer; Electronics is not allowed to change places and is flowed to first conduction type, second semiconductor layer (barrier layer) from first conduction type, first semiconductor layer (drift region), the effective like this carrier concentration that strengthens device surface, thus reduced the forward voltage drop and the loss of device.For situation shown in Figure 7; The top of valence band on few sub-barrier layer is lower than the drift region top of valence band, be higher than at the bottom of the conduction band at the bottom of the conduction band of drift region, but the hole still has the trend from few sub-barrier layer diffusion to the drift region; Be more conducive to flowing through of hole current; Need cross certain potential barrier and electronics flows to less sub-barrier layer from the drift region, effectively strengthen the carrier concentration of IGBT near surface, reduce on-state voltage drop and loss.Equally, because the energy gap on few sub-barrier layer can be lower greater than the energy gap or the doping content of drift region, thereby guarantee that the withstand voltage of device can not descend.
As concrete execution mode, the doping content of said first conduction type, second semiconductor layer is 5e12/cm
3-1e15/cm
3, the doping content of said first conduction type, first semiconductor layer is 5e12/cm
3-1e15/cm
3Particularly, in first kind of concrete semiconductor power device embodiment, the doping content of said first conduction type, second semiconductor layer 203 is 1e14/cm
3, the doping content of said first conduction type, first semiconductor layer 204 is 1e14/cm
3Simultaneously, the doping content in said first source region 2011 and second source region 2012 is 2e19/cm
3, the doping content in said first well region 2021 and second source region 2022 is 1e18/cm
3, the doping content of said second conduction type the 3rd semiconductor layer 206 is 5e
17/ cm
3Particularly, in second kind of concrete semiconductor power device embodiment, the doping content of said first conduction type, second semiconductor layer 303 is 6e13/cm
3, the doping content of said first conduction type, first semiconductor layer 304 is 8e13/cm
3Simultaneously, the doping content in said first source region 3011 and second source region 3012 is 2e19/cm
3, the doping content in said first well region 3021 and second source region 3022 is 1e18/cm
3, the doping content of said second conduction type the 3rd semiconductor layer 306 is 5e17/cm
3
As concrete execution mode; The energy gap of said first conduction type, second semiconductor layer is 1-5eV; The energy gap of said first conduction type, first semiconductor layer is 0.1-3eV, thereby can select suitable semi-conducting material easily, guarantees that the barrier layer energy gap is greater than the drift region energy gap; Stop that effectively few son collected by trap-drift region knot, better realize technique effect of the present invention.
As concrete execution mode; The material of said first conduction type, second semiconductor layer is selected from a kind of in silicon (Si), carborundum (SiC), aluminum phosphate (AlP), indium phosphide (InP), the aluminium arsenide (AlAs), the perhaps bigger semi-conducting material of other energy gap.
As concrete execution mode, the material of said first conduction type, first semiconductor layer is selected from germanium (Ge), SiGe (Si
1-xGe
x), a kind of in the carbon SiGe (SiGeC), the perhaps less semi-conducting material of other energy gap.
As concrete embodiment, in first kind of semiconductor power device, the material of said first conduction type, first semiconductor layer 204 and second conduction type the 3rd semiconductor layer 206 is Si
1-xGe
x, the material in said first conduction type, second semiconductor layer 203, first well region 3021, second source region 3022, first source region 3011 and second source region 3012 is Si.
As concrete execution mode, in semiconductor power device provided by the invention, said first conduction type is the N type, and second conduction type is the P type, specifically please refer to Fig. 2 and first kind of semiconductor power device and second kind of semiconductor power device shown in Figure 3; Certainly, those skilled in the art can also exchange first conduction type and second conduction type on the basis of aforementioned IGBT structure, and promptly said first conduction type is the P type, and second conduction type is the N type.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. semiconductor power device; It is characterized in that; Comprise first conduction type, first semiconductor layer; Be positioned at first conduction type, second semiconductor layer of first conduction type, first semiconductor layer surface, be arranged at second conduction type, first well region in first conduction type, second semiconductor layer, and second conduction type, second well region that separates with said second conduction type, first well region; Be arranged at first conduction type, first source region in the said second conduction type first well region subregion, and be arranged at first conduction type, second source region in the said second conduction type second well region subregion; Be arranged at first insulating barrier that on first conduction type, second semiconductor layer and has partly covered first source region, second source region, first well region and second well region; Be arranged at the polysilicon layer on first insulating barrier; Be arranged on first conduction type, second semiconductor layer and covered second insulating barrier in polysilicon layer and part first source region and second source region; Be arranged on first conduction type, second semiconductor layer and covered the first metal layer of first source region, second source region, first well region, second well region and second insulating barrier; Be arranged at second conduction type the 3rd semiconductor layer at first conduction type, the first semiconductor layer back side; And second metal level that covers second conduction type the 3rd semiconductor layer back side, the energy gap of said first conduction type, second semiconductor layer is greater than the energy gap of first conduction type, first semiconductor layer.
2. semiconductor power device according to claim 1 is characterized in that, said first conduction type, second semiconductor layer is surrounded on first well region and second well region, and first conduction type, first semiconductor layer is contacted with first insulating barrier.
3. semiconductor power device according to claim 1 is characterized in that, said first conduction type, second semiconductor layer is surrounded on first well region and second well region, and first conduction type, first semiconductor layer and first insulating barrier are separated.
4. semiconductor power device according to claim 1 is characterized in that, the doping content of said first conduction type, second semiconductor layer is smaller or equal to the doping content of first conduction type, first semiconductor layer.
5. semiconductor power device according to claim 4 is characterized in that, the doping content of said first conduction type, second semiconductor layer is 5e12/cm
3-1e15/cm
3, the doping content of said first conduction type, first semiconductor layer is 5e12/cm
3-1e15/cm
3
6. semiconductor power device according to claim 4 is characterized in that, the electron affinity energy of said first conduction type, second semiconductor layer is less than the electron affinity energy of first conduction type, first semiconductor layer.
7. semiconductor power device according to claim 1 is characterized in that, the energy gap of said first conduction type, second semiconductor layer is 1-5eV, and the energy gap of said first conduction type, first semiconductor layer is 0.1-3eV.
8. semiconductor power device according to claim 1 is characterized in that, the material of said first conduction type, second semiconductor layer is selected from a kind of in silicon, carborundum, aluminum phosphate, indium phosphide, the aluminium arsenide.
9. semiconductor power device according to claim 1 is characterized in that, the material of said first conduction type, first semiconductor layer is selected from a kind of in germanium, SiGe, the carbon SiGe.
10. according to each described semiconductor power device among the claim 1-9, it is characterized in that said first conduction type is the N type, second conduction type is the P type; Perhaps said first conduction type is the P type, and second conduction type is the N type.
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| CN201210073789.4A CN102760759B (en) | 2011-04-29 | 2012-03-20 | A kind of semiconductor power device |
| PCT/CN2012/074782 WO2012146190A1 (en) | 2011-04-29 | 2012-04-26 | Semiconductor power device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015055108A1 (en) * | 2013-10-15 | 2015-04-23 | 苏州晶湛半导体有限公司 | Group-iii nitride semiconductor device and manufacturing method therefor |
| TWI557878B (en) * | 2013-12-16 | 2016-11-11 | 旺宏電子股份有限公司 | Semiconductor device and method of fabricating the same |
| CN107516670A (en) * | 2017-08-17 | 2017-12-26 | 电子科技大学 | A kind of grid-controlled transistor with high current climbing |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07193232A (en) * | 1993-12-27 | 1995-07-28 | Nissan Motor Co Ltd | Conductivity modulation type transistor |
| EP0837508A2 (en) * | 1996-10-18 | 1998-04-22 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| JP2002184986A (en) * | 2000-12-13 | 2002-06-28 | Mitsubishi Electric Corp | Field-effect semiconductor device |
| DE10117483A1 (en) * | 2001-04-07 | 2002-10-17 | Bosch Gmbh Robert | Semiconductor power component and corresponding manufacturing process |
| US20060292805A1 (en) * | 2005-06-27 | 2006-12-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN101101923A (en) * | 2006-07-07 | 2008-01-09 | 三菱电机株式会社 | Semiconductor device |
| US20090072242A1 (en) * | 2007-09-18 | 2009-03-19 | Cree, Inc. | Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication |
| CN101501859A (en) * | 2006-08-17 | 2009-08-05 | 克里公司 | High power insulated gate bipolar transistors |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63157478A (en) * | 1986-12-22 | 1988-06-30 | Nissan Motor Co Ltd | Conductivity modulating mosfet |
| CN102263127B (en) * | 2010-05-29 | 2013-06-19 | 比亚迪股份有限公司 | MOS (Metal Oxide Semiconductor) type power device and manufacturing method thereof |
-
2012
- 2012-03-20 CN CN201210073789.4A patent/CN102760759B/en active Active
- 2012-04-26 WO PCT/CN2012/074782 patent/WO2012146190A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07193232A (en) * | 1993-12-27 | 1995-07-28 | Nissan Motor Co Ltd | Conductivity modulation type transistor |
| EP0837508A2 (en) * | 1996-10-18 | 1998-04-22 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| JP2002184986A (en) * | 2000-12-13 | 2002-06-28 | Mitsubishi Electric Corp | Field-effect semiconductor device |
| DE10117483A1 (en) * | 2001-04-07 | 2002-10-17 | Bosch Gmbh Robert | Semiconductor power component and corresponding manufacturing process |
| US20060292805A1 (en) * | 2005-06-27 | 2006-12-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN101101923A (en) * | 2006-07-07 | 2008-01-09 | 三菱电机株式会社 | Semiconductor device |
| CN101501859A (en) * | 2006-08-17 | 2009-08-05 | 克里公司 | High power insulated gate bipolar transistors |
| US20090072242A1 (en) * | 2007-09-18 | 2009-03-19 | Cree, Inc. | Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015055108A1 (en) * | 2013-10-15 | 2015-04-23 | 苏州晶湛半导体有限公司 | Group-iii nitride semiconductor device and manufacturing method therefor |
| TWI557878B (en) * | 2013-12-16 | 2016-11-11 | 旺宏電子股份有限公司 | Semiconductor device and method of fabricating the same |
| CN107516670A (en) * | 2017-08-17 | 2017-12-26 | 电子科技大学 | A kind of grid-controlled transistor with high current climbing |
| CN107516670B (en) * | 2017-08-17 | 2019-12-10 | 电子科技大学 | Grid-controlled thyristor with high current rise rate |
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| Publication number | Publication date |
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| CN102760759B (en) | 2016-02-03 |
| WO2012146190A1 (en) | 2012-11-01 |
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