CN100346167C

CN100346167C - Low-power consumption sweep test method based on circuit division

Info

Publication number: CN100346167C
Application number: CNB2005100293018A
Authority: CN
Inventors: 陈进; 杜敏; 郭筝
Original assignee: Shanghai Jiao Tong University
Current assignee: Shanghai Jiao Tong University
Priority date: 2005-09-01
Filing date: 2005-09-01
Publication date: 2007-10-31
Anticipated expiration: 2025-09-01
Also published as: CN1737599A

Abstract

A low power consumption sweep test method based on circuit division belongs to the technical field of tests, which comprises the following procedures that (1) the circuit division: a design is logically divided, after the division, one logical part is corresponding to one sweep test mode; (2) a sweep clock design: when a sweep test is carried out on each logical part, a clock of a sweep time sequence unit of one logical part can be controlled each moment; (3) a separate sweep chain circuit design: after the whole design is logically divided, the relationship of each divided test logical part is inequality; (4) input-output multiplexing: the multiple logical parts have corresponding sweep chains, the sweep chain of each logical part reuses common input and output terminals through a demultiplexer. The present invention reduces the number of sweep triggers which simultaneously carry out the sweep test, greatly reduces instantaneous test power consumption, and also reduces average power consumption. Thereby, the ineffectiveness of a chip because of great power consumption in test procedures is avoided.

Description

The low-power consumption sweep test method of cutting apart based on circuit

Technical field

What the present invention relates to is a kind of method of technical field of measurement and test, specifically is a kind of low-power consumption sweep test method of cutting apart based on circuit.

Background technology

Testability method based on scan chain is used widely in the built-in testing of digital integrated circuit, because this method has increased the controllability and the observability of circuit internal node, has saved testing cost simultaneously.All having carried out Testability Design in present large-scale SOC (system on a chip) (SoC) design, is to add a test pattern for Digital Logic way partly commonly used, under this pattern chip is carried out design for Measurability based on scan chain.When the test of the enterprising line scanning chain of test machine, according to the test vector of input, may have trigger on a large amount of scan chains in upset, at this moment can cause chip instantaneous peak value power consumption excessive, even burn chip.Generally speaking, the power consumption under the scan testing mode is more a lot of than exceeding under the feature operation pattern, and the power consumption during therefore based on testing scanning chain becomes the subject matter that chip designer and Test Engineer pay close attention to.Usually can adopt at present the method that adds the point of interruption or reduce clock frequency to prevent that power consumption is excessive, yet preceding a kind of solution not only needs expending of hardware, and need the test duration.Second kind of suggestion needs less hardware, but reducing clock frequency need increase the extra test duration, can cause the loss of wrong coverage rate simultaneously, because some dynamic error conductively-closeds.

Find through literature search prior art, published " being adapted to the scan chain architecture of low-power consumption " (Adapting scan architectures for low power operation) literary composition in " the international testing meeting " in 2000 10 (Proceedingsof International Test Conference Oct.2000), this article has proposed a kind of scan chain to be divided into the method that a plurality of parts reduce testing power consumption, this method is by being divided into scan chain isometric several parts, the response data of these several parts directly feeds back to testing apparatus and compares in test process, has reduced the shift count of data in scan chain.This method reduces power consumption by the upset that reduces the trigger device, but it need add extra scan chain control module, finishes for the cutting apart of scan chain, and for up to a million SoC, design complexities increases greatly.In addition,, but can't reduce the quantity of T-flip flop simultaneously, therefore can't reduce the instantaneous peak value power consumption though this method has reduced the total power consumption of whole test process.

Summary of the invention

The objective of the invention is to solve the excessive problem of testing power consumption in the large scale integrated circuit design, a kind of low-power consumption sweep test method of cutting apart based on circuit is provided.Make it solve the power problems of test, when testing, just a part of logic is wherein tested at every turn, the instantaneous power consumption when having reduced test like this by avoiding all triggers to overturn simultaneously.

The present invention is achieved by the following technical solutions, comprises following several steps:

1) circuit is cut apart: the instantaneous power consumption that reaches as required requires logical partitioning is carried out in design, divides all corresponding scan testing mode of each logical gate of back.For the design that is divided into N logical gate, its instantaneous power consumption will be reduced to original 1/N.

2) scan clock design: when each logical gate of dividing is carried out sweep test, each has only the clock of the scanning sequence unit (sweep trigger) of a logical gate to control constantly, and the clock of the sweep trigger of other parts is in unactivated state all the time.

3) independent scan chain circuits designs: after carrying out logical division for whole design, the test logic of each division partly is the relation of inequality, and promptly a part of logic is under the test pattern, and the test clock of the logic of other parts is closed, and is equivalent to a black box.At the logical gate under a kind of test pattern and belong between the logical gate under other test patterns and exist the testability problem, promptly the logic of the input end of tested part exists the controllability problem like this, and output exists the observability problem.The existence of testability problem can cause the decline of test coverage.Propose two kinds of schemes among the present invention and solve this problem:

A) divide the test logic part according to clock zone.Signal is fewer alternately between the general different clock-domains, divides according to different clock-domains, and helping can high testability.

B) add independently scan chain between the logical gate of each division, this scan chain input/output terminal directly is connected on the port of chip, walks around the logic inside that is divided.Suppose the scan chain logical add between logical partitioning M1 and M2, independent scan chain logic can both play effect under two kinds of test patterns of test M1 and M2, and clock is closed during operate as normal.When test logic part M1, applied the controllability that excitation increases circuit in the importation of the middle M1 of both mutual exchange channels by the independent scan chain between M1 and the M2 in the past, also can be displaced to the value of the output port of M1 on the output port, increase the observability of M1 test, thereby can increase the test coverage of M1.The independent scan chain that is connecting the input and output of M1 is connecting the output input of M2 equally.Equally, this independently scan chain also can play the observability that increases M2 and the effect of controllability during M2 in test.The adding of independent scan chain makes the test coverage of entire chip improve greatly.

4) input and output are multiplexing: a plurality of logical gates of division all have corresponding scan chain, and the scan chain of Different Logic part can pass through the multiplexing common input/output port of MUX.

The present invention is by being provided with a plurality of scan testing modes, under each scan testing mode, only some scan chain carries out sweep test, other scan chains that do not belong under the current scan testing mode then are in unactivated state, so just whole sweep test power consumption several parts have been divided into, greatly reduce peak value operation power consumption, avoided the generation of ELECTROMIGRATION PHENOMENON effectively.Simultaneously these scan testing modes have identical complexing pin, and promptly the input/output port of corresponding scan chain is the same under every kind of pattern, and therefore multiple sweep test can not cause the sheet increase of pin outward.The present invention has reduced the quantity of carrying out the sweep trigger of sweep test simultaneously, greatly reduces instantaneous testing power consumption, and average power consumption also decreases, thereby has avoided chip to lose efficacy owing to power consumption is excessive in test process.

Description of drawings

Fig. 1 the present invention carries out logical circuit to design cuts apart synoptic diagram

Independent scan chain design diagram among Fig. 2 the present invention

The multiplexing synoptic diagram of the different test pattern scan chain input/output port of Fig. 3

Embodiment

Be example with a process that is divided into the SoC Testability Design of two parts below, the concrete low-power consumption sweep test method of cutting apart based on circuit of introducing, this SoC comprises 40,000 triggers approximately.

At first be that circuit is cut apart, circuit requires to be divided into two sweep test SD1 and SD2 according to power consumption in this embodiment as shown in Figure 1.The scan pattern that SD1 is corresponding different with SD2.SD1 has k module: IP1, IP2 ..., IPk; N module: IP (k+1) arranged among the SD2, IP (k+2) ... IP (k+n).

It then is the scan clock design, when the test scan pattern of corresponding SD1, the CLK1 that is in state of activation can arrive IP1, IP2 ..., all scanning sequence unit among the IPk, and CLK2 is a fixed value, promptly there is not clock can arrive module I P (k+1) among the SD2, IP (k+2) ... IP (k+n).Equally, during the test scan pattern of corresponding SD2, have only CLK2 to activate, can arrive all modules among the SD2, and CLK1 is a fixed value.Test clock CLK1 and CLK2 are generated by the MUX in the test clock module (Test clock unit) by test enable signal test_mode1 and test_mode2, promptly when test_mode1 set, CLK1 is in state of activation, when test_mode2 set, CLK2 is in state of activation.

Be independent scan chain circuits design then, this independent scan chain logic wrapper module as shown in Figure 2, has independent scan input end mouth SI and scanning output end mouth SO.The enable signal of supposing the test pattern of SD1 and SD2 is respectively test_mode1 and test_mode2, and the test enable signal test_mode of then independent scan chain logic is:

test_mode＝test_mode1‖test_mode2

Promptly under the scan testing mode of SD1 and SD2, independent scan chain logic all plays effect.When test_mode1, clock of independent scan chain logic (wrapper_clk) and test enable signal (wrapper_se) have identical input source with the test clock and the enable signal of SD1 part.Equally, when test_mode2, clock of independent scan chain logic (wrapper_clk) and test enable signal (wrapper_se) have identical source with the test clock and the enable signal of SD2 part.

Be that input and output are multiplexing at last, independent scan chain all plays effect under two kinds of test patterns, be with independently scanning input/output port.Under different test patterns, scan chain each other can pass through multiplexing identical input port SI of MUX and output port SO, as shown in Figure 3 respectively for SD1 and SD2.

The circuit that design is finished carries out the vector emulation testing, compares with primary circuit, and total power consumption, test duration and fault coverage are suitable, and the instantaneous peak value power consumption has reduced over half.

Claims

1. low-power consumption sweep test method of cutting apart based on circuit is characterized in that step is as follows:

1) circuit is cut apart: logical partitioning is carried out in design, divided all corresponding scan testing mode of each logical gate of back, for the design that is divided into N logical gate, its instantaneous power consumption will be reduced to original 1/N;

2) scan clock design: when each logical gate of dividing was carried out sweep test, each had only the clock may command of the scanning sequence unit of a logical gate constantly, and the clock of other sweep trigger is in unactivated state all the time;

3) independent scan chain circuits designs: after carrying out logical division for whole design, the test logic of each division partly is the relation of inequality, and promptly a part of logic is under the test pattern, and the test clock of Bu Fen logic is closed in addition, is equivalent to a black box;

4) input and output are multiplexing: a plurality of logical gates of division all have corresponding scan chain, and the scan chain of each logical gate is by the multiplexing common input/output port of MUX;

In the described step 3), the logic of the input end of tested part exists the controllability problem, and this problem solves by taking following two kinds of schemes simultaneously:

A) divide the test logic part according to clock zone;

B) add independently scan chain between the logical gate of each division, this scan chain input/output terminal directly is connected on the port of chip, walks around the logic inside that is divided;

Described b), be implemented as follows:

Suppose that the scan chain logical add is between logical partitioning M1 and M2, independent scan chain logic can both work under two kinds of test patterns of test M1 and M2, clock is closed during operate as normal, when test logic part M1, apply the controllability of excitation increase circuit toward the importation of the middle M1 of both mutual exchange channels by the independent scan chain between M1 and the M2, and the value of the output port of M1 is displaced on the output port, increase the observability of M1 test, thereby increase the test coverage of M1, the independent scan chain that is connecting the input and output of M1 is connecting the output input of M2 equally, equally, this independently scan chain play the observability that increases M2 and the effect of controllability during M2 in test.