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Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips
- Tung-Che Liang,
- Yi-Chen Chang,
- Zhanwei Zhong,
- Yaas Bigdeli,
- Tsung-Yi Ho,
- Krishnendu Chakrabarty,
- Richard Fair
We describe an exciting new application domain for deep reinforcement learning (RL): droplet routing on digital microfluidic biochips (DMFBs). A DMFB consists of a two-dimensional electrode array, and it manipulates droplets of liquid to automatically ...
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis
Logic synthesis is a crucial step in electronic design automation tools. The rapid developments of reinforcement learning (RL) have enabled the automated exploration of logic synthesis. Existing RL based methods may lead to data inefficiency, and the ...
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow
Deep learning has become a highly popular research field, and previously deep learning algorithms ran primarily on CPUs and GPUs. However, with the rapid development of deep learning, it was discovered that existing processors could not meet the specific ...
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks
Cache timing channel attacks exploit the inherent properties of cache memories: hit and miss time along with the shared nature of the cache to leak secret information. The side channel and covert channel are the two well-known cache timing channel ...
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference
Recently Processing-in-Memory (PIM) has become a promising solution to achieve energy-efficient computation in data-intensive applications by placing computation near or inside the memory. In most Deep Learning (DL) frameworks, a user manually partitions ...
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing
For real-time embedded systems, QoS (Quality of Service), fault tolerance, and energy budget constraint are among the primary design concerns. In this research, we investigate the problem of energy constrained standby-sparing for both periodic and ...
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems
Over the past decade, machine learning model complexity has grown at an extraordinary rate, as has the scale of the systems training such large models. However, there is an alarmingly low hardware utilization (5–20%) in large scale AI systems. The low ...
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware
Controllers are mission-critical components of any electronic design. By sending control signals, they decide which and when other data path elements must operate. Faults, especially Single Event Upset (SEU) occurrence in these components, can lead to ...
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning
Recently, GPU-accelerated placers such as DREAMPlace and Xplace have demonstrated their superiority over traditional CPU-reliant placers by achieving orders of magnitude speed up in placement runtime. However, due to their limited focus in placement ...
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking
Time-Sensitive Networking (TSN) realizes high bandwidth and time determinism for data transmission and thus becomes the crucial communication technology in time-critical systems. The Gate Control List (GCL) is used to control the transmission of different ...
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans
Multiple software and hardware intellectual property (IP) components are combined on a single chip to form Multi-Processor Systems-on-Chips (MPSoCs). Due to the rigid time-to-market constraints, some of the IPs are from outsourced third parties. Due to ...
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface
- Bo-Yuan Huang,
- Steven Lyubomirsky,
- Yi Li,
- Mike He,
- Gus Henry Smith,
- Thierry Tambe,
- Akash Gaonkar,
- Vishal Canumalla,
- Andrew Cheung,
- Gu-Yeon Wei,
- Aarti Gupta,
- Zachary Tatlock,
- Sharad Malik
Ideally, accelerator development should be as easy as software development. Several recent design languages/tools are working toward this goal, but actually testing early designs on real applications end-to-end remains prohibitively difficult due to the ...
Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins
Placement is a critical step in the physical design for digital application specific integrated circuits (ASICs), as it can directly affect the design qualities such as wirelength and timing. For many domain specific designs, the demands for high ...
Pareto Optimization of Analog Circuits Using Reinforcement Learning
Analog circuit optimization and design presents a unique set of challenges in the IC design process. Many applications require the designer to optimize for multiple competing objectives, which poses a crucial challenge. Motivated by these practical ...
RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA
Finite field multiplication is a non-linear transformation operator that appears in the majority of symmetric cryptographic algorithms. Numerous specified finite field multiplication units have been proposed as a fundamental module in the coarse-grained ...
A Module-Level Configuration Methodology for Programmable Camouflaged Logic
- Jianfeng Wang,
- Zhonghao Chen,
- Jiahao Zhang,
- Yixin Xu,
- Tongguang Yu,
- Ziheng Zheng,
- Enze Ye,
- Sumitha George,
- Huazhong Yang,
- Yongpan Liu,
- Kai Ni,
- Vijaykrishnan Narayanan,
- Xueqing Li
Logic camouflage is a widely adopted technique that mitigates the threat of intellectual property (IP) piracy and overproduction in the integrated circuit (IC) supply chain. Camouflaged logic achieves functional obfuscation through physical-level ...
Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey
The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today’s ...