2005 Proceeding- General Chair:
- Brad Calder,
- Program Chair:
- Ben Zorn
The Memory Systems Performance workshop has been held on two previous occasions (in 2002 and 2004) and brings together scientists and practitioners from around the globe. Architecture, programming, and application trends have made memory performance a critical issue in the speed and efficiency of computer systems. The workshop is multidisciplinary and fosters collaboration among researchers in a range of fields including compilers, memory management, programming languages, architecture, operating systems, performance evaluation, and database systems.The program committee is pleased to present the proceedings of the 2005 ACM SIGPLAN Workshop on Memory Systems Performance which contains a collection of 8 papers covering a wide range of topics. This year a total of 24 technical papers were submitted to the workshop from North America, South America, Europe, and Asia. Papers were submitted from academic institutions, industrial research labs, and government research labs. Of the 24 papers submitted, 8 were accepted to appear in the proceedings.The submission and review process was done in the following way. Each submission was assigned to at least 3 reviewers. Reviewers were asked to have their initial reviews done one week ahead of time so that conflicting reviews could be discussed before the program committee meeting. The program committee meeting was held as a telephone conference on April 4, 2005. Reviewers who had conflicts of interest with papers that were discussed were asked to leave the phone conference and were then called back after the paper was discussed. Each program committee member reviewed 5-6 papers. Authors of both accepted and rejected papers received written review feedback from the reviewers.
Proceeding Downloads
Recursive data structure profiling
As the processor-memory performance gap increases, so does the need for aggressive data structure optimizations to reduce memory access latencies. Such optimizations require a better understanding of the memory behavior of programs. We propose a ...
Application analysis using memory pressure
As the speeds of microprocessors continue to follow Moore's law, memory speeds keep lagging farther behind so as to make the "memory wall" more and more distinct. In order for a processor architect to be able to evaluate the right micro-architectural ...
Transparent pointer compression for linked data structures
64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and memory bandwidth of the system (compared to 32-bit address spaces). This ...
Impact of modern memory subsystems on cache optimizations for stencil computations
In this work we investigate the impact of evolving memory system features, such as large on-chip caches, automatic prefetch, and the growing distance to main memory on 3D stencil computations. These calculations form the basis for a wide range of ...
Performance characteristics of MAUI: an intelligent memory system architecture
Combining ideas from several previous proposals, such as Active Pages, DIVA, and ULMT, we present the Memory Arithmetic Unit and Interface (MAUI) architecture. Because the "intelligence" of the MAUI intelligent memory system architecture is located in ...
On the importance of optimizing the configuration of stream prefetchers
This paper provides a detailed analysis of how the parameters of hardware prefetchers affect the memory system performance. In particular, we found the configuration of the frequently used stream prefetcher to have a major impact on the runtime, making ...
Gated memory control for memory monitoring, leak detection and garbage collection
In the past, program monitoring often operates at the code level, performing checks at function and loop boundaries. Recent research shows that profiling analysis can identify high-level phases in complex binary code. Examples are time steps in ...
A locality-improving dynamic memory allocator
In general-purpose applications, most data is dynamically allocated. The memory manager therefore plays a crucial role in application performance by determining the spatial locality of heap objects. Previous general-purpose allocators have focused on ...
- Proceedings of the 2005 workshop on Memory system performance
Recommendations
Acceptance Rates
| Year | Submitted | Accepted | Rate |
|---|---|---|---|
| MSPC '14 | 20 | 6 | 30% |
| Overall | 20 | 6 | 30% |