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Transparent pointer compression for linked data structures

Published: 12 June 2005 Publication History

Abstract

64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and memory bandwidth of the system (compared to 32-bit address spaces). This paper presents a sophisticated, automatic transformation that shrinks pointers from 64-bits to 32-bits. The approach is "macroscopic," i.e., it operates on an entire logical data structure in the program at a time. It allows an individual data structure instance or even a subset thereof to grow up to 232 bytes in size, and can compress pointers to some data structures but not others. Together, these properties allow efficient usage of a large (64-bit) address space. We also describe (but have not implemented) a dynamic version of the technique that can transparently expand the pointers in an individual data structure if it exceeds the 4GB limit. For a collection of pointer-intensive benchmarks, we show that the transformation reduces peak heap sizes substantially by (20% to 2x) for several of these benchmarks, and improves overall performance significantly in some cases.

References

[1]
A. Adl-Tabatabai, J. Bharadwaj, M. Cierniak, M. Eng, J. Fang, B. Lewis, B. Murphy, and J. Stichnoth. Improving 64-bit Java IPF performance by compressing heap references. In Proc. 2004 Int'l Symposium on Code Generation and Optimization, pages 100--110, Mar. 2004.]]
[2]
C. S. Ananian and M. Rinard. Data Size Optimizations for Java Programs. In LCTES, San Diego, CA, Jun 2003.]]
[3]
T. Austin, et al. The Pointer-intensive Benchmark Suite. www.cs.wisc.edu/~austin/ptr-dist.html, Sept 1995.]]
[4]
B.-C. Cheng and W. mei Hwu. Modular interprocedural pointer analysis using access paths: Design, implementation, and evaluation. In PLDI, pages 57--69, Vancouver, British Columbia, Canada, June 2000.]]
[5]
J. S. Foster, M. Fähndrich, and A. Aiken. Polymorphic versus monomorphic flow-insensitive points-to analysis for c. In SAS'00: Proc. 7th Int'l Symp. on Static Analysis, pages 175--198, London, UK, 2000.]]
[6]
G. Heiser, K. Elphinstone, J. Vochteloo, S. Russell, and J. Liedtke. The Mungi single-address-space operating system. Software -- Practice and Experience, 28(9):901--928, 1998.]]
[7]
C. Lattner. Macroscopic Data Structure Analysis and Optimization. PhD thesis, Computer Science Dept., University of Illinois at Urbana-Champaign, Urbana, IL, May 2005. See http://11vm.cs.uiuc.edu.]]
[8]
C. Lattner and V. Adve. Automatic Pool Allocation for Disjoint Data Structures. In Proc. ACM SIGPLAN Workshop on Memory System Performance, Berlin, Germany, Jun 2002.]]
[9]
C. Lattner and V. Adve. LLVM: A Compilation Framework for Lifelong Program Analysis and Transformation. In Proc. 2004 Int'l Symp. on Code Generation and Optimization (CGO'04), San Jose, USA, Mar 2004.]]
[10]
C. Lattner and V. Adve. Automatic pool allocation: Improving performance by controlling data structure layout in the heap. In Proc. 2005 ACM SIGPLAN Conf. on Programming Language Design and Implementation (PLDI'05), Chicago, IL, Jun 2005.]]
[11]
D. Liang and M. J. Harrold. Efficient computation of parameterized pointer information for interprocedural analysis. In SAS, July 2001.]]
[12]
J. C. Mogul, J. F. Bartlett, R. N. Mayo, and A. Srivastava. Performance implications of multiple pointer sizes. In USENIX Winter, pages 187--200, 1995.]]
[13]
E. M. Nystrom, H.-S. Kim, and W. mei W. Hwu. Bottom-up and top-down context-sensitive summary-based pointer analysis. In SAS, 2004.]]
[14]
A. Rogers, M. Carlisle, J. Reppy, and L. Hendren. Supporting dynamic data structures on distributed memory machines. TOPLAS, 17(2), Mar. 1995.]]
[15]
H. Shacham, M. Page, B. Pfaff, E.-J. Goh, N. Modadugu, and D. Boneh. On the effectiveness of address-space randomization. In Proc. ACM Conf. on Computer And Communications Security, pages 298--307, 2004.]]
[16]
M. Takagi and K. Hiraki. Field array compression in data caches for dynamically allocated recursive data structure. In Proceedings of 5th International Symposium on High Performance Computing (ISHPC'03), Tokyo-Odaiba, Japan, October 2003, pages 127--145.]]
[17]
D. N. Truong, F. Bodin, and A. Seznec. Improving cache behavior of dynamically allocated data structures. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'98), pages 322--329, Oct. 1998.]]
[18]
C. Yarvin, R. Bukowski, and T. Anderson. Anonymous RPC: Low-latency protection in a 64-bit address space. In USENIX Summer, pages 175--186, 1993.]]
[19]
Y. Zhang and R. Gupta. Data compression transformations for dynamically allocated data structures. In International Conference on Compiler Construction (CC), Apr 2002.]]
[20]
C. B. Zilles. Benchmark health considered harmful. SIGARCH Comput. Archit. News, 29(3):4--5, 2001.]]

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    cover image ACM Other conferences
    MSP '05: Proceedings of the 2005 workshop on Memory system performance
    June 2005
    74 pages
    ISBN:1595931473
    DOI:10.1145/1111583
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    Published: 12 June 2005

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    Author Tags

    1. cache
    2. data layout
    3. pointer compression
    4. recursive data structure
    5. static analysis

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    MSP05: Memory Systems Performance Workshop
    June 12, 2005
    Illinois, Chicago

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