Article

Low Power Adder with Adaptive Supply Voltage

Authors:

Hiroaki Suzuki,

Woopyo Jeong,

Kaushik RoyAuthors Info & Claims

ICCD '03: Proceedings of the 21st International Conference on Computer Design

Page 103

Published: 13 October 2003 Publication History

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Abstract

Demands for the low power VLSI have been pushing thedevelopment of aggressive design methodologies to reducethe power consumption drastically. To meet the growingdemand, we propose a low power adder, which adaptivelyselects supply voltages based on the input vector patterns.We prototyped a 32-bit Ripple Carry Adder and analyzedthe power consumption and performance in details.Results show 29% improvement in power consumptionover a conventional ripple carry adder with comparableperformance.

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Bahadori MKamal MAfzali-Kusha AAfsharnezhad YSalehi E(2017)CL-CPAIntegration, the VLSI Journal10.5555/3063717.306372757:C(62-68)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.5555/3063717.3063727
Ghosh SRoy KKyung CChoi KHa S(2008)Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretchingProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356955(635-640)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356955
Chen YLi HLi JKoh CMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Variable-latency adder (VL-adder)Proceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283822(195-200)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283822
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Low Power Adder with Adaptive Supply Voltage
1. Hardware

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ICCD '03: Proceedings of the 21st International Conference on Computer Design

October 2003

ISBN:0769520251

Publisher

IEEE Computer Society

United States

Publication History

Published: 13 October 2003

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Bahadori MKamal MAfzali-Kusha AAfsharnezhad YSalehi E(2017)CL-CPAIntegration, the VLSI Journal10.5555/3063717.306372757:C(62-68)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.5555/3063717.3063727
Ghosh SRoy KKyung CChoi KHa S(2008)Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretchingProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356955(635-640)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356955
Chen YLi HLi JKoh CMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Variable-latency adder (VL-adder)Proceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283822(195-200)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283822
Mohapatra DKarakonstantis GRoy KMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Low-power process-variation tolerant arithmetic units using input-based elastic clockingProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283797(74-79)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283797
Chen YLi HRoy KKoh CRoy KTiwari V(2005)Cascaded carry-select adder (C2SA)Proceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077634(115-118)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077634
Uht A(2005)Uniprocessor Performance Enhancement through Adaptive Clock Frequency ControlIEEE Transactions on Computers10.1109/TC.2005.3454:2(132-140)Online publication date: 1-Feb-2005
https://dl.acm.org/doi/10.1109/TC.2005.34
Roberts DAustin TBlauww DMudge TFlautner K(2005)Error Analysis for the Support of Robust Voltage ScalingProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.53(65-70)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.53
Suzuki HJeong WRoy KJoshi RChoi KTiwari VRoy K(2004)Low-power carry-select adder using adaptive supply voltage based on input vector patternsProceedings of the 2004 international symposium on Low power electronics and design10.1145/1013235.1013312(313-318)Online publication date: 9-Aug-2004
https://dl.acm.org/doi/10.1145/1013235.1013312

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Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Estimation of Low Power Multi-Supply Voltage Level Shifter

A novel low-power full-adder cell for low voltage

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