Article

Cascaded carry-select adder (C²SA): a new structure for low-power CSA design

Authors:

Yiran Chen,

Hai Li,

Kaushik Roy,

Cheng-Kok KohAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 115 - 118

https://doi.org/10.1145/1077603.1077634

Published: 08 August 2005 Publication History

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Abstract

In this paper we propose a novel low-power Carry-Select Adder (CSA) design called Cascaded CSA (C2SA). Based on the prediction of the critical path delay of current operation, C²SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C²SA in 180nm Technology show that C²SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) Latency Per Operation (LPO) compared to standard CSA

References

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http://www-device.eecs.berkeley.edu/~ptm.

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Cited By

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Ndai PRafique NThottethodi MGhosh SBhunia SRoy K(2019)TrifectaIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200749118:1(53-65)Online publication date: 21-Nov-2019
https://dl.acm.org/doi/10.1109/TVLSI.2008.2007491
Ghosh SMohapatra DKarakonstantis GRoy K(2018)Voltage scalable high-speed robust hybrid arithmetic units using adaptive clockingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202253118:9(1301-1309)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2022531
Goel AGhosh SMeterelliyoz MParkhurst JRoy K(2011)Integrated Design & TestProceedings of the 2011 Asian Test Symposium10.1109/ATS.2011.100(486-491)Online publication date: 20-Nov-2011
https://dl.acm.org/doi/10.1109/ATS.2011.100
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Index Terms

Cascaded carry-select adder (C²SA): a new structure for low-power CSA design
1. Hardware
  1. Integrated circuits
  2. Very large scale integration design

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A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but with speed penalty. This paper proposes a new add-one circuits using the ...
An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit
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This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular and iterative-shared transistor structure very suitable for implementation in VLSI. This adder is based on both a static and compact multi-output ...
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ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. ...

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Published In

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 August 2005

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ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Ndai PRafique NThottethodi MGhosh SBhunia SRoy K(2019)TrifectaIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200749118:1(53-65)Online publication date: 21-Nov-2019
https://dl.acm.org/doi/10.1109/TVLSI.2008.2007491
Ghosh SMohapatra DKarakonstantis GRoy K(2018)Voltage scalable high-speed robust hybrid arithmetic units using adaptive clockingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202253118:9(1301-1309)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2022531
Goel AGhosh SMeterelliyoz MParkhurst JRoy K(2011)Integrated Design & TestProceedings of the 2011 Asian Test Symposium10.1109/ATS.2011.100(486-491)Online publication date: 20-Nov-2011
https://dl.acm.org/doi/10.1109/ATS.2011.100
Ghosh SRoy KKyung CChoi KHa S(2008)Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretchingProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356955(635-640)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356955
Ndai PBhunia SAgarwal ARoy K(2008)Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved ThroughputIEEE Transactions on Computers10.1109/TC.2008.4057:7(940-951)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1109/TC.2008.40
Chen YLi HLi JKoh CMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Variable-latency adder (VL-adder)Proceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283822(195-200)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283822
Mohapatra DKarakonstantis GRoy KMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Low-power process-variation tolerant arithmetic units using input-based elastic clockingProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283797(74-79)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283797

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High-Performance Carry Select Adder Using Fast All-One Finding Logic

An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit

Low-power carry-select adder using adaptive supply voltage based on input vector patterns

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High-Performance Carry Select Adder Using Fast All-One Finding Logic

An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit

Low-power carry-select adder using adaptive supply voltage based on input vector patterns

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