Article

Garp: a MIPS processor with a reconfigurable coprocessor

Authors:

J. R. Hauser,

J. WawrzynekAuthors Info & Claims

FCCM '97: Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines

Page 12

Published: 16 April 1997 Publication History

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Abstract

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

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FCCM '97: Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines

April 1997

ISBN:0818681594

Publisher

IEEE Computer Society

United States

Publication History

Published: 16 April 1997

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Jindal NChandran SPanda PPrasad SMitra ASinghal KGupta STuli S(2019)DHOOMProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317799(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317799
Zhao BLiang XAn NLu HZhang ZEmrouznejad AQian Z(2018)The Design of Heterogeneous Multi-core Reconfigurable Mobile Terminal ArchitectureProceedings of the 2nd International Conference on Computer Science and Application Engineering10.1145/3207677.3278021(1-5)Online publication date: 22-Oct-2018
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Vipin KFahmy S(2018)FPGA Dynamic and Partial ReconfigurationACM Computing Surveys10.1145/319382751:4(1-39)Online publication date: 25-Jul-2018
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