NBTI mitigation by giving random scan-in vectors during standby mode
Abstract
Negative Bias Temperature Instability (NBTI) is one of the serious concerns for circuit performance degradation. NBTI degrades PMOS transistors under negative bias, whereas without negative bias they recovers. In this paper, we propose a mitigation method for NBTIinduced performance degradation that exploits the recovery property by shifting random input sequence through scan paths. With this method, we prevent consecutive stress that causes large degradation. Experimental results reveal that random scan-in vectors successfully mitigate NBTI and the path delay degradation is reduced by 71% in a test case when standby mode occupies 10% of total time.
References
[1]
Wang, W., Reddy, V., Krishnan, A.T., Vattikonda, R., Krishnan, S., Cao, Y.: Compact modeling and simulation of circuit reliability for 65nm CMOS technology. IEEE Transactions on Device and Material Reliability 7, 509-517 (2007).
[2]
Ramey, S., Prasad, C., Agostinelli, M., Pae, S., Walstra, S., Gupta, S., Hicks, J.: Frequency and Recovery Effects in High- k BTI Degradation. In: International Reliability Physics Symposium, pp. 1023-1027 (2009).
[3]
Abdollahi, A., Fallah, F., Pedram, M.: Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Transactions on Very Large Scale Integration Systems 12(2), 140-154 (2004).
[4]
Wang, Y., Luo, H., He, K., Luo, R., Yang, H., Xie, Y.: Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. In: Design, Automation, and Test in Europe conference, pp. 546-551 (2007).
[5]
Wang, Y., Chen, X., Wang, W., Balakrishnan, V., Cao, Y., Xie, Y., Yang, H.: On the efficacy of input vector control to mitigate NBTI effects and leakage power. In: International Symposium on Quality Electronic Design, pp. 19-26 (2009).
[6]
Bild, D.R., Bok, G., Dick, R.P.: Minimization of NBTI performance degradation using internal node control. In: Design, Automation, and Test in Europe Conference, pp. 148-153 (2009).
[7]
Jin, S., Zhang, L., Li, H., Li, X., Yan, G.: M-IVC: Using Multiple Input Vectors to Minimize Aging-induced Delay. In: Asian Test Symposium, pp. 437-442 (2009).
[8]
Calimera, A., Macii, E., Poncino, M.: NBTI-aware sleep transistor design for reliable power-gating. In: Great Lakes Symposium on VLSI, pp. 333-338 (2009).
[9]
Konoura, H., Mitsuyama, Y., Hashimoto, M., Onoye, T.: Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. In: International Symposium on Quality Electronic Design, pp. 646-651 (2010).
[10]
Cao, Y.: Reliability mechanisms and the impact on IC designs. In: Asia and South Pacific Design Automation Conference, Tutorial, vol. 4, pp. 342-372 (2009).
[11]
Alam, M.A., Mahapatra, S.: A comprehensive model of PMOS NBTI degradation. Microelectronics Reliability 45, 71-81 (2005).
[12]
Lee, J.H., Wu, W.H., Islam, A.E., Alam, M.A., Oates, A.S.: Separation method of hole trapping and interface trap generation and their roles in NBTI reaction-diffusion model. In: International Reliability Physics Symposium, pp. 745-746 (2008).
[13]
Krishnan, A.T., Chansellor, C., Chakravarthi, S., Nicollian, P.E., Reddy, V., Varghese, A., Khamankar, R.B., Krishnan, S.: Material dependence of hydrogen diffusion: implications for NBTI degradation. In: IEEE International Electron Devices Meeting, pp. 688-691 (2005).
- NBTI mitigation by giving random scan-in vectors during standby mode
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Published In
September 2011
352 pages
ISBN:9783642241536
Sponsors
- Universidad Complutense de Madrid
- IEEE Council on Electronic Design Automation (CEDA)
Publisher
Springer-Verlag
Berlin, Heidelberg
Publication History
Published: 26 September 2011
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