Negative Bias Temperature Instability (NBTI) has been regarded as most important source of reliability of CMOS devices, and specifically pMOS transistors.

In this work we focus on the NBTI-induced degradation of sleep transistor cells More in details we present a practical SPICE-based analysis framework for evaluating delay degradation of power-gated circuits due to NBTI-induced current capability reducing of pMOS sleep transistor. We also describe three NBTI-tolerant pMOS sleep transistor cell design approaches, in which the V<_i>th increase due to NBTI is compensated through (i) sleep-transistor over-sizing, (ii) forward-body-biasing, (iii) equivalent 0-probability reduction of the sleep-transistor driving signal.

Characterization results on a commercial 45nm CMOS technology define fundamental guide-lines to be used during NBTI-aware sleep-transistor design, while experiments on an industrial benchmark highlight the importance of considering NBTI effect on pMOS sleep transistor design, emphasizing the effectiveness of the proposed design methodologies: more than 85% of time-life extension.