article

Free access

Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats

Authors:

Scott A. Mahlke,

B. Ramakrishna RauAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 5, Issue 4

Pages 752 - 773

https://doi.org/10.1145/362652.362658

Published: 01 October 2000 Publication History

Abstract

PICO is a fully automated system for designing the architecture and the microarchitecture of VLIW and EPIC processors. A serious concern with this class of processors, due to their very long instructions, is their code size. One focus of this paper is to describe a series of code size minimization techniques used within PICO, some of which are applied during the automatic design of the instruction format, while others are applied during program assembly. The design of a retargetable assembler to support these techniques also poses certain novel challenges, which constitute the second focus of this paper. Contrary to widely held perceptions, we demonstrate that it is entirely possible to design VLIW and EPIC processors that are capable of issuing large numbers of operational per cycle, but whose code size is only moderately larger than that for a sequential CISC processor.

References

[1]

ADITYA, S., RAU, B. R., AND JOHNSON, R. C. 2000. Automatic design of VLIW and EPIC instruction formats. HPL Technical Report HPL-1999-94, Hewlett-Packard Laboratories.

[2]

ADITYA, S., RAU, B. R., AND KATHAIL, V. 1999. Automatic architectural synthesis of VLIW and EPIC processors. In International Symposium on System Synthesis, ISSS'99 (San Jose, California, 1999), IEEE Computer Society, 107-113.

[3]

ARNOLD, M. AND CORPORAAL, H. 1999. Instruction set synthesis using operation pattern detection. In Fifth Annual Conference of ASCI (Heijen, The Netherlands, 1999).

[4]

BECK, G. R., YEN, D. W. L., AND ANDERSON, T. L. 1993. The cydra 5 mini-supercomputer: architecture and implementation. The Journal of Supercomputing 7, 1/2, 143-180.

Digital Library

[5]

COLWELL, R. P., NIX, R. P., O'DONNELL, J. J., PAPWORTH, D. B., AND RODMAN, P. K. 1988. A vliw architecture for a trace scheduling compiler. IEEE Transactions on Computers 37, 8, 967-979.

Digital Library

[6]

CONTE, T. M., BANERJIA, S., LARIN, S. Y., MENEZES, K. N., AND SATHAYE, S. W. 1996. Instruction fetch mechanisms for VLIW architectures with compressed encodings. In 29th International Symposium on Microarchitecture (1996), 201-211.

Digital Library

[7]

HANONO, S. AND DEVADAS, S. 1998. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In 35th Design Automation Conference (1998), 510-515.

[8]

INTEL CORPORATION. 1999. IA-64 Application Developer's Architecture Guide.

[9]

KATHAIL, V., SCHLANSKER, M., AND RAU, B. R. 2000. HPL-PD architecture specification: Version 1.1. Technical Report HPL-93-80 (R.1), Hewlett-Packard Laboratories.

[10]

KOZUCH, M. AND WOLFE, A. 1994. Compression of embedded system programs. In IEEE International Conference on Computer Design (1994). 270-277.

Digital Library

[11]

LEE, C., POTKONJAK, M., AND MANGIONE-SMITH, W. H. 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communication systems. In 30th Annual International Symposium on Microarchitecture (MICRO-30) (1997). ACM and IEEE Computer Society.

[12]

LIAO, S. Y., DEVADAS, S., AND KEUTZER, K. 1998. Code density optimization for embedded DSP processors using data compression techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, 7, 601-608.

Digital Library

[13]

PHILIPS SEMICONDUCTORS. 1997. Trimedia TM-1 Media Processor Data Book.

[14]

RAU, B. R. 1988. Cydra 5 directed dataflow architecture. In COMPCON '88 (San Francisco, 1988), 106-113.

[15]

RAU, B. R., KATHAIL, V., AND ADITYA, S. 1999. Machine-description driven compilers for EPIC and VLIW processors. Design Automation for Embedded Systems 4, 2/3, 71-118.

[16]

SCHLANSKER, M. S. AND RAU, B. R. 2000. EPIC: Explicitly parallel instruction computing. Computer 33, 2, 37-45.

Digital Library

[17]

VAN PRAET, J., GOOSSENS, G., LANNEER, D., AND DE MAN, H. 1994. Instruction set definition and instruction selection for ASIPs. In 7th ACM/IEEE International Symposium on High-Level Synthesis (Niagara-on-the-Lake, Ontario, Canada, 1994). IEEE, 11-16.

Digital Library

[18]

WOLFE, A. AND CHANIN, A. 1992. Executing compressed programs on an embedded risc architecture. In The 25th Annual International Symposium on Microarchitecture (MICRO-25) (1992). IEEE.

Digital Library

Cited By

Sartor ABecker PHoozemans JWong SBeck A(2018)Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW ProcessorIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.27602994:3(327-339)Online publication date: 1-Jul-2018
https://doi.org/10.1109/TMSCS.2017.2760299
Sartor ALorenzon ACarro LKastensmidt FWong SBeck A(2017)Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW ProcessorsACM Journal on Emerging Technologies in Computing Systems10.1145/300193513:2(1-21)Online publication date: 6-Jan-2017
https://dl.acm.org/doi/10.1145/3001935
Sartor AWong SBeck A(2016)Adaptive ILP control to increase fault tolerance for VLIW processors2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2016.7760767(9-16)Online publication date: Jul-2016
https://doi.org/10.1109/ASAP.2016.7760767
Show More Cited By

Index Terms

Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats

Recommendations

A design of EPIC type processor based on MIPS architecture
Abstract
This paper proposes an EPIC (Explicitly Parallel Instruction Computing Architecture) type processor based on MIPS. VLIW processors can execute multiple instructions simultaneously, but due to dependency of instructions, it is often impossible to ...
Reducing code size in VLIW instruction scheduling
Low-power Embedded Systems

Code size is an important concern in embedded systems. VLIW architectures are popular for embedded systems, but often increase code size, by requiring NOPs to be inserted into the code to satisfy instruction placement constraints. Existing VLIW ...
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions

Existing trend of processors shows a progress toward customizable and reconfigurable architectures. In this paper, we study the benefit of combining the architectural design of a VLIW DSP and the concepts of modern customizable processors like ASIPs (...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 5, Issue 4

Oct. 2000

86 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/362652

Editor:
Mary Jane Irwin
Pennsylvania State Univ., University Park

Issue’s Table of Contents

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 2000

Published in TODAES Volume 5, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

20
Total Citations
View Citations
749
Total Downloads

Downloads (Last 12 months)95
Downloads (Last 6 weeks)23

Reflects downloads up to 04 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Sartor ABecker PHoozemans JWong SBeck A(2018)Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW ProcessorIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.27602994:3(327-339)Online publication date: 1-Jul-2018
https://doi.org/10.1109/TMSCS.2017.2760299
Sartor ALorenzon ACarro LKastensmidt FWong SBeck A(2017)Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW ProcessorsACM Journal on Emerging Technologies in Computing Systems10.1145/300193513:2(1-21)Online publication date: 6-Jan-2017
https://dl.acm.org/doi/10.1145/3001935
Sartor AWong SBeck A(2016)Adaptive ILP control to increase fault tolerance for VLIW processors2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2016.7760767(9-16)Online publication date: Jul-2016
https://doi.org/10.1109/ASAP.2016.7760767
Kultala HViitanen TJääskeläinen PHelkala JTakala J(2016)Improving Code Density with Variable Length Encoding Aware Instruction SchedulingJournal of Signal Processing Systems10.1007/s11265-015-1081-684:3(435-446)Online publication date: 1-Sep-2016
https://dl.acm.org/doi/10.1007/s11265-015-1081-6
Davis BBaird RGavin PSjälander MFinlayson IRasapour FCook GUh GWhalley DTyson GIyer RGarg S(2015)Scheduling instruction effects for a statically pipelined processorProceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.5555/2830689.2830710(167-176)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.5555/2830689.2830710
Davis BBaird RGavin PSjalander MFinlayson IRasapour FCook GUh GWhalley DTyson G(2015)Scheduling instruction effects for a statically pipelined processor2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2015.7324557(167-176)Online publication date: Oct-2015
https://doi.org/10.1109/CASES.2015.7324557
Kultala HViitanen TJaaskelainen PHelkala JTakala J(2014)Compiler optimizations for code density of variable length instructions2014 IEEE Workshop on Signal Processing Systems (SiPS)10.1109/SiPS.2014.6986074(1-6)Online publication date: Oct-2014
https://doi.org/10.1109/SiPS.2014.6986074
Qin WMalik S(2010)Architecture Description Languages for Retargetable CompilationThe Compiler Design Handbook10.1201/9781420040579.ch14Online publication date: 7-Mar-2010
https://doi.org/10.1201/9781420040579.ch14
Catthoor FRaghavan PLambrechts AJayapala MKritikakou AAbsar JCatthoor FRaghavan PLambrechts AJayapala MKritikakou AAbsar J(2010)Global State-of-the-Art OverviewUltra-Low Energy Domain-Specific Instruction-Set Processors10.1007/978-90-481-9528-2_2(17-32)Online publication date: 3-Jul-2010
https://doi.org/10.1007/978-90-481-9528-2_2
Malik SQin W(2009)Architecture Description Languages for Retargetable CompilationThe Compiler Design Handbook10.1201/9781420043839.ch16(16-1-16-27)Online publication date: 7-Dec-2009
https://doi.org/10.1201/9781420043839.ch16
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Figures

Tables

Media

View Issue’s Table of Contents