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Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip

Authors:

Janardhan Rao Doppa,

Partha Pratim Pande,

Krishnendu ChakrabartyAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 24, Issue 6

Article No.: 62, Pages 1 - 22

https://doi.org/10.1145/3357158

Published: 17 September 2019 Publication History

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Abstract

Monolithic-3D-integration (M3D) improves the performance and energy efficiency of 3D ICs over conventional through-silicon-vias-based counterparts. The smaller dimensions of monolithic inter-tier vias offer high-density integration, the flexibility of partitioning logic blocks across multiple tiers, and significantly reduced total wire-length enable high-performance and energy-efficiency. However, the performance of M3D ICs degrades due to the presence of electrostatic coupling when the inter-layer-dielectric thickness between two adjacent tiers is less than 50nm. In this work, we evaluate the performance of an M3D-enabled Network-on-chip (NoC) architecture in the presence of electrostatic coupling. Electrostatic coupling induces significant delay and energy overheads for the multi-tier NoC routers. This in turn results in considerable performance degradation if the NoC design methodology does not incorporate the effects of electrostatic coupling. We demonstrate that electrostatic coupling degrades the energy-delay-product of an M3D NoC by 18.1% averaged over eight different applications from SPLASH-2 and PARSEC benchmark suites. As a countermeasure, we advocate the adoption of electrostatic coupling-aware M3D NoC design methodology. Experimental results show that the coupling-aware M3D NoC reduces performance penalty by lowering the number of multi-tier routers significantly.

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Index Terms

Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 24, Issue 6

November 2019

275 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3357467

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

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Copyright © 2019 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 17 September 2019

Accepted: 01 July 2019

Revised: 01 June 2019

Received: 01 November 2018

Published in TODAES Volume 24, Issue 6

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