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Boundary-Functional Broadside and Skewed-Load Tests

Published: 21 December 2018 Publication History

Abstract

Close-to-functional broadside tests are used for avoiding overtesting of delay faults that can result from non-functional operation conditions, while avoiding test escapes because of faults that cannot be detected under functional operation conditions. When a close-to-functional broadside test deviates from functional operation conditions, the deviation can affect the entire circuit. This article defines the concept of a boundary-functional broadside test where non-functional operation conditions are prevented from crossing a preselected boundary. Using the procedure described in this article, the boundary maintains the same values under a boundary-functional broadside test as under a functional broadside test from which it is derived. Indirectly, this ensures that the deviations from functional operation conditions throughout the entire circuit are limited. The concept of a boundary-functional broadside test is extended to skewed-load tests, and to partial-boundary-functional tests. Experimental results are presented for benchmark circuits to demonstrate the fault coverage improvements that can be achieved using boundary-functional broadside and skewed-load tests as well as partial-boundary-functional tests of both types.

References

[1]
Muzaffer O. Simsir, Ajay Bhoj, and Niraj K. Jha. 2010. Fault modeling for FinFET circuits. In Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’10). IEEE Press, Piscataway, NJ, 41--46. http://dl.acm.org/citation.cfm?id=1835957.1835969.
[2]
Dong Xiang, Zhen Chen, and Laung-Terng Wang. 2012. Scan flip-flop grouping to compress test data and compact test responses for launch-on-capture delay testing. ACM Trans. Des. Autom. Electron. Syst. 17, 2, Article 18 (April 2012), 24 pages.
[3]
Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han (Hans) Tsai, Wu-Tung Cheng, Stephen Sunter, Yung-Fa Chou, and Ding-Ming Kwai. 2012. Small delay testing for TSVs in 3-D ICs. In Proceedings of the 49th Annual Design Automation Conference (DAC’12). ACM, New York, NY, 1031--1036.
[4]
Arijit Mondal, P. P. Chakrabarti, and Pallab Dasgupta. 2012. Symbolic-event-propagation-based minimal test set generation for robust path delay faults. ACM Trans. Des. Autom. Electron. Syst. 17, 4, Article 47 (Oct. 2012), 20 pages.
[5]
Matthias Sauer, Alexander Czutro, Ilia Polian, and Bernd Becker. 2012. Small-delay-fault ATPG with waveform accuracy. In Proceedings of the International Conference on Computer-Aided Design (ICCAD’12). ACM, New York, NY, 30--36.
[6]
Wei Zhao, Junxia Ma, Mohammad Tehranipoor, and Sreejit Chakravarty. 2013. Power-safe application of tdf patterns to flip-chip designs during wafer test. ACM Trans. Des. Autom. Electron. Syst. 18, 3, Article 43 (July 2013), 20 pages.
[7]
Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, and Pascal Trotta. 2015. SATTA: A self-adaptive temperature-based TDF awareness methodology for dynamically reconfigurable FPGAs. ACM Trans. Reconfig. Technol. Syst. 8, 1, Article 1 (March 2015), 22 pages.
[8]
Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, and Masahiro Fujita. 2015. Temperature-aware software-based self-testing for delay faults. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE’15). EDA Consortium, San Jose, CA, 423--428. http://dl.acm.org/citation.cfm?id=2755753.2755850.
[9]
A. Satya Trinadh, Seetal Potluri, Sobhan Babu Ch., V. Kamakoti, and Shiv Govind Singh. 2017. Optimal don’t care filling for minimizing peak toggles during at-speed stuck-at testing. ACM Trans. Des. Autom. Electron. Syst. 23, 1, Article 5 (Aug. 2017), 26 pages.
[10]
J. Rearick. 2001. Too much delay fault coverage is a bad thing. In Proceedings of the International Test Conference 2001 (Cat. No.01CH37260). 624--633.
[11]
J. Saxena, K. M. Butler, V. B. Jayaram, S. Kundu, N. V. Arvind, P. Sreeprakash, and M. Hachinger. 2003. A case study of ir-drop in structured at-speed testing. In Proceedings of the International Test Conference 2003 (ITC’03), Vol. 1. 1098--1104.
[12]
S. Sde-Paz and E. Salomon. 2008. Frequency and power correlation between at-speed scan and functional tests. In Proceedings of the 2008 IEEE International Test Conference. 1--9.
[13]
I. Pomeranz. 2004. On the generation of scan-based test sets with reachable states for testing under functional operation conditions. In Proceedings of the 41st Design Automation Conference 2004. 928--933.
[14]
Yung-Chieh Lin, Feng Lu, Kai Yang, and Kwang-Ting Cheng. 2005. Constraint extraction for pseudo-functional scan-based delay testing. In Proceedings of the Asia and South Pacific Design Automation Conference 2005 (ASP-DAC’05), Vol. 1. 166--171.
[15]
Zhuo Zhang, S. M. Reddy, and I. Pomeranz. 2005. On generating pseudo-functional delay fault tests for scan designs. In Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05). 398--405.
[16]
I. Polian and H. Fujiwara. 2006. Functional constraints vs. test compression in scan-based delay testing. In Proceedings of the Design Automation Test in Europe Conference, Vol. 1. 1--6.
[17]
I. Pomeranz and S. M. Reddy. 2006. Generation of functional broadside tests for transition faults. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 25, 10 (Oct. 2006), 2207--2218.
[18]
I. Pomeranz and S. M. Reddy. 2009. Definition and generation of partially-functional broadside tests. IET Compu. Digital Techn. 3, 1 (January 2009), 1--13.
[19]
E. K. Moghaddam, J. Rajski, M. Kassab, and S. M. Reddy. 2010. At-speed scan test with low switching activity. In Proceedings of the 2010 28th VLSI Test Symposium (VTS’10). 177--182.
[20]
M. Valka, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, E. Sanchez, M. De Carvalho, and M. S. Reorda. 2011. A functional power evaluation flow for defining test power limits during at-speed delay testing. In Proceedings of the 2011 16th IEEE European Test Symposium. 153--158.
[21]
I. Pomeranz. 2011. Scan shift power of functional broadside tests. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 30, 9 (Sep. 2011), 1416--1420.
[22]
T. Zhang and D. M. Hank Walker. 2013. Power supply noise control in pseudo functional test. In Proceedings of the 2013 IEEE 31st VLSI Test Symposium (VTS’11). 1--6.
[23]
A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, and M. S. Reorda. 2015. Exploring the impact of functional test programs re-used for power-aware testing. In Proceedings of the 2015 Design, Automation Test in Europe Conference and Exhibition (DATE’15). 1277--1280.
[24]
I. Pomeranz. 2015. Generation of close-to-functional broadside tests with equal primary input vectors. In Proceedings of the 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC’15). 1--6.
[25]
I. Pomeranz. 2015. Piecewise-functional broadside tests based on reachable states. IEEE Trans. Comput. 64, 8 (Aug. 2015), 2415--2420.
[26]
Irith Pomeranz. 2018. Partially invariant patterns for LFSR-based generation of close-to-functional broadside tests. ACM Trans. Des. Autom. Electron. Syst. 23, 4, Article 53 (May 2018), 18 pages.
[27]
S. V. Kodakara, M. V. Sagar, and J. Yuen. 2015. Extracting effective functional tests from commercial programs. In Proceedings of the 2015 IEEE 33rd VLSI Test Symposium (VTS’15). 1--6.
[28]
I. Pomeranz. 2018. A static test compaction procedure for large pools of multicycle functional broadside tests. IET Comput. Digital Techn. 12, 5 (Sep. 2018), 233--240.
[29]
I. Pomeranz and S. M. Reddy. 2008. Primary input vectors to avoid in random test sequences for synchronous sequential circuits. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 27, 1 (Jan. 2008), 193--197.

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  1. Boundary-Functional Broadside and Skewed-Load Tests

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    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 24, Issue 1
    January 2019
    309 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/3293467
    • Editor:
    • Naehyuck Chang
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 21 December 2018
    Accepted: 01 September 2018
    Revised: 01 August 2018
    Received: 01 May 2018
    Published in TODAES Volume 24, Issue 1

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    Author Tags

    1. Functional broadside tests
    2. functional test sequences
    3. skewed-load tests
    4. switching activity
    5. test generation
    6. transition faults

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