Article

Thread-associative memory for multicore and multithreaded computing

Authors:

Shuo Wang,

Lei WangAuthors Info & Claims

ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design

Pages 139 - 142

https://doi.org/10.1145/1165573.1165606

Published: 04 October 2006 Publication History

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Abstract

Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction.

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Cited By

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Wang LPatel N(2019)Improving error tolerance for multithreaded register filesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515827.151583416:8(1009-1020)Online publication date: 21-Nov-2019
https://dl.acm.org/doi/10.5555/1515827.1515834
Zhuravlev SSaez JBlagodurov SFedorova APrieto M(2012)Survey of scheduling techniques for addressing shared resources in multicore processorsACM Computing Surveys (CSUR)10.1145/2379776.237978045:1(1-28)Online publication date: 7-Dec-2012
https://dl.acm.org/doi/10.1145/2379776.2379780
Reddy RPetrov P(2010)Cache partitioning for energy-efficient and interference-free embedded multitaskingACM Transactions on Embedded Computing Systems (TECS)10.1145/1698772.16987749:3(1-35)Online publication date: 5-Mar-2010
https://dl.acm.org/doi/10.1145/1698772.1698774
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Index Terms

Thread-associative memory for multicore and multithreaded computing
1. Computer systems organization
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design

October 2006

446 pages

ISBN:1595934626

DOI:10.1145/1165573

General Chairs:
Wolfgang Nebel
University of Oldenburg and OFFIS
,
Mircea Stan
University of Virginia
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Joerg Henkel
University of Karlsruhe
,
Diana Marculescu
Carnegie Mellon University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 October 2006

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ISLPED06

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ISLPED06: International Symposium on Low Power Electronics and Design

October 4 - 6, 2006

Bavaria, Tegernsee, Germany

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Wang LPatel N(2019)Improving error tolerance for multithreaded register filesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515827.151583416:8(1009-1020)Online publication date: 21-Nov-2019
https://dl.acm.org/doi/10.5555/1515827.1515834
Zhuravlev SSaez JBlagodurov SFedorova APrieto M(2012)Survey of scheduling techniques for addressing shared resources in multicore processorsACM Computing Surveys (CSUR)10.1145/2379776.237978045:1(1-28)Online publication date: 7-Dec-2012
https://dl.acm.org/doi/10.1145/2379776.2379780
Reddy RPetrov P(2010)Cache partitioning for energy-efficient and interference-free embedded multitaskingACM Transactions on Embedded Computing Systems (TECS)10.1145/1698772.16987749:3(1-35)Online publication date: 5-Mar-2010
https://dl.acm.org/doi/10.1145/1698772.1698774
Reddy RPetrov PKim TSainrat PLumetta SNavarro N(2007)Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systemsProceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1289881.1289917(198-207)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289881.1289917

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