Article

A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs

Authors:

Jianwei Zhang,

Yizheng Ye,

Binda LiuAuthors Info & Claims

ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design

Pages 135 - 138

https://doi.org/10.1145/1165573.1165605

Published: 04 October 2006 Publication History

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Abstract

A new mismatch-dependent low-power technique is presented for content-addressable memories (CAMs). With a novel shadow match-line voltage-detecting scheme, the word circuits realize fast self-disable of the charging paths in case of mismatches. Since the majority of CAMs words are mismatched, a significant power is reduced with a high search speed. Simulation results show the proposed 256-word-144-bit ternary CAM, using 0.13-?m 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900 ps search time. The achievement illustrates a 77% energy-delay-product (EDP) reduction as compared to the speed-optimized current-saving scheme.

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Cited By

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Lakshmi GMahmood MKusuma VBasha D(2022)Analysis of TG Based Content Addressable Memory Circuits2022 International Conference on Applied Artificial Intelligence and Computing (ICAAIC)10.1109/ICAAIC53929.2022.9792775(1772-1777)Online publication date: 9-May-2022
https://doi.org/10.1109/ICAAIC53929.2022.9792775
Chen YOguntoyinbo O(2019)Power efficient packet classification using cascaded bloom filter and off-the-shelf ternary CAM for WDM networksComputer Communications10.1016/j.comcom.2008.11.00232:2(349-356)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1016/j.comcom.2008.11.002
Rajendar SRamakrishna P(2017)A novel high performance design of memory architecture using modified 4T CAM cell2017 International Conference on Inventive Communication and Computational Technologies (ICICCT)10.1109/ICICCT.2017.7975202(272-277)Online publication date: Mar-2017
https://doi.org/10.1109/ICICCT.2017.7975202
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Index Terms

A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design

October 2006

446 pages

ISBN:1595934626

DOI:10.1145/1165573

General Chairs:
Wolfgang Nebel
University of Oldenburg and OFFIS
,
Mircea Stan
University of Virginia
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Joerg Henkel
University of Karlsruhe
,
Diana Marculescu
Carnegie Mellon University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 October 2006

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ISLPED06

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ISLPED06: International Symposium on Low Power Electronics and Design

October 4 - 6, 2006

Bavaria, Tegernsee, Germany

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Lakshmi GMahmood MKusuma VBasha D(2022)Analysis of TG Based Content Addressable Memory Circuits2022 International Conference on Applied Artificial Intelligence and Computing (ICAAIC)10.1109/ICAAIC53929.2022.9792775(1772-1777)Online publication date: 9-May-2022
https://doi.org/10.1109/ICAAIC53929.2022.9792775
Chen YOguntoyinbo O(2019)Power efficient packet classification using cascaded bloom filter and off-the-shelf ternary CAM for WDM networksComputer Communications10.1016/j.comcom.2008.11.00232:2(349-356)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1016/j.comcom.2008.11.002
Rajendar SRamakrishna P(2017)A novel high performance design of memory architecture using modified 4T CAM cell2017 International Conference on Inventive Communication and Computational Technologies (ICICCT)10.1109/ICICCT.2017.7975202(272-277)Online publication date: Mar-2017
https://doi.org/10.1109/ICICCT.2017.7975202
Parmar MMalathi P(2017)Low Power Master Slave Matchline Design for CAM Using Modified XNOR Cell2017 International Conference on Computing, Communication, Control and Automation (ICCUBEA)10.1109/ICCUBEA.2017.8463845(1-5)Online publication date: Aug-2017
https://doi.org/10.1109/ICCUBEA.2017.8463845
Ramakrishna PRajendar SMalladhi N(2017)Design of low power memory architecture using 4T content addressable memory cell2017 4th International Conference on Advanced Computing and Communication Systems (ICACCS)10.1109/ICACCS.2017.8014618(1-6)Online publication date: Jan-2017
https://doi.org/10.1109/ICACCS.2017.8014618
Do AYin CVelayudhan KLee ZYeo KKim T(2014)0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation ToleranceIEEE Journal of Solid-State Circuits10.1109/JSSC.2014.231624149:7(1487-1498)Online publication date: Jul-2014
https://doi.org/10.1109/JSSC.2014.2316241

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