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Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system

Published: 24 January 2006 Publication History

Abstract

This paper addresses the problem of minimizing energy consumption of a computer system performing periodic hard real-time tasks with precedence constraints. In the proposed approach, dynamic power management and voltage scaling techniques are combined to reduce the energy consumption of the CPU and devices. The optimization problem is first formulated as an integer programming problem. Next, a three-phase solution framework, which integrates power management scheduling and task voltage assignment, is proposed. Experimental results show that the proposed approach outperforms existing methods by an average of 18% in terms of the systemwide energy savings.

References

[1]
L. Benini, A. Bogliolo and G. De Micheli, "A survey of design techniques for system-level dynamic power management," IEEE Trans on VLSI, vol.8 iss.3, pp.299--316, 2000.
[2]
J. Luo and N. Jha, "Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems," ASP-DAC, pp. 719--26, 2002.
[3]
F. Gruian and K. Kuchchinski, "LEneS: task scheduling for low-energy systems using variable supply voltage processors," ASP-DAC, pp. 449--55, 2001.
[4]
Y. Zhang, X. Hu, and D. Z. Chen, "Task scheduling and voltage selection for energy minimization," DAC, pp. 183--8, 2002.
[5]
Y-H Lu, L. Benini and G. De Micheli, "Low-power task scheduling for multiple devices," CODES, pp. 39--43, 2000.
[6]
V. Swaminathan and K. Chakrabarty, "Pruning-based energy-optimal device scheduling for hard real-time systems," CODES, pp. 175--80, 2002.
[7]
Y-H Lu, L. Benini and G. De Micheli, "Power-aware operating systems for interactive systems," IEEE Trans. on VLSI, vol. 10 iss.2, pp. 119--34, 2002.
[8]
V. Swaminathan and K. Chakrabarty, "Energy-conscious, deterministic I/O device scheduling in hard real-time systems," IEEE Trans. on CAD, vol.22 iss.7, pp.847--58, 2003.
[9]
J. Liu and P. H. Chou, "Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization," ICCAD, pp. 21--28, 2004.
[10]
R. Jejurikar and R. Gupta, "Dynamic voltage scaling for system-wide energy minimization in real-time embedded systems," ISLPED, pp. 78--81, 2001.
[11]
K. Choi, W. Lee, Soma and M. Pedram, "Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation," ICCAD, pp. 29--34, 2004.
[12]
Q. Qiu and M. Pedram, "Dynamic power management based on continuous-time Markov decision processes," DAC, pp. 555--561, 1999.
[13]
T. Simunic, L. Benini, A. Acquaviva, P. Glynn and G. De Micheli, "Dynamic voltage scaling and power management for portable systems," DAC, pp.524--529, 2001.
[14]
S. Irani, S. Shukla and R. Gupta, "Algorithms for power savings," SODA, pp. 37 -- 46, 2003.
[15]
http://ziyang.ece.northwestern.edu/tgff.

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                      cover image ACM Conferences
                      ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
                      January 2006
                      998 pages
                      ISBN:0780394518

                      Sponsors

                      • IEEE Circuits and Systems Society
                      • SIGDA: ACM Special Interest Group on Design Automation
                      • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
                      • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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                      IEEE Press

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                      Published: 24 January 2006

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