research-article

Efficient resource utilization for an extensible processor through dynamic instruction set adaptation

Authors:

Muhammad Shafique,

Jörg HenkelAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Issue 10

Pages 1295 - 1308

https://doi.org/10.1109/TVLSI.2008.2002430

Published: 01 October 2008 Publication History

Abstract

State-of-the-art application-specific instruction set processors (ASIPs) allow the designer to define individual prefabrication customizations, thus improving the degree of specialization towards the actual application requirements, e.g., the computational hot spots. However, only a subset of hot spots can be targeted to keep the ASIP within a reasonable size. We propose a modular Special Instruction composition with multiple implementation possibilities per Special Instruction, compile-time embedded instructions to trigger a run-time adaptation of the instruction set, and a run-time system that dynamically selects an appropriate variation of the instruction set, i.e., a situation-dependent beneficial implementation for each Special Instruction. We thereby achieve a better efficiency of resource usage of up to 3.0× (average 1.4×) compared with current state-of-the-art ASIPs, resulting in a 3.1× (average 1.4×) improved application performance (compared with a general purpose processor up to 25.7× and average 17.6×).

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Cited By

Diniz CShafique MBampi SHenkel J(2015)A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video CodingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.238451734:2(238-251)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1109/TCAD.2014.2384517
Kornaros GPnevmatikatos D(2013)A survey and taxonomy of on-chip monitoring of multicore systems-on-chipACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244208818:2(1-38)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442088
Choi JKim SHan HGantenbein RKuo T(2011)Accelerating loops for coarse grained reconfigurable architectures using instruction extensionsProceedings of the 2011 ACM Symposium on Research in Applied Computation10.1145/2103380.2103445(314-318)Online publication date: 2-Nov-2011
https://dl.acm.org/doi/10.1145/2103380.2103445
Show More Cited By

Index Terms

Efficient resource utilization for an extensible processor through dynamic instruction set adaptation
1. Computer systems organization
2. Hardware

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Information & Contributors

Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 16, Issue 10

October 2008

170 pages

ISSN:1063-8210

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Copyright © 2008.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 October 2008

Revised: 23 March 2008

Received: 26 October 2007

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Cited By

Diniz CShafique MBampi SHenkel J(2015)A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video CodingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.238451734:2(238-251)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1109/TCAD.2014.2384517
Kornaros GPnevmatikatos D(2013)A survey and taxonomy of on-chip monitoring of multicore systems-on-chipACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244208818:2(1-38)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442088
Choi JKim SHan HGantenbein RKuo T(2011)Accelerating loops for coarse grained reconfigurable architectures using instruction extensionsProceedings of the 2011 ACM Symposium on Research in Applied Computation10.1145/2103380.2103445(314-318)Online publication date: 2-Nov-2011
https://dl.acm.org/doi/10.1145/2103380.2103445
Shafique MMolkenthin BHenkel JDe Micheli GAl-Hashimi BMueller WMacii E(2010)An HVS-based adaptive computational complexity reduction scheme for H.264/AVC video encoder using prognostic early mode exclusionProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871342(1713-1718)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871342
Bauer LShafique MHenkel JRosenstiel WWakabayashi K(2009)MinDegProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629481(335-342)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629481

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