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A novel multi-objective instruction synthesis flow for application-specific instruction set processors

Published: 16 May 2010 Publication History

Abstract

Application-Specific Instruction set Processor (ASIP) has become an increasingly popular platform for embedded systems. Traditional ASIP synthesis flows mainly target performance improvement, with other design metrics not being addressed appropriately. In this paper, we show that traditional custom instruction exploration algorithms and cost estimation methods for performance improvement only are not suitable for other design objectives, such as energy reduction and area minimization. We propose an ASIP design flow that can be adapted to different design objectives and achieve the balance between them. A novel design space exploration algorithm is developed to identify custom instructions for execution acceleration and energy reduction while reducing the hardware overhead.

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cover image ACM Conferences
GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI
May 2010
502 pages
ISBN:9781450300124
DOI:10.1145/1785481
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 16 May 2010

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Author Tags

  1. application-specific instruction set processor (ASIP)
  2. instruction set synthesis

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GLSVLSI '10
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GLSVLSI '10: Great Lakes Symposium on VLSI 2010
May 16 - 18, 2010
Rhode Island, Providence, USA

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