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A Power and Energy Exploration of Network-on-Chip Architectures

Authors:

Arnab Banerjee,

Robert Mullins,

Simon MooreAuthors Info & Claims

NOCS '07: Proceedings of the First International Symposium on Networks-on-Chip

Pages 163 - 172

https://doi.org/10.1109/NOCS.2007.6

Published: 07 May 2007 Publication History

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Abstract

In this study, we analyse the move towards Networks-on- Chips from an energy perspective by accurately modelling a Circuit-Switched router, a Wormhole router and a speculative Virtual-Channel router in a 90nm CMOS process. All the routers are shown to dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data-path. This leads to the key result that, if this trend continues, the energy cost of more elaborate control will not be vast, making it easier to justify. Given effective clock-gating, this additional energy is also shown to be more or less independent of network congestion. Accurate speed and area metrics are also reported for the networks, which will allow a more complete comparison to be made across the NoC architectural space considered.

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Reza M(2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
https://dl.acm.org/doi/10.1145/3591470
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Zoni DFornaciari W(2015)Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based SimulatorsACM Journal on Emerging Technologies in Computing Systems10.1145/275156112:3(1-24)Online publication date: 21-Sep-2015
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Index Terms

A Power and Energy Exploration of Network-on-Chip Architectures
1. Hardware

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NOCS '07: Proceedings of the First International Symposium on Networks-on-Chip

May 2007

304 pages

ISBN:0769527736

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IEEE Computer Society

United States

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Published: 07 May 2007

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Reza M(2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
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Oveis-Gharan MKhan GBarros FPerumalla KEwald R(2014)Power and chip-area aware network-on-chip modeling for system on chip simulationProceedings of the 7th International ICST Conference on Simulation Tools and Techniques10.4108/icst.simutools.2014.254626(178-185)Online publication date: 17-Mar-2014
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Zoni DFornaciari WMacii E(2013)Sensor-wise methodology to face NBTI stress of NoC buffersProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485537(1038-1043)Online publication date: 18-Mar-2013
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Abstract

References

Cited By

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