research-article

ATPG for Heat Dissipation Minimization During Test Application

Authors:

Seongmoon Wang,

Sandeep K. GuptaAuthors Info & Claims

IEEE Transactions on Computers, Volume 47, Issue 2

Pages 256 - 262

https://doi.org/10.1109/12.663775

Published: 01 February 1998 Publication History

Abstract

A new automatic test pattern generator (ATPG) algorithm is proposed that reduces switching activity (between successive test vectors) during test application. The main objective is to permit safe and inexpensive testing of low power circuits and bare die that might otherwise require expensive heat removal equipment for testing at high speeds. Three new cost functions, namely, transition controllability, observability, and test generation costs, have been defined. It has been shown, for a fanout free circuit under test, that the transition test generation cost for a fault is the minimum number of transitions required to test a given stuck-at fault. The proposed algorithm has been implemented and the generated tests are compared with those generated by a standard PODEM implementation for the larger ISCAS85 benchmark circuits. The results clearly demonstrate that the tests generated using the proposed ATPG can decrease the average number of (weighted) transitions between successive test vectors by a factor of 2 to 23.

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Cited By

Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Kumar AKassab MMoghaddam EMukherjee NRajski JReddy STyszer JChen Wang (2015)Isometric Test Data CompressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.243213334:11(1847-1859)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1109/TCAD.2015.2432133
Arvaniti ETsiatouhas Y(2014)Low-Power Scan TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-014-5453-930:3(329-341)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1007/s10836-014-5453-9
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ATPG for Heat Dissipation Minimization During Test Application

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 47, Issue 2

February 1998

128 pages

ISSN:0018-9340

Editor:
Jane W. S. Liu
Univ. of Illinois, Urbana

Issue’s Table of Contents

Copyright © Copyright © 1998 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 February 1998

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Cited By

Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Kumar AKassab MMoghaddam EMukherjee NRajski JReddy STyszer JChen Wang (2015)Isometric Test Data CompressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.243213334:11(1847-1859)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1109/TCAD.2015.2432133
Arvaniti ETsiatouhas Y(2014)Low-Power Scan TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-014-5453-930:3(329-341)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1007/s10836-014-5453-9
Lee L(2013)Observation-Oriented ATPG and Scan Chain Disabling for Capture Power ReductionJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5404-x29:5(625-634)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1007/s10836-013-5404-x
Jayaraman DSethuram RTragoudas SBahar RLombardi FAtienza DBrunvand E(2010)Gating internal nodes to reduce power during scan shiftProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785500(79-84)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785500
Li JXu QHu YLi X(2010)X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201998018:7(1081-1092)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2019980
Chen ZXiang DYin BLombardi FBhanja SMassoud YBahar R(2009)A power-effective scan architecture using scan flip-flops clustering and post-generation fillingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531659(517-522)Online publication date: 10-May-2009
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Czysz DKassab MLin XMrugalski GRajski JTyszer J(2009)Low-power scan operation in test compression environmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203044528:11(1742-1755)Online publication date: 1-Nov-2009
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Li JXu QHu YLi XKyung CChoi KHa S(2008)On reducing both shift and capture power for scan-based testingProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356961(653-658)Online publication date: 21-Jan-2008
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Li JXu QHu YLi XSciuto D(2008)iFillProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403663(1184-1189)Online publication date: 10-Mar-2008
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