article

A survey on application mapping strategies for Network-on-Chip design

Authors:

Pradip Kumar Sahu,

Santanu ChattopadhyayAuthors Info & Claims

Journal of Systems Architecture: the EUROMICRO Journal, Volume 59, Issue 1

Pages 60 - 76

https://doi.org/10.1016/j.sysarc.2012.10.004

Published: 01 January 2013 Publication History

Abstract

Application mapping is one of the most important dimensions in Network-on-Chip (NoC) research. It maps the cores of the application to the routers of the NoC topology, affecting the overall performance and power requirement of the system. This paper presents a detailed survey of the work done in last one decade in the domain of application mapping. Apart from classifying the reported techniques, it also performs a quantitative comparison among them. Comparison has been carried out for larger sized test applications also, by implementing some of the prospective techniques.

References

[1]

Benini, L. and De Micheli, G., Networks on Chips: a new SoC paradigm. IEEE Computer. v35 i1. 70-78.

[2]

W. J. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in: Proceedings of the 38th Design Automation Conference (DAC), 2001, pp. 684-689.

[3]

S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, A. Hemani, A network on chip architecture and design methodology, in: Proceedings of ISVLSI, 2002, pp. 117-124.

[4]

U.Y. Ogras, J. Hu, R. marculescu, Key research problems in NoC design: a holistic perspective, in: Proceedings of the IEEE International Conference on Hardware/Software Codesign and System, Synthesis, 2005, pp. 69-74.

[5]

Marculescu, R., Ogras, U.Y., Peh, L.S., Jerger, N.E. and Hoskote, Y., Outstanding research problems in NoC design: systems, microarchitecture, and circuit perspectives. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems. v28 i1. 03-21.

[6]

Survey of network on chip (NoC) architectures & contributions. Journal of Engineering, Computing and, Architecture. v3 i1.

[7]

R. Pop, S. Kumar, A survey of techniques for mapping and scheduling applications to network on chip systems, ISSN 1404 - 0018, Research Report 04:4, School of Engineering, Jönköping University, 2004.

[8]

G. Chen, F. Li, M. Kandemir, Compiler-directed application mapping for NoC based chip multiprocessors, in: Proceedings of LCTES, 2007, pp. 155-157.

[9]

E. Carvalho, N. Calazans, F. Moraes, Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs, IEEE International Workshop on Rapid system Prototyping (RSP), 2007, pp. 34-40.

[10]

C.L. Chou, R. Marculescu, Incremental runtime application mapping for homogeneous NoCs with multiple voltage levels, in: ACM International Conference on Hardware/Software codesign and system synthesys, 2007, pp. 161-166.

[11]

C.L. Chou, R. Marculescu, User-aware dynamic task allocation in Network-on-Chip, in: Proceedings of Design, Automation and Test in Europe (DATE), 2008, pp. 1232-1237.

Digital Library

[12]

Chou, C.L., Ogras, U.Y. and Marculescu, R., Energy- and performance-aware incremental mapping for NoCs with multiple voltage levels. IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems. v27 i10. 1866-1879.

[13]

E. Carvalho, F. Moraes, Congestion-aware task mapping in heterogeneous MPSoCs, in: International Symposium on SoC, 2008, pp. 1-4.

[14]

Mehran, A., Khademzadeh, A. and Saeidi, S., DSM: a heuristic dynamic spiral mapping algorithm for Network-on-Chip. IEICE Electronics Express. v5 i13. 464-471.

[15]

M.A.A. Faruque, R. Krist, J. Henkel, ADAM: run-time agent based distributed application mapping for on-chip communication, IEEE Design Automation Conference (DAC), 2008, pp. 760-765.

[16]

A.K. Singh, W. Jigang, A. Prakash, T. Srikanthan, Mapping algorithms for NoC-based heterogeneous MPSoC platforms, in: Euromicro Conference on Digital System Design/Architecture, Methods and Tools, 2009, pp. 133-140.

Digital Library

[17]

Singh, A.K., Srikanthan, T., Kumar, A. and Jigang, W., Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms. Journal of System Architecture. v56. 242-255.

Digital Library

[18]

Carvalho, E., Calazans, N. and Moraes, F., Dynamic task mapping for MPSoCs. IEEE Design and Test of Computers. 26-35.

[19]

M. Mandelli, L. Ost, E. Carara, G. Guindani, T. Gouvea, G. Medeiros, F.G. Moraes, Energy-aware dynamic task mapping for NoC-based MPSoCs, in: Proceedings of ISCAS, 2011, pp. 1676-1679.

[20]

M. Mandelli, A. Amory, L. Ost, F.G. Moraes, Multi-task dynamic mapping onto NoC-based MPSoCs, in: Proceedings of the 24th Symposium on Integrated Circuits and System Design, 2011, pp. 191-196.

[21]

A. Weichslgartner, S. Wildermann, J. Teich, Dynamic decentralized mapping of tree-structured applications on NoC architectures, in: IEEE/ACM International Symposium on Network-on-Chip (NOCS), 2011, pp. 201-208.

[22]

A. Bender, MILP based task mapping for heterogeneous multiprocessor systems, in: Proceedings of International conference on Design and Automation (EURO-DAC), 1996, pp. 190-197.

[23]

C. Rhee, H. Jeong, S. Ha, Many-to-Mmany core-switch mapping in 2-D Mesh NoC architectures, in: IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), 2004, pp. 438-443.

[24]

S. Murali, L. Benini, G.D. Micheli, Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees, in: Asia and South Pacific Design Automation Conference (ASP-DAC), 2005, pp. 27-32.

[25]

Srinivasan, K., Chatha, K.S. and Konjevod, G., Linear-programming-based techniques fo synthesis of Network-on-Chip architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. v14 i4. 407-420.

[26]

C. Ostler, K.S. Chatha, An ILP formulation for system-level application mapping on network processor architecture, in: Proceedings of Design, Automation and Test in Europe (DATE), 2007, pp. 1-6.

[27]

O. Ozturk, M. Kandemir, S.W. Son, An ILP based approach to reducing energy consumption in NoC based CMPs, in: IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2007, pp. 411-414.

[28]

P. Ghosh, A. Sen, A. Hall, Energy efficient application mapping to NoC processing elements operating at multiple voltage levels, in: IEEE International Symposium on Network-on-Chip (NoCS), 2009, pp. 80-85.

Digital Library

[29]

J. Huang, C. Buckl, A. Raabe, A. Knool, Energy-aware task allocation for Network-on-Chip based heterogeneous multiprocessor systems, in: Euromicro International Conference on Parallel, Distributed and Network based Processing (PDP), 2011, pp. 447-454.

Digital Library

[30]

C.L. Chou, R. Marculescu, Contention-aware application mapping for Network-on-Chip communication architectures, in: IEEE International Conference on Computer Design (ICCD), 2008, pp. 164-169.

[31]

S. Tosun, O. Ozturk, M. Ozen, An ILP formulation for application mapping onto Network-on-Chips, in: International Conference on Application of Information and Communication Technologies (AICT), 2009, pp. 1-5.

[32]

Tosun, S., Clustered-based application mapping method for Network-on-Chip. Journal of Advances in Engineering Software. v42 i10. 868-874.

[33]

J. Hu, R. Marculescu, Energy-aware mapping for tile-based NoC architectures under performance constraints, in: Asia and South Pacific Design Automation Conference (ASP-DAC), 2003, pp. 233-239.

[34]

J. Hu, R. Marculescu, Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures, in: Proceedings of Design, Automation and Test in Europe (DATE), 2003, pp. 688-693.

[35]

Hu, J. and Marculescu, R., Energy- and performance-aware mapping for regular NoC architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. v24 i4. 551-562.

[36]

T.J. Lin, S.Y. Lin, A.Y. Wu, Traffic-balanced IP mapping algorithm for 2D-Mesh on-chip-networks, in: IEEE Workshop on Signal Processing Systems (SiPS), 2008, pp. 200-203.

[37]

Reshadi, M., Khademzadeh, A. and Reza, A., Elixir: a new bandwidth-constrained mapping for networks-on-chip. IEICE Electronics Express. v7 i2. 73-79.

[38]

T. Lei, S. Kumar, A two-step genetic algorithm for mapping task graphs to a network on chip architecture, in: Proceedings of the Euromicro Symposium on Digital System Design (DSD), 2003, pp. 180-187.

Digital Library

[39]

W. Zhou, Y. Zhang, Z. Mao, An application specific NoC mapping for optimized delay, in: IEEE International Conference on Design and Test of Integrated Systems in Nanoscale (DTIS), 2006, pp. 184-188.

[40]

G. Ascia, V. Catania, M. Palesi, Multi-objective mapping for mesh-based NoC architectures, in: ACM International Conference on Hardware/Software Codesign and System Synthesis, 2004, pp. 182-187.

[41]

Ascia, G., Catania, V. and Palesi, M., Multi-objective genetic approach to mapping problem on Network-on-Chip. Journal of Universal Computer Science. v12 i4. 370-394.

[42]

Multi-objective mapping for NoC architecture. Journal of Digital Information Management. v5. 378-384.

[43]

R.K. Jena, G.K. Sharma, A multi-objective evolutionary algorithm based optimization model for Network-on-Chip synthesis, in: IEEE International Conference on Information Technology (ITNG), 2007, pp. 977-982.

[44]

K. Bhardwaj, R.K. Jena, Energy and bandwidth aware mapping of IPs onto regular NoC architectures using multi-objective genetic algorithms, in: International Symposium on System-on-Chip (SOC), 2009, pp. 27-31.

[45]

F.M. Darbari, A. Khademzadeh, G.G. Fard, Evaluating the performance of a chaos genetic algorithm for solving the network on chip mapping problem, in: International Conference on Computational Science and Engineering, 2009, pp 366-373.

[46]

Darbari, F.M., Khademzadeh, A. and Fard, G.G., CGMAP: a new approach to Network-on-Chip mapping problem. IEICE Electronics Express. v6 i1. 27-34.

[47]

Fard, G.G., Khademzadeh, A. and Darbari, F.M., Evaluating the performance of one-dimensional chaotic maps in Network-on-Chip mapping problem. IEICE Electronics Express. v6 i12. 811-817.

[48]

GBMAP: an evolutionary approach to mapping cores onto a mesh-based NoC architecture. Journal of Communication and Computer. v7 i3. 1-7.

[49]

Fen, G. and Ning, W., Genetic algorithm based mapping and routing approach for network on chip architectures. Chinese Journal of Electronics. v19 i1. 91-96.

[50]

W. Jang, D.Z. Pan, A3MAP: Architecture-aware analytic mapping for Network-on-Chip, in: Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp. 523-528.

[51]

N. Choudhary, M.S. Gaur, V. Laxmi, V. Singh, Energy aware design methodologies for application specific NoC, in: Proceedings of NORCHIP, 2010, pp. 1-4.

[52]

N. Choudhary, M.S. Gaur, V. Laxmi, V. Singh, GA based congestion aware topology generation for application specific NoC, in: IEEE International Symposium on Electronics Design, Test, and Application, 2011, pp. 93-98.

Digital Library

[53]

M.J. Sepulveda, M. Strum, W.J. Chau, A multi-objective adaptive immune algorithm for NoC mapping, in: International Conference on Very Large Scale Integration (VLSI-SOC), 2009, pp. 193-196.

[54]

M.J. Sepulveda, M. Strum, W.J. Chau, G. Gogniat, A multi-objective approach for multi-application NoC mapping, in: IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2011, pp. 1-4.

[55]

I. Kennedy, R.C. Eberhart, Particle swarm optimization, in: Proceedings of IEEE International Conference on Neural Networks, NJ, 1995, pp. 1942-1948.

[56]

Zhou, W., Zhang, Y. and Mao, Z., Link-load balance aware mapping and routing for NoC. WSEAS Transactions on Circuits and Systems. v6 i11. 583-591.

[57]

A.R. Fekr, A. Khademzadeh, M. Janidarmian, V.S. Bokharaei, Bandwidth/fault/contention aware application-specific NoC using PSO as a mapping generator, in: Proceedings of the World Congress on Engineering (WCE), vol. 1, 2010, pp. 247-252.

[58]

W. Lei, L. Xiang, Energy- and latency-aware NoC mapping based on discrete particle swarm optimization, in: Proceedings of IEEE International Conference on Communications and Mobile Computing, 2010, pp. 263-268.

[59]

A.H. Benyamina, P. Boulet, A. Aroul, S. Eltar, K. Dellal, Mapping real time applications on NoC architecture with hybrid multi-objective algorithm, in: International Conference on Metaheuristics and Nature Inspired, Computing, 2010, pp. 1-10.

[60]

P.K. Sahu, P. Venkatesh, S. Gollapalli, S. Chattopadhyay, Application mapping onto mesh structured Network-on-Chip using particle swarm optimization, in: IEEE International symposium on VLSI (ISVLSI), 2011, pp. 335-336.

[61]

K. Wang, L. Huang, C. Zhou, W. Pang, Particle swarm optimization for traveling salesman problem, in: Proceedings of the Second International Conference on Machine Learning and Cybermetics, 2003, pp. 1583-1585.

[62]

Yuhui Shi, Russell Eberhart, Parameter Selection in Particle Swarm Optimization, Springer Berlin/ Heidelberg, vol. 1447/1998, 2006, pp. 591-600.

[63]

Colorni, A., Dorigo, M. and Maniezzo, V., Distributed optimization by ant colonies, actes de la première conférence européenne sur la vie artificielle. 1991. France, Elsevier Publishing, Paris.

[64]

Wang, J., Li, Y., Chai, S. and Peng, Q., Bandwidth-aware application mapping for NoC-based MPSoCs. Journal of Computational Information Systems. v7 i1. 152-159.

[65]

N. Koziris, M. Romesis, P. Tsanakas, G. Papakonstantinou, An efficient algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures, in: Proceedings of 8th Euro PDP, 2000, pp. 406-413.

[66]

A. Hansson, K. Goossens, A. Radulescu, A unified approach to constrained mapping and routing on Network-on-Chip architectures, in: IEEE/ACM International Conference on Hardware/Software Codesign and System, Synthesis (CODES+ISSS), 2005, pp. 75-80.

Digital Library

[67]

S. Saeidi, A. Khademzadeh, A. Mehran, SMAP: An intelligent mapping tool for network on chip, in: International Symposium on Signals, Circuits and Systems (ISSCS), 2007, pp. 1-4.

[68]

Mehran, R., Saeidi, S., Khademzadeh, A. and Kusha, A.A., Spiral: a heuristic mapping algorithm for network on chip. IEICE Electronics Express. v4 i15. 478-484.

[69]

T. Shen, C.H. Chao, Y.K. Lien, A.Y. Wu, A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network, in: Proceedings of NOCS'07, 2007, pp. 317-322.

[70]

Tavanpour, M., Khademzadeh, A. and Janidarmian, M., Chain-mapping for mesh based Network-on-Chip architecture. IEICE Electronics Express. v6 i22. 1535-1541.

[71]

Y. Chen, L. Xie, J. Li, An energy-aware heuristic constructive mapping algorithm for network on chip, in: International Conference on ASIC (ASICON), 2009, pp. 101-104.

[72]

A. Patooghy, H. Tabkhi, S.G. Miremadi, RMAP: a reliability-aware application mapping for Network-on-Chips, in: International Conference on Dependability, 2010, pp. 112-117.

[73]

B. Yang, T.C. Xu, T. Santti, J. Plosila, Tree-model based mapping for energy-efficient and low-latency Network-on-Chip, in: International Symposium on Design and Diagnostics of Electronics Circuits and Systems (DDECS), 2010, pp. 189-192.

[74]

Tosun, S., New heuristic algorithm for energy aware application mapping and routing on mesh-based NoCs. Journal of System Architecture. v57. 69-78.

[75]

S. Murali, G. De Micheli, Bandwidth constrained mapping of cores onto NoC architectures, in: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), vol. 2, 2004, pp. 896-901.

[76]

S. Murali, G. De Micheli, SUNMAP: a tool for automatic topolog selection and generation for NoCs, in: Proceedings of 41st Design Automation Conference (DAC), 2004, pp. 914-919.

[77]

K. Srinivasan, K.S. Chatha, A technique for low energy mapping and routing in Network-on-Chip architecture, in: IEEE International Symposiun on Low Power Electronics and Design (ISLPED), 2005, pp. 387-392.

Digital Library

[78]

C. Marcon, N. Calazans, F. Moraes, A. Susin, I. Reis, F. Hessel, Exploring NoC mapping strategies: an energy and timing aware technique, in: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), vol. 1, 2005, pp. 502-507.

[79]

C. Marcon, A. Borin, A. Susin, L. Carro, F. Wagner, Time and energy efficient mapping of embeded applications onto NoCs, in: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), vol. 1, 2005, pp. 33-38.

[80]

Marcon, C.A.M., Moreno, E.I., Calazans, N.L.V. and Moraes, F.G., Comparison of Network-on-Chip mapping algorithms targeting low energy consumption. IET Computer & Digital Technique. v2 i6. 471-482.

[81]

C.A.M. Marcon, J.C.S. Palma, A.A. Susin, R.A.L. Reis, N.L.V. Calazans, F.G. Moraes, Modeling the traffic effect for the application cores mapping problem onto NoCs, VLSI-SoC International Federation for Information Processing, vol. 240/2007, 2007, pp. 179-194.

[82]

H.M. Harmanani, R. Farah, A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area, in: IEEE International Workshop on Circuits and systems and TAISA Conference (NEWCAS-TAISA), 2008, pp. 29-32.

[83]

Z. Lu, L. Xia, A. Jantsch, Cluster-based simulated annealing for mapping cores onto 2D mesh Networks on Chip, in: Proceedings of Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2008, pp. 1-6.

Digital Library

[84]

H. Elmiligi, A.A. Morgan, M.W.E. Kharashi, F. Gebali, Power-aware topology optimization for Network-on-Chips, in: IEEE International Symposium on Circuits and Systems, 2008, PP. 360-363.

[85]

A. Morgan, H. Elmiligi, A.M.W.E. Kharashi, F. Gebali, Application-specific networks-on-chip topology customization using network partitioning, in: 1st International Forum on Next-generation Multicore/manycore Technologies, 2008.

Digital Library

[86]

Elmiligi, H., Morgan, A.A., Kharashi, M.W.E. and Gebali, F., Power optimization for application-specific networks-on-chips: a topology-based approach. Journal of Microprocessor and Microsystems. v33. 343-355.

Digital Library

[87]

M.Y. Yu, M. Li, J.J. Song, F.F. Fu, Y.X. Bai, Pipelining-based high throughput low energy mapping on Network-on-Chip, in: Euromicro International Conference on Digital System Design/Architectures, Methods and Tools, 2009, pp. 427-432.

Digital Library

[88]

Janidarmian, M., Khademzadeh, A. and Tavanpour, M., Onyx: a new heuristic bandwidth-constrained mapping of cores onto network on chip. IEICE Electronics Express. v6 i1. 1-7.

[89]

Saeidi, S., Khademzadeh, A. and Vardi, F., Crinkle: a heuristic mapping algorithm for network on chip. IEICE Electronics Express. v6 i24. 1737-1744.

[90]

X. Wang, M. Yang, Y. Jiang, P. Liu, Power-aware mapping for Network-on-Chip architectures under bandwidth and latency constraints, in: International Conference on Embedded and Multimedia Computing (EM-COM), 2009, pp. 1-6.

[91]

Wang, X., Yang, M., Jiang, Y. and Liu, P., Power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints. ACM Transactions on Architecture and Code Optimization. v7 i1. 1-30.

[92]

M. Janidarmian, A. Khademzadeh, A.R. Fekr, V.S. Bokharaei, Citrine: a methedology for application-specific Network-on-Chips design, in: Proceedings of World Congress on Engineering and Computer Science, vol. 1, 2010, pp. 196-202.

[93]

B. Yang, L. Guang, T.C. Xu, T. Santti, J. Plosila, Multi-application mapping algorithm for Network-on-Chip platforms, in: IEEE 26th Convention of Electrical and Electronics Engineers in Israel (IEEEI), 2010, pp. 540-544.

[94]

P.K. Sahu, N. Shah, K. Manna, S. Chattopadhyay, A new application mapping algorithm for mesh based Network-on-Chip design, in: IEEE International Conference (INDICON), 2010, pp. 1-4.

[95]

Kernighan, B. and Lin, S., An efficient heuristic procedure for partitioning graphs. Bell System Technical Journal. v49 i2. 291-307.

[96]

Z. Chang, G. Xiong, N. Sang, Energy-aware mapping for tree-based NoC architecture by recursive bipartitioning, in: International Conference on Embedded Software and Systems (ICESS), 2008, pp. 105-109.

[97]

D. Majeti, A. Pasalapudi, K. Yalamanchili, Low energy tree based network on chip architectures using homogeneous routers for bandwidth and latency constrained multimedia applications, in: International Conference on Emerging Trends in Engineering and Technology (ICETET), 2009, pp. 358-363.

Digital Library

[98]

P.K. Sahu, N. Shah, K. Manna, S. Chattopadhyay, An application mapping technique for butterfly-fat-tree Network-on-Chip, in: IEEE International Conference on Emerging Applications and Information Technology (EAIT), 2011, pp. 383-386.

Digital Library

[99]

P.K. Sahu, N. Shah, K. Manna, S. Chattopadhyay, A new application mapping strategy for mesh-of-tree based Network-on-Chip, in: IEEE International Conference on Emerging Trends in Electrical and Computer Technology (ICETECT), 2011, pp. 518-523.

[100]

R.P. Dick, D.L. Rhodes, W. Wolf, TGFF: task graphs for free, in: Proceedings of International Workshop on Hardware/Software Codesign, 1998.

[101]

R. Tornero, J.M. Orduna, A. Mejia, J. Flich, J. Duato, CART: communication-aware routing technique for application-specific NoCs, in: IEEE Euromicro Conference on Digital System Design Architecture, Methods and Tools, 2008, pp. 26-31.

[102]

Tornero, R., Orduna, J.M., Mejia, A., Flich, J. and Duato, J., A communication-driven routing technique for application-specific NoCs. International Journal of Parallel Programming. v39 i3. 357-374.

[103]

R. Tornero, S. Kumar, S. Mubeen, J.M. Orduna, Distance constrained mapping to support NoC platforms based on source routing, in: Workshop on Highly Parallel Processing on a Chip (HPPC), 2009, pp. 8-17.

[104]

R. Tornero, V. Sterrantino, M. Palesi, J.M. Orduna, A multi-objective strategy for concurrent mapping and routing in Networks on Chip, in: IEEE International Symposium on Parallel and Distributed Processing (IPDPS), 2009, pp. 1-8.

Digital Library

[105]

M. Palesi, R. Holsmark, S. Kumar, A methodology for design of application specific deadlock-free routing algorithms for NoC Systems, in: ACM International Conference on Hardware/Software Codesign and System Synthesis, 2006, pp. 142-147.

[106]

Palesi, M., Holsmark, R., Kumar, S. and Catania, V., Application specific routing algorithms for network on chip. IEEE Transactions on Parallel and Distributed Systems. v20 i3. 316-330.

[107]

J. Hu, R. Marculescu, Energy-aware communication and task scheduling for Network-on-Chip architectures under real-time constraints, in: Design Automation and Test in Europe Conference and Exhibition, vol. 1, 2004, pp. 234-239.

[108]

Hu, J. and Marculescu, R., Communication and task scheduling of application-specific Network-on-Chip. IEE Proc. Compute. Digit. Tech. v152 i5. 643-651.

[109]

S. Stuijk, T. Basten, M. Geilen, A.H. Ghamarian, B. Theelen, Resource-efficient routing and scheduling of time-constrained Network-on-Chip communication, in: Proceedings of EUROMICRO Conference on Digital System Design, 2006, pp. 45-52.

[110]

A. Mello, N. Calazans, F. moraes, Rate-based scheduling policy for QoS Floows in network on chip, in: International Conference on Very large Scale Integration (VLSI-SoC), 2007, pp. 140-145.

[111]

A. Raina, V. Muthukumar, Traffic aware scheduling algorithm for network on chip, in: International Conference on Information Technology, 2009, pp. 877-882.

[112]

W. Hu, X. Tang, B. Xie, T. Chen, D. Wang, An efficient power-aware optimization for task scheduling on NoC-based many-core System, in: IEEE International Conference on Computer and Information Technology (CIT), 2010, pp. 171-178.

Digital Library

[113]

H. Yu, Y. Ha, B. Veeravalli, Communication-aware application mapping and scheduling for NoC-based MPSoCs, in: IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 3232-3235.

[114]

Xie, Y. and Hung, W.L., Temperature-aware task allocation and scheduling for embeded multiprocessor system-on-chip (MPSoC) design. Journal of VLSI Signal Processing. v45. 177-189.

[115]

A. Jalabert, S. Murali, L. Benini, G.D. Micheli, xpipesCompiler: a tool for instantiating application specific network on chip, in: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), 2004, pp. 884-889.

[116]

D. Bertozzi, L. Benini, xpipes: a Network-on-Chip architecture for gigascale system-on-chip, in: IEEE Circuits and Systems Magazine, 2004, pp. 18-31.

[117]

L. Bononi, N. Concer, M. Grammatikakis, NoC topology exploration based on simulation models, in: Euromicro Conference on Digital System Design Architecture, Methods and Tools (DSD), 2007, pp. 543-546.

[118]

F. Pellegrini, SCOTCH and LibScotch 4.0 User's Guide.

[119]

J. Joven, O.F. Bach, D.C. Rufas, R. Martinez, L. Teres, J. Carrabina, xENoC - an experimental Network-on-Chip environment for parallel distributed computing on NoC-based MPSoC architecture, in: Euromicro Conference on Parallel, Distributed and Network-based Processing, 2008, pp. 141-148.

[120]

J. Chan, S. Parameswaran, NoCGEN: a templet based reuse methodology for network on chip architecture, in: International Conference on VLSI Design, 2004, pp. 717-720.

[121]

E.A. Carara, R.P. de Oliveira, N.L.V. Calazans, F.G. Moraes, HeMPS - a framework for NoC based MPSoC generation, in: IEEE Symposium on Circuits and Systems (ISCAS), 2009, pp. 1345-1348.

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https://dl.acm.org/doi/10.1007/s10586-022-03919-2
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A survey on application mapping strategies for Network-on-Chip design
1. Computing methodologies
  1. Artificial intelligence
    1. Search methodologies

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Published In

cover image Journal of Systems Architecture: the EUROMICRO Journal

Journal of Systems Architecture: the EUROMICRO Journal Volume 59, Issue 1

January, 2013

77 pages

ISSN:1383-7621

Issue’s Table of Contents

Copyright © Elsevier B.V. © 2012.

Publisher

Elsevier North-Holland, Inc.

United States

Publication History

Published: 01 January 2013

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Cited By

Ramesh SManna KGogineni VChattopadhyay SMahapatra S(2024)Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337125543:8(2249-2262)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3371255
Vardi FMahjoub A(2024)A hot-module-aware mapping approach in network-on-chipThe Journal of Supercomputing10.1007/s11227-023-05424-880:1(670-702)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1007/s11227-023-05424-8
Sacanamboy M(2024)Heuristic algorithm for task mapping problem in a hierarchical wireless network-on-chip architectureCluster Computing10.1007/s10586-022-03919-227:1(159-175)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1007/s10586-022-03919-2
Hanson ELi SZhou GCheng FWang YBose RLi HChen Y(2023)Si-Kintsugi: Towards Recovering Golden-Like Performance of Defective Many-Core Spatial Architectures for AIProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614278(972-985)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614278
Jin OXing QLi YDeng SHe SPan GAamodt TJerger NSwift M(2023)Mapping Very Large Scale Spiking Neuron Network to Neuromorphic HardwareProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582038(419-432)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582038
Sambangi RPandey AManna KMahapatra SChattopadhyay S(2023)Application Mapping Onto Manycore Processor Architectures Using Active Search FrameworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.323985031:6(789-801)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3239850
Chen QHuang WHuang Y(2023)The Learnable Model-Based Genetic Algorithm for the IP Mapping ProblemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321502342:7(2350-2363)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3215023
Amin WHussain FAnjum SSaleem SBaloch NZikria YYu H(2023)Efficient application mapping approach based on grey wolf optimization for network on chipJournal of Network and Computer Applications10.1016/j.jnca.2023.103729219:COnline publication date: 1-Oct-2023
https://dl.acm.org/doi/10.1016/j.jnca.2023.103729
Gomes de Araujo Rocha HSchneider Beck AEduardo Kreutz MDiniz Monteiro Maia SMagalhães Pereira M(2023)Using evolutionary metaheuristics to solve the mapping and routing problem in networks on chipDesign Automation for Embedded Systems10.1007/s10617-023-09269-527:1-2(51-83)Online publication date: 10-Mar-2023
https://dl.acm.org/doi/10.1007/s10617-023-09269-5
Wang JTan ZYuan B(2023)Quad-Criteria Task Scheduling in Multicores Based on NSGAIIIAdvances in Swarm Intelligence10.1007/978-3-031-36622-2_19(229-241)Online publication date: 14-Jul-2023
https://dl.acm.org/doi/10.1007/978-3-031-36622-2_19
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